Scan converter with interpolating function

[0002] 1. Field of the Invention

[0003] This invention relates to a scan converter with an interpolating function.

[0004] This application is based on Japanese Patent Application No. Hei 10-208259, the contents of which are incorporated herein by reference.

[0005] 2. Background Art Including Information Disclosed Under 37 CFR 1.97 and 1.98

[0006] In general, scan converter circuits for converting the scan mode have become widely used, for example, to display a computer format video signal on a television monitor, or to record the computer format video signal on a video tape recorder. The scan system of the standard computer format video signal such as VGA or Super VGA (SVGA) differs from that of the general television signal such as NTSC (National Television System Committee) or PAL (Phase Alternation by line). Because these scan systems employ different scan frequencies, a frame buffer for temporarily storing video data is required to convert the scan mode.

[0007] Further, VGA and SVGA employ the non-interlaced scan (progressive scan) system while NTSC and PAL employ the interlaced scanning system. To avoid deterioration of the image quality after the conversion of the scan frequency, images must be interpolated. The interpolation requires a plurality of line buffers which can store data for one horizontal line.

[0008] Japanese Unexamined Patent Application, First Publication No. Hei 7-225562 discloses the scan converter using the frame buffer and the line buffers. Japanese Unexamined Patent Applications, First Publication Nos. Hei 6-105229, 7-212652, 10-098694, and 10-126748 also disclose the scan converter.

[0009] However, the above background technique using the frame buffer and the line buffers increases the scale of the circuitry. That is, the frame buffer and the line buffers must be semiconductor memories with large storage capacities because a video signal generally includes a large amount of data. The frame buffer and the line buffers with the large storage capacities increase the scale of the circuitry, the size of the device, and the costs.

[0010] It is therefore an object of the present invention to provide a scan converter with an interpolating function which reduces the scale of the circuitry.

[0011] In one aspect of the present invention, the scan converter with an interpolating function comprises: a plurality of frame buffers for dividing and storing video data of a first scan system and for reading the video data at a timing in accordance with a second scan system; and an interpolator for performing interpolation in the vertical direction for the video data read from the frame buffers.

[0012] In another aspect of the present invention, the scan converter with an interpolating function comprises: a high speed readable frame buffer for storing video data of a first scan system and for reading a plurality of pixel video data at a timing in accordance with a second scan system within a time to display one pixel; a plurality of temporary memories for temporarily storing the neighboring pixel video data read from the frame buffer; and an interpolator for performing interpolation in the vertical direction for the video data read from the frame buffers.

[0013] According to the present invention, the scan converter with the interpolating function can reduce the scale of the circuitry because it does not need a line buffer.

[0014] FIG. 1 is a block diagram showing the first embodiment of the scan converter with an interpolating function according to the present invention.

[0015] FIG. 2 is a block diagram showing in detail the structure of an interpolator in the first embodiment of the present invention.

[0016] FIG. 3 is a block diagram showing the second embodiment of the scan converter with an interpolating function according to the present invention.

[0017] The best mode of the scan converter with the interpolating function, according to an embodiment of the present invention, will be explained.

[0018] [First Embodiment]

[0019] The first embodiment of the present invention will be explained with reference to FIGS. 1 and 2.

[0020] FIG. 1 is a block diagram showing the construction of the first embodiment. Reference numeral 1 denotes a write controller, reference numerals 2A to 2C denote frame buffers, reference numeral 3 denotes a read controller, and reference numeral 4 denotes an interpolator. The write controller 1 controls a process to write a video data 10 to the frame buffers 2A to 2C. The video data 10 is a computer format video signal (digital signal), such as a VGA or SVGA signal, in the non-interlaced scan system.

[0021] Each frame buffer 2A to 2C has a memory capacity sufficinet to store ⅓ of the image undergoing the scan conversion process, and stores the video data 10. The read controller 3 controls a process to read the video data 21 to 23 from the frame buffers 2A to 2C, and reads the video data 21 to 23 at the timing of an NTSC signal, a PAL signal, or a television signal.

[0022] The interpolator 4 interpolates the video data 21 to 23 read by the read controller 3, and outputs converted data 30 with a scan frequency in an interlaced mode according to the NTSC or PAL signal format.

[0023] FIG. 2 is a block diagram showing the structure of the interpolator 4 in detail. The interpolator 4 comprises multipliers 5A to 5C, an adder 6, and a divider 7.

[0024] The video data 21 to 23 are neighboring each other in the vertical direction. The multipliers 5A to 5C increase the video data 21 to 23 by a factor of two or outputs the data as they are, to produce the video data 21a,22a,and 23a.The adder 6 adds up the video data 21ato 23ato produce the video data 24. The divider 7 divides the video data 24 by, for example, 4, to produce converted video data 30. For example, the multiplier 5 simply comprises a one-bit left shifter and a selector, and the divider 7 also simply comprises a 2-bit right shifter.

[0025] The operation of the first embodiment will now be explained.

[0026] The write controller 1 writes one horizontal line of the video data 10 at a time at a scan timing for the personal computer video signal to the frame buffers 2A, 2B, and 2C. For instance, the first line, the fourth line, the seventh line, . . . , the (3n+1) line are written in the frame buffer 2A. The second line, the fifth line, the eighth line, . . . , the (3n+2) line are written in the frame buffer 2B. The third line, the sixth line, the ninth line, . . . , the 3n line are written in the frame buffer 2C. Here, n is a nonnegative integer.

[0027] On the other hand, the read controller 3 reads the video data 21 to 23 from the frame buffers 2A, 2B, and 2C at a scan timing for the NTSC or PAL signal. For example, when reading the M line of the video data, the data of the (M−1) line, the M line, and the (M+1) line are simultaneously read out. The simultaneity is achieved because the video data 21 to 23 are written in the different frame buffers 2A, 2B, and 2C by the write controller 1.

[0028] The video data 21 to 23 successive in the vertical direction are input to the interpolator 4. The interpolator 4 generates, based on the video data 21 to 23, the converted video data 30 through a predetermined processing.

[0029] Specifically, the interpolator 4 performs interpolation for one pixel based on two dots above and below the target pixel in the vertical direction. That is, from pixel data F(m) in the m line, pixel data F(m−1) in the (m−1) line, and pixel data F(m+1) in the (m+1) line, the interpolated video data F′(m) is obtained by a weighting of 1:2:1, from the equation:

[0030] F′(m)={F(m−1)+2F(m)+F(m+1)}/4

[0031] The multipliers 5A to 5C can select a 1x mode or an 2x mode. The video data 21 to 23 are the data of the (m−1) line, the m line, and the (m+1) line. By switching only the multiplier for the data of the m line (for example, the multiplier 5B) to the x2 mode while switching the other multipliers 5A and 5C to the x1 mode, the above weighting is obtained.

[0032] The weighted outputs 21a,21b,and 21cfrom the multipliers 5A to 5C are added up by the adder 6, and the output from the adder 6 is divided by 4 by the divider 7. Thus, the interpolated video data F′(m) can be obtained.

[0033] In the first embodiment, the scan converter having an interpolating function can be constructed without a line buffer and without increasing the capacities of the frame buffers, reducing the scale of the circuity.

[0034] [Second Embodiment]

[0035] Next, the second embodiment of the present invention will be explained with reference to FIG. 3. In FIG. 3, reference numerals which are identical to those of FIG. 1 indicate elements which are identical to those of the first embodiment, therefore, explanations thereof will be omitted.

[0036] As shown in FIG. 3, instead of the frame buffers 2A to 2C, the second embodiment has one frame buffer 2D and three temporary memories 8A to 8C. The frame buffer 2D is a high speed memory which can perform more than three read operations within one pixel time for a TV signal (a time required to display one pixel). The frame buffer 2D has a storage capacity sufficient to store data for one image. The write controller 1A writes the video data 10 to a frame buffer 2D at the timing for a computer format video signal. The read controller 3A reads the video data from the frame buffer 2D at a timing for a TV signal.

[0037] When reading pixel data at the coordinates (X, Y) on the image from the frame buffer 2D, the read controller 3A also reads data of the two neighboring points (X, Y−1) and (X, Y+1), and stores the data in the temporary memories 8A to 8C each of which can store data for one pixel. The frame buffer 2D is a high speed memory, and reads the data of the three pixels within one pixel time.

[0038] The video data 21 to 23 stored in the temporary memories 8A to 8C is simultaneously read and are input to the interpolator 4, which produces the converted video data 30. The second embodiment requires only one frame buffer, thereby reducing the number of parts and the cost.

[0039] According to the present invention, the scan converter with the interpolating function can reduce the scale of the circuitry because it does not need a line buffer.

[0040] This invention may be embodied in other forms or carried out in other ways without departing from the spirit thereof. The present embodiments are therefore to be considered in all respects illustrative and not limiting, the scope of the invention being indicated by the appended claims, and all modifications falling within the meaning and range of equivalency are intended to be embraced therein.