Semiconductor device and method of forming a semiconductor structure to provide electrostatic discharge protection

[0002] This application is related to U.S. patent applications entitled Zener Diode And RC Network Combination Semiconductor Device For Use In Integrated Circuits and Method Therefor and RC Networks In Semiconductor Devices And Method Therefor, which are filed concurrently with the present U.S. patent application. The present U.S. patent application and the related Applications are assigned to the same assignee.

[0003] 1. Field of the Invention

[0004] This invention generally relates to semiconductor devices and integrated circuits that require electrostatic discharge (hereinafter referred to as “ESD”) protection. In typical electrical circuits, such devices include Resistor-Capacitor (hereinafter referred to as “RC”) or Resistor-Capacitor-Inductor (hereinafter referred to as “RCL”) networks and fabrication methods therefor. Specifically, this invention relates to an improved semiconductor device and a method for manufacturing such an improved semiconductor device which provides protection against ESD for active or passive devices or any type of integrated circuit.

[0005] 2. Description of the Related Art

[0006] In the past art, the primary method for integrating protection of ESD in RC Network types of semiconductor devices was to use or incorporate certain types of diodes, i.e. Schottky diodes and Zener diodes to provide for ESD protection. For example, Rao et al. (U.S. Pat. Nos. 5,355,014 and 5,770,886) employs a Schottky diode for ESD protection.

[0007] However, one primary disadvantage of the use of a Schottky/Zener diode technique for ESD protection is the added complexity of the process flow for manufacturing these fairly complicated semiconductor devices. The prior art semiconductor process for fabricating these types of semiconductor devices usually required an epitaxy growth process step to obtain or form regions of P type conductivity, formation of the LOCOS field isolation and formation of a multi-layer metalization system on the backside of the semiconductor wafer.

[0008] Therefore, a simpler, more cost effective and more reliable semiconductor device and semiconductor process solution was needed or required as contrasted to both the semiconductor device and process complexity incurred by the incorporation of Schottky/Zener diodes to provide ESD protection for use with, for example, RC network semiconductor devices.

[0009] It is an object of the present invention to provide an improved semiconductor structure and method for protecting an active or passive device against ESD.

[0010] It is another object of the present invention to provide an improved semiconductor structure and method for protecting an integrated circuit device against ESD.

[0011] It is another object of the present invention to provide an improved semiconductor structure and method for protecting an active or passive network against ESD which provides a simpler, more cost effective and more reliable solution than the prior use of a Schottky diode for ESD protection.

[0012] It is still another object of the present invention to provide an improved semiconductor structure and method for protecting an active or passive network against ESD which provides a simpler, more cost effective and more reliable solution than a Zener diode for ESD protection.

[0013] It is a further object of the present invention to provide an improved semiconductor structure for protecting an active or passive network against ESD which utilizes a simpler, more cost effective and more reliable type of semiconductor device structure which is an improved diode comprising an anode, cathode and injector.

[0014] In accordance with one embodiment of the present invention, a semiconductor diode is provided for protection of active or passive devices against electrostatic discharge comprising a P well cathode located within an N type substrate, an N+ type anode region located within the P well cathode, an N+ type injector region located within the P well cathode and spaced from the N+ type anode region, a P+ type ohmic contact region located within the P well cathode and in contact with the N+ type injector region, a first metal electrode in electrical contact with a surface portion of the N+ type anode region, and a second metal electrode in electrical contact with surface portions of both the N+ type injector region and the P+ type ohmic contact region which are adjacent and co-planar to each other. The improved diode is preferably fabricated in a single, monolithic integrated circuit made of silicon.

[0015] In accordance with another embodiment of the invention, a method is disclosed for fabricating a semiconductor device structure for protection of active or passive devices against ESD which comprises the steps of forming a P well cathode located within an N type substrate, forming an N+ type anode region located within the P well cathode, forming an N+ type injector region located within the P well cathode and spaced from the N+ type anode region, forming a P+ type ohmic contact region located within the P well cathode and in contact with the N+ type injector region, forming a first metal electrode in electrical contact with a surface portion of the N+ type anode region, and forming a second metal electrode in electrical contact with surface portions of both the N+ type injector region and the P+ type ohmic contact region which are adjacent and co-planar to each other.

[0016] The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.

[0017] FIG. 1 is a cross sectional view of the semiconductor structure of the present invention in an early stage of the fabrication process depicting a P well cathode in an N type substrate, a silicon dioxide layer located on a surface thereof with apertures therein and spaced apart N+ type regions in the P well cathode.

[0018] FIG. 2 is a cross sectional view of a later stage in the fabrication process in forming the semiconductor structure of the present invention showing a subsequent addition of a photoresist layer with an aperture therein and through the underlying portion of silicon dioxide to permit the formation in the P well cathode of a P+ type ohmic contact region.

[0019] FIG. 3 is a cross sectional view of a still later stage in the fabrication process in forming the semiconductor structure of the present invention after the photoresist layer is removed and a silicon nitride layer is deposited and after a heat treatment diffusion drive-in operation is used to create the desired depth of the two N+ regions and the P+ region, respectively, comprising the anode, injector and ohmic contact regions in the P well cathode.

[0020] FIG. 4 is a cross sectional view of the completed semiconductor diode structure of the present invention showing openings in the silicon nitride layer and a first metal electrode in electrical contact to the N+ anode region and a second metal electrode in electrical contact to both the N+ injector and P+ ohmic contact regions in the P well cathode.

[0021] Referring to FIG. 1, a relatively early phase in the fabrication process of forming the semiconductor structure of the present invention is illustrated. The starting N type silicon substrate 10 contains N type impurities such as arsenic, phosphorous, etc. The substrate 10 is doped to a desired level to provide optimum electrical characteristics for a starting N type substrate.

[0022] Initially a P type well cathode 20 is implanted or diffused into the N type substrate 10. The P type well cathode 20 contains P type impurities such as boron. The P type well cathode 20 is doped to a desired level to provide optimum electrical characteristics for a P type well.

[0023] Subsequently, a silicon dioxide layer 30 is thermally grown or deposited on the surface of the substrate 10. Standard semiconductor photolithography, i.e. masking and etching using photoresist (not shown), is used to create two apertures in the oxide layer 30 which openings are spaced apart. Subsequently two N+ type regions 41 and 42 are created in the P type well cathode 20 below the two apertures in the oxide layer 30 by ion implantation or diffusion techniques using an N type impurity. The N+ type region 41 forms the anode of a semiconductor diode device as shown in FIG. 4. The N+ type region 42 forms the injector for the semiconductor diode device as shown in FIG. 4.

[0024] Referring to FIG. 2, a later phase in the semiconductor process for forming the semiconductor structure of the present invention is illustrated. A photoresist (PR) layer 44 is initially deposited over the surface of the semiconductor structure of FIG. 1. Then a single aperture is etched through both the photoresist layer 44 and the underlying portion of the silicon dioxide layer 30 by using photolithographic masking and etching techniques to permit ion implantation or diffusion of a P+ type ohmic contact region 60 into the P type well cathode 20. The P+ type ohmic contact region 60 is preferably adjacent to and in contact with the N+ type injector region 42. The P+ type ohmic contact region 60 is formed to obtain better ohmic contact with the P well cathode 20 as subsequently shown in FIG. 4.

[0025] Referring to FIG. 3, another subsequent phase in the process for fabricating the semiconductor structure of the present invention is shown. After the photoresist layer 44 (see FIG. 2) is removed, a silicon nitride deposition operation is conducted to deposit a silicon nitride layer 50. The semiconductor structure is annealed or heat treated at a sufficiently high temperature to drive in the various regions 41, 42 and 60 in the surface portion thereof. Subsequent to the heat treatment, the regions 41, 42 and 60 have a greater depth as shown in FIG. 3 in contrast to the depth as shown in FIG. 2.

[0026] Referring to FIG. 4, the completed semiconductor structure and device of the present invention is illustrated. In completing the semiconductor structure, two apertures are etched or formed into the silicon nitride layer 50. The first aperture is etched or formed directly over the N+ type anode region 41. The second aperture is etched or formed directly over, and spanning a portion of both sides of the P-N junction interface of the N+ type injector region 42 and the P+ type ohmic contact region 60. Then, a metal electrode layer, comprising aluminum or an aluminum alloy in the preferred embodiment, is deposited over the nitride layer 50. The metal layer is etched by using photolithographic masking and etching techniques to form an opening therein thereby providing a first metal electrode 68 that makes electrical contact with the N+ type anode region 41 (by penetrating through an aperture previously formed in the silicon nitride layer 50 over the N+ type anode region 41). The deposited metal layer also provides a second metal electrode 70 that makes electrical contact with both the N+ type injector region 42 and the P+ type ohmic contact region 60 by penetrating through a previously formed aperture in the silicon nitride layer 50 over surface portions of the N+ type injector region 42 and the P+ type ohmic contact region 60. Since aluminum tends to create an N type surface inversion, the P+ type ohmic contact region 60 permits a more reliable ohmic contact to be made to the P well cathode 20.

[0027] The creation of the N+ type injector region 42 located adjacent to the P+ type ohmic contact region 60 and electrically connected to each other by means of the second metal electrode 70 contacting each of these two regions across the P-N junction between these two regions together with the N+ type anode region 41 serve when combined with the P well cathode region 20 as a protective diode for ESD while simultaneously significantly reducing dimensions as compared to prior art ESD protective devices.

[0028] When the breakdown current increases, the N+ type injector 42 begins to introduce minority carriers. By increasing conductivity of the semiconductor diode device, the maximum current that the semiconductor diode can carry without realizing damage is increased. Therefore, with the semiconductor device of the present invention, the high current generated by ESD can be effectively controlled.

[0029] Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.