Hierarchical bus structure data processing apparatus and method with reduced data transfer volume

[0002] 1. Field of the Invention

[0003] This invention relates to a data processing apparatus with an input/output (I/O) device and a data processing method.

[0004] 2. Description of the Related Art

[0005] An I/O device, e.g., disk controller, network controller, etc. is usually connected to a bus. Since the number of devices connectable to a bus is restricted by an electrical condition of the bus, number of control signals, etc., the number of the devices connected to the bus is limited.

[0006] The number of devices connectable to the bus can be increased by layering the bus. The layered bus is called as a hierarchical bus, hereinafter. In the hierarchical bus, a bus coupler is provided between a bus at an upper layer and a bus at a lower layer. The bus coupler relays data from a bus to an appropriate bus based on a destination address of the data transmitted in the bus.

[0007] FIG. 23 illustrates a data transfer system with the hierarchical bus according to the related art. In FIG. 23, disk controllers and magnetic disk drives (or also called as disk drives, hereinafter) controlled by the disk controllers are provided as the I/O devices for example. Normally, an origin or destination of a data transfer is a main memory, and the main memory is shared by all the I/O devices. Therefore, the main memory is connected to a top layer in the hierarchical bus.

[0008] Operations are explained with reference to FIG. 23.

[0009] Data in files 61a-61fin disk drives 8a-8fare transferred to buffers 10a-10fin a main memory 2, and processed by a central processing unit (CPU) 1.

[0010] The CPU 1 requests a disk controller 7ato transfer the data in the file 61ain the disk drive 8ato the buffer 10a. The disk controller 7atransfers the data to an I/O bus 5a.An I/O bus coupler 6arelays the data from the I/O bus 5ato an I/O bus 5d.A system bus-I/O bus coupler 4 relays the data from the I/O bus 5dto a system bus 3. Then, the data are stored in the buffer 10ain the main memory 2.

[0011] The CPU 1 also requests a disk controller 7bto transfer the data in the file 61bin the disk drive 8bto the buffer 10b.The disk controller 7btransfers the data to the I/O bus 5a.The I/O bus coupler 6arelays the data from the I/O bus 5ato the I/O bus 5d.The system bus-I/O bus coupler 4 relays the data from the I/O bus 5dto the system bus 3. Then, the data are stored in the buffer 10bin the main memory 2.

[0012] The CPU 1 also requests a disk controller 7cto transfer the data in the file 61cin the disk drive 8cto the buffer 10c.The disk controller 7ctransfers the data to an I/O bus 5b.An I/O bus coupler 6brelays the data from the I/O bus 5bto the I/O bus 5d. The system bus-I/O bus coupler 4 relays the data from the I/O bus 5dto the system bus 3. Then, the data are stored in the buffer 10cin the main memory 2.

[0013] The CPU 1 also requests a disk controller 7dto transfer the data in the file 61din the disk drive 8dto the buffer 10d.The disk controller 7dtransfers the data to the I/O bus 5b.The I/O bus coupler 6brelays the data from the I/O bus 5bto the I/O bus 5d.The system bus-I/O bus coupler 4 relays the data from the I/O bus 5dto the system bus 3. Then, the data are stored in the buffer 10din the main memory 2.

[0014] The CPU 1 also requests a disk controller 7eto transfer the data in the file 61ein the disk drive 8eto the buffer 10e.The disk controller 7etransfers the data to an I/O bus 5c.An I/O bus coupler 6crelays the data from the I/O bus 5cto the I/O bus 5d.The system bus-I/O bus coupler 4 relays the data from the I/O bus 5dto the system bus 3. Then, the data are stored in the buffer 10ein the main memory 2.

[0015] The CPU 1 also requests a disk controller 7fto transfer the data in the file 61fin the disk drive 8fto the buffer 10f.The disk controller 7ftransfers the data to the I/O bus 5c.The I/C bus coupler 6crelays the data from the I/O bus 5cto the I/O bus 5d.The system bus-I/O bus coupler 4 relays the data from the I/C bus 5dto the system bus 3. Then, the data are stored in the buffer 10fin the main memory 2.

[0016] The CPU 1 processes the data transferred to the buffers 10a-10f,and stores a result from processing in a last output buffer 101.

[0017] As stated, the data are always transferred to the main memory 2 via the I/O bus 5d,system bus-I/O bus coupler 4, and system bus 3. The data transferred from all the I/O devices connected at lower layers in the hierarchical bus are channeled through the buses at upper layers in the hierarchical bus.

[0018] However, since data transfer in a bus per unit time is generally limited, data exceeding the limit cannot be transferred.

[0019] When a bus is occupied for a transfer of data, even if a transfer of other data is requested, the latter data cannot be transferred until the first data transfer is completed. When the data in the files 61a-61eare transferred at once, transfer speed of the data is restricted by transfer speeds of data in the I/O bus 5dand system bus 3. Therefore, even if the number of connectable devices is increased by adopting the hierarchical bus, the data transfer speed of the system is restricted by the transfer speed of the bus at the top layer. Hence, a data transfer speed appropriate for the number of devices cannot be realized.

[0020] In the hierarchical bus according to the related art, the CPU 1 processes all the data. Since the data processed by the CPU per unit time period is limited, data exceeding the limit cannot be processed. When the CPU 1 processes the data transferred from the files 61a-61e,a processing speed of the data is restricted by the processing speed of the CPU 1. Even if the number of connectable devices is increased by adopting the hierarchical bus, the processing speed of the system is restricted by the processing speed of the CPU, and the data processing speed appropriate for the number of devices cannot be realized.

[0021] The hierarchical bus according to the related art is configured as above stated, and all the transferred data are channeled through the buses at upper layers. Therefore, even if the number of connectable devices is increased, an appropriate data transfer speed cannot be realized.

[0022] The hierarchical bus according to the related art is configured as above stated, and the processing speed of data is restricted by the processing speed of the CPU. Therefore, even if the number of connectable devices is increased, an appropriate processing speed cannot be realized.

[0023] It is an object of this invention to solve the above-stated problems in the related art. Particularly, this invention aims at increasing the number of connectable devices by adopting a hierarchical bus and improving a transfer speed when the number of the devices is increased.

[0024] This invention also aims at increasing the number of connectable devices by adopting the hierarchical bus and improving processing speed when the number of the devices is increased.

[0025] According to one aspect of this invention, a data processing apparatus includes an upper bus and a lower bus connected hierarchically, a memory connected to the upper bus, a device connected to the lower bus, a processor, connected to the lower bus, for receiving data from the device via the lower bus, extracting a part of the received data, and transferring the extracted data to the memory via the upper bus, and a processing unit connected to the upper bus for processing the transferred data in the memory.

[0026] According to another aspect of this invention, a data processing method includes the steps of transferring data from the device to the processor via the lower bus, extracting a part of the transferred data by the processor, transferring the extracted data to the memory via the upper bus, and processing the transferred data in the memory by the processing unit.

[0027] Further features and applications of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

[0028] Other objects features, and advantages of the invention will be apparent from the following description when taken in conjunction with the accompany drawings.

[0029] FIG. 1 shows a system configuration chart in an embodiment of this invention;

[0030] FIG. 2 shows a configuration chart of a system bus-I/O bus coupler in an embodiment of this invention;

[0031] FIG. 3 shows a configuration chart of an I/O bus coupler in an embodiment is invention;

[0032] FIG. 4 shows a configuration chart of a processor in an embodiment of this invention;

[0033] FIG. 5 illustrates an address distribution in a physical address space in and embodiment of this invention;

[0034] FIG. 6 illustrates an address translation by a processor in an embodiment of this invention;

[0035] FIG. 7 illustrates a configuration of a file in an embodiment of this invention;

[0036] FIG. 8 illustrates a configuration of a block constituting a file in an embodiment of this invention;

[0037] FIG. 9 illustrates a sample of a first accumulation and a result from the first accumulation in an embodiment of this invention;

[0038] FIG. 10 illustrates an internal configuration in a first accumulation in an embodiment of this invention;

[0039] FIG. 11 illustrates a sample of a selection—projection processing and its result from the selection—projection processing in an embodiment of this invention;

[0040] FIG. 12 illustrates a sample of aback accumulation processing and its result from the first accumulation in an embodiment of this invention;

[0041] FIG. 13 illustrates a sample of a second accumulation and its result from the second accumulation in an embodiment of this invention;

[0042] FIG. 14 illustrates an accumulation processing in an embodiment of this invention;

[0043] FIG. 15 shows a flow chart of operations in an embodiment of this invention;

[0044] FIG. 16 shows a system configuration chart in another embodiment of this invention;

[0045] FIG. 17 shows a configuration chart of an I/O bus coupler with a processor in another embodiment of this invention;

[0046] FIG. 18 shows a system configuration chart in another embodiment of this invention;

[0047] FIG. 19 illustrates an accumulation processing in another embodiment of this invention;

[0048] FIG. 20 illustrates an accumulation processing in another embodiment of this invention;

[0049] FIG. 21 shows a flow chart of operations in another embodiment of this invention;

[0050] FIG. 22 illustrates a hierarchical accumulation processing in another embodiment of this invention; and

[0051] FIG. 23 shows a system configuration chart according to the related art.

[0052] FIG. 1 illustrates a configuration of a system for realizing an embodiment of this invention.

[0053] In FIG. 1, the central processing unit (CPU) 1 controls each unit in the whole system. The main memory 2 is also illustrated. The system bus 3 is a channel for a data transfer between the CPU 1 and the main memory 2 and a data transfer between the system bus—I/O bus coupler 4 and the main memory 2. The system bus-I/O bus coupler 4 relays data transferred between a device connected to an I/O bus and a device connected to the system bus. An I/O device, e.g., disk controller, etc. or bus coupler is connected to the I/O buses 5a-5d.The I/O buses 5a-5dare controlled in a different procedure from the system bus 3. Each of the I/O bus couplers 6a-6cis connected to two of the I/O buses for relaying the data transferred between I/O devices or bus couplers connected to the different I/O buses. The system bus 3 and all the I/O buses 5a-5dare assumed to have the same physical address space.

[0054] Each of I/O devices 102a-102fincludes a disk controller and a magnetic disk drive. The disk controllers 7a-7fcontrol the magnetic disk drives (or also called as disk drives) 8a-8frespectively. Processors 9a-9care provided. The buffers 10a-10care provided in the main memory 2. The files 61a-61fare stored in the disk drives 8a-8frespectively. The last output buffer 101 is also provided in the main memory 2.

[0055] FIG. 2 illustrates a configuration of the system bus-I/O bus coupler 4 according to this embodiment.

[0056] In FIG. 2, the system bus 3 and the I/O bus 5dare illustrated. A system bus interface 11, an I/O bus interface 12, and buffers 11 and 14 are also illustrated. When data are transferred from the I/O bus 5dto the system bus 3, the data are stored in the buffer 13 temporarily. When data are transferred from the system bus 3 to the I/O bus 5d,the data are stored in the buffer 14 temporarily. A physical address range of the I/O bus 5dis stored in an I/O bus physical address range register 15. A physical address can be assigned to the I/O bus 5dby providing the physical address range of the I/O bus 5din the I/O bus physical address range register 15.

[0057] When a request for transfer of the physical address range provided in the I/O bus physical address range register 15 is transmitted to the system bus 3, the system bus-I/O bus coupler 4 responds to the request. If the request is a transfer of data from the system bus 3 to the I/O bus 5d,the system bus interface 11 responds to the request in the system bus 3, and stores the data sent from the system bus 3 in the buffer 14. Then, the data are transferred to the I/O bus 5dvia the I/O bus interface 12. If the request is a transfer of data from the I/O bus 5dto the system bus 3, the I/O bus interface 12 relays the request for transfer of the address range assigned to the I/O bus 5d,and receives transferring data from the I/O bus 5d.Then, the data are stored in the buffer 13, and transferred to the system bus 3 via the system bus interface 11. The system bus-I/O bus coupler 4 does not respond to a request for transfer in the system bus 3 for a physical address range which is not provided in the I/O bus physical address range register 15.

[0058] However, when a request for transfer of a physical address range which is not provided in the I/O bus physical address range register 15 is transferred to the I/O bus 5d,the system bus-I/O bus coupler 4 responds to the request If the request is a transfer of data from the I/O bus 5dto the system bus 3, the I/O bus interface 12 responds to the request in the I/O bus 5d,and stores the data sent from the I/O bus 5din the buffer 13. Then, the data are transferred to the system bus 3 via the system bus interface 11. If the request is a transfer of data from the system bus 3 to the I/O bus 5d,the system bus interface 11 relays the request for transfer of the address range assigned to the system bus 3, and receives the data from the system bus 3. Then, the data are stored in the buffer 14, and transferred to the I/O bus 5dvia the I/O bus interface 12. The system bus-I/O bus coupler 4 does not respond to a request for transfer in the I/O bus 5dfor a physical address range which is provided in the I/O bus physical address range register 15.

[0059] FIG. 3 illustrates a configuration of the I/O bus coupler 6aaccording to this embodiment. The configuration of the I/O bus couplers 6band 6care the same as FIG. 3.

[0060] In FIG. 3, the I/O bus 5dvat an upper layer and the I/O bus 5aat a lower layer are illustrated. An upper bus interface 21, a lower bus interface 22, and buffers 23 and 24 are also illustrated. Data transferred from the I/O bus 5aat the lower layer to the I/O bus 5dat the upper layer is temporarily stored in the buffer 23. Data transferred from the I/O bus 5dat the upper layer to the I/O bus 5aat the lower layer is temporarily stored in the buffer 24. A physical address range of the I/O bus 5aat the lower layer is stored at a lower layer I/O bus physical address range register 25 temporarily. A physical address can be assigned to the I/O bus 5aat the lower layer by providing a physical address range of the I/O bus 5aat the lower layer in the I/O bus physical address range register 25.

[0061] The I/O bus coupler 6aresponds to the request for transfer of the data in the I/O bus 5dat the upper layer for a physical address range provided in the lower layer I/O bus physical address range register 25. If the request is a transfer of the data from the I/O bus 5dat the upper layer to the I/O bus 5aat the lower layer, the upper bus interface 21 responds to the request for transfer of the data in the I/O bus 5dat the upper layer, and stores the data transferred from the I/O bus 5dat the upper layer in the buffer 24. Then, the data are transferred to the I/O bus 5avia the lower bus interface 22. If the transfer of the data is from the I/O bus 5aat the lower layer to the I/O bus 5dat the upper layer, the lower bus interface 22 relays the request for transfer of the concerned address to the I/O bus 5d,and receives the transferred data from the I/O bus 5aat the lower layer. Then, the data are stored in the buffer 23. The data are transferred to the I/O bus 5dat the upper layer via the upper bus interface 21. The I/O bus coupler 6adoes not respond to a request for transfer of a physical address range which is not provided in the I/O bus physical address range register 25 in the I/O bus at the upper layer.

[0062] The system bus-I/O bus coupler 4 responds to a request for transfer in the I/O bus 5aat the lower layer for the physical address range besides the physical address range provided in the lower layer I/O bus physical address range register 25.

[0063] If the transfer of the data is from the I/O bus 5aat the lower layer to the I/O bus 5dat the upper layer, the lower bus interface 22 responds to the request for transfer of the data in the I/O bus 5aat the lower layer, and stores the data transferred from the I/O bus 5aat the lower layer in the buffer 23. Then, the data are transferred to the I/O bus 5dat the upper layer via the upper bus interface 21. If the transfer of the data is from the I/O bus 5dat the upper layer to the I/O bus 5aat the lower layer, the upper bus interface 21 relays the request for transfer of the concerned address to the I/O bus 5dat the upper layer, and receives the transferring data from the I/O bus 5dat the upper layer. The data are stored in the buffer 24 once, and transferred to the I/O bus 5aat the lower layer via the lower bus interface 22. The I/O bus coupler 6adoes not respond to a request for transfer for the physical address range provided in the lower layer I/O bus physical address range register 25.

[0064] FIG. 4 illustrates a configuration of the processor 9aaccording to this embodiment. Configuration of the processors 9band 9care the same as in FIG. 4.

[0065] In FIG. 4, the I/O bus 5ais illustrated. The processor 9ais connected to the I/O bus 5a.An I/O bus-local bus coupler 30 is provided for performing a data transfer between an I/O device or bus coupler connected to the I/O bus and a microprocessor 32, local memory 33 or DMA (Direct Memory Access) controller 36 connected to a local bus 31. The local bus 31 has a local address space different from the I/O bus 5a.The microprocessor 32 and the local memory 33 are also illustrated. The local memory 33 functions as a main memory of the microprocessor 32. An address translator 34 performs an address translation of the physical address in the I/O bus 5aand a local address in the local bus 31 for performing a data transfer between the I/O bus 5aand the local bus 31, which have different address spaces. A physical address range register 35 is also illustrated. A physical address range can be assigned to the processor 9aby providing the physical address range in the physical address range register 35. Input buffers 37aand 37bare provided in the local memory 33, and output buffer 38aand 38bare provided in the local memory 33.

[0066] FIG. 5 illustrates an address distribution in a physical address space according to this embodiment.

[0067] A whole physical address space 41 is illustrated. A physical address range 42 in the physical address space is assigned to the system bus 3, and a physical address range 43 in the physical address space is assigned to the main memory 2.

[0068] In FIG. 5, a physical address range 44ain the physical address space is assigned to the I/O bus 5a.A physical address range 45ain the physical address range 44aof the I/O bus 5ais assigned to the processor 9a.Physical address ranges 46aand 46bin the physical address range 45aof the processor 9aare assigned to the input buffers 37aand 37bin the local memory 33. Physical address ranges 47aand 48bin the physical address range 45aof the processor 9aare assigned to the output buffer 38aand 38bin the local memory 33.

[0069] In FIG. 5, a physical address range 44bin the physical address space is assigned to the I/O bus 5b.A physical address range 45bin the physical address range 44bof the I/O bus 5bis assigned to the processor 9b.Physical address ranges 46cand 46din the physical address range 45bof the processor 9bare assigned to the input buffers 37aand 37bin the local memory 33. Physical address ranges 47cand 47din the physical address range 45bof the processor 9bare assigned to the output buffers 38aand 38bin the local memory 33.

[0070] In FIG. 5, a physical address range 44cin the physical address space is assigned to the I/O bus 5c.A physical address range 45cin the physical address range 44cof the I/O bus 5cis assigned to the processor 9c.Physical address ranges 46eand 46fin the physical address range 45cof the processor 9care assigned to the input buffers 37aand 37bin the local memory 33. Physical address ranges 47eand 47fin the physical address range 45cof the processor 9care assigned to the output buffers 38aand 38bin the local memory 33.

[0071] In FIG. 5, a physical address range 48ain a physical address range 43 of the main memory 2 is assigned to the buffer 10a.A physical address range 48bin the physical address range 43 of the main memory 2 is assigned to the buffer 10b.A physical address range 48cin the physical address range 43 of the main memory 2 is assigned to the buffer 10c.A physical address range 48din the physical address range 43 of the main memory 2 is assigned to the buffer 10d.A physical address range 48ein the physical address range 43 of the main memory 2 is assigned to the buffer 10e.A physical address range 48fin the physical address range 43 of the main memory 2 is assigned to the buffer 10f.A physical address range 48gin the physical address range 43 of the main memory 2 is assigned to the last output buffer 101.

[0072] FIG. 6 shows an address translation in the processor 9aaccording to this invention.

[0073] In FIG. 6, the physical address space 41 and the local address space 51 in the local bus 31 are illustrated. The physical address range 45aprovided in the physical address range register 35 is translated to a local address range 55 by the address translator 34. Data in the input buffer 37ais in the physical address range 46ain the physical address space 41 of the I/O bus and in a local address range 56ain the local address space 51 of the local bus at the same time. Data in the input buffer 37bis in the physical address range 46bin the physical address space 41 of the I/O bus and in a local address range 56bin the local address space 51 of the local bus at the same time. Data in the output buffer 38ais in the physical address range 47ain the physical address space 41 of the I/O bus and in a local address range 57ain the local address space 51 of the local bus at the same time. Data in the output buffer 38bis in the physical address range 47bin the physical address space 41 of the I/O bus and in a local address range 57bin the local address space 51 of the local bus at the same time.

[0074] FIG. 7 illustrates a data format of the file 61aaccording to this embodiment. Formats of the files 61b-61fare the same as the file 61a.

[0075] The file 61aincludes a plurality of blocks 62a-62d,etc. Sizes of the blocks 62a-62d,etc. and sizes of the input buffers 37aand 37bare all the same.

[0076] FIG. 8 illustrates a data format of the block 62ain the file 61aaccording to this embodiment. Formats of the blocks 62b-62d,etc. are the same as the block 62a.

[0077] In FIG. 8, the block 62aincludes a plurality of records 63a-63m,etc. Each of the records 63a-63m,etc. includes data in a key field 64, numeric field 65, date field 66, etc.

[0078] FIG. 9 illustrates a sample of a first accumulation and a result from the first accumulation.

[0079] In FIG. 9, a first accumulation 71aand a result 72afrom the first accumulation of the block 62aare illustrated. The result 72afrom the first accumulation includes first accumulation records 73a-73d.Each of the first accumulation records 73a-73dincludes data in a first accumulation key field 74 and a first accumulation numeric field 75. In this embodiment, data in the numeric field 65 with data in the date field 66 of May, 1998 are accumulated for each kind of data in the key field 64 in the first accumulation.

[0080] FIG. 10 illustrates operations in the first accumulation according to this embodiment.

[0081] In FIG. 10, the first accumulation 71ais illustrated. The block 62ais an input to the first accumulation 71a.The result 72afrom the first accumulation 71ais an output from the first accumulation 71a.The first accumulation 71aincludes steps of selection-projection 76 and block accumulation 77. A result 67 from the selection-projection 76 is an output from the selection—projection 76 and becomes an input to the block accumulation 77.

[0082] FIG. 11 illustrates a sample of the selection-projection 76 and the result 67 from the selection-projection 76 according to this embodiment.

[0083] In FIG. 11, the selection-projection 76 and the result 67 from the selection-projection 76 of the block 62aare illustrated. Post-selection-projection records 163c-163I are illustrated. Each of the post-selection-projection records 163c-163iincludes data in the key field 64 and the numeric field 65.

[0084] In this embodiment, records 63c-63iwith data in the date field 66 of May 1998 are selected, and data in the key field 64 and numeric field 65 of the records 63c-63iare extracted or projected for generating the post-selection-projection records 163c-163irespectively. The post-selection-projection records 163c-163iare the result 67 from the selection-projection.

[0085] FIG. 12 illustrates a sample of the block accumulation 77 and its result 72afrom the first accumulation according to this embodiment.

[0086] In FIG. 12, the block accumulation 77 and the result 72afrom the first accumulation, i.e., the result 72afrom the block accumulation 77 of the result 67 from the selection-projection, are illustrated. In the block accumulation 77, data in the numeric field of records are accumulated for each kind of data in the key field 65, and the first accumulation records 73a-73dare generated. In FIG. 12, the first accumulation record 73ais generated from the post-selection-projection records 163cand 163h,the first accumulation record 73bis generated from the post-selection projection records 163d,163g,and 163i,the first accumulation record 73cis generated from the post-selection-projection record 163e,and the first accumulation record 73dis generated from the post-selection-projection record 163f.

[0087] FIG. 13 illustrates a sample of a second accumulation 81 and a result 82 from the second accumulation 81 according to this embodiment.

[0088] In FIG. 13, the result 72afrom the first accumulation and a previous result 82afrom the second accumulation 81 are illustrated. The result 82 from the second accumulation of the result 72afrom the first accumulation and the previous result 82afrom the second accumulation 81 is illustrated. The previous result 82afrom the second accumulation includes second accumulation records 83a-83d,and the result 82 from the second accumulation includes second accumulation records 83e-83i. Each of the second accumulation records 83a-83dand 83e-83iincludes data in a second accumulation key field 84 and a second accumulation numeric field 85.

[0089] FIG. 14 illustrates a sample of an accumulation processing according to this embodiment.

[0090] In FIG. 14, files 61a-61finclude blocks 62a-62d,etc. First accumulations 71a-71fof the files 61a-61fare illustrated. The first accumulations 71aand 71bare performed by the processor 9a,the first accumulations 71cand 71dare performed by the processor 9b,and the first accumulation 71eand 71fare performed by the processor 9c.The results 72a-72d,etc. from the first accumulation 71aof the blocks 62a-62d,etc. are obtained. The results from the same first accumulation, e.g., 72a-72d,etc. are generally called as a first accumulation result sequence. First accumulation result sequences 92a-92fare sets of the results from the first accumulations 71a-71f.A queue 91 for the result from the first accumulation is also illustrated. The second accumulation 81 and the result 82 from the second accumulation 81 are also illustrated.

[0091] FIG. 15 shows a flow chart of operation of an accumulation processing according to this embodiment. The operations are shown in steps S0-S8.

[0092] Operations are explained.

[0093] For a purpose of explanation of this embodiment, data in the numeric field 65 are accumulated for each kind data in the key field 64 in the files 61a-61fstored in the magnetic disk drives 8a-8f,and the result 82 from the second accumulation is obtained as a final processing result.

[0094] The CPU 1 provides the physical address range 44ain the lower layer I/O bus physical address range register 25 in the I/O bus coupler 6aat a time of initializing a system. The CPU 1 also provides the physical address range 44bin the lower layer I/O bus physical address range register 25 in the I/O bus coupler 6band the physical address range 44cin the lower layer I/O bus physical address range register 25 in the I/O bus coupler 6c.

[0095] The CPU 1 also provides the physical address range 44din the I/O bus physical address range register 15 in the system bus-I/O bus coupler 4 at the time of initializing the system.

[0096] The CPU 1 also provides the physical address range 45ain the physical address range register 35 in the processor 9aat the time of initializing the system. The CPU 1 also provides the physical address range 45bin the physical address range register 35 in the processor 9band the physical address range 45cin the physical address range register 35 in the processor 9c.

[0097] By providing these addresses, the hierarchical bus as illustrated in FIG. 1 is initialized to have the physical address ranges as illustrated in FIG. 5.

[0098] Then, the accumulation operations are performed as shown in FIG. 15. The CPU 1 clears the result 82 from the second accumulation in the last output buffer 101. By doing so, no second accumulation record is included in the result 82 from the second accumulation (step S0).

[0099] Then, the CPU 1 instructs the disk controller 7ato transfer data in a first block of the file 61ain the magnetic disk drive 8ato the physical address range 46a(step S1). The disk controller 7areads the data from the file 61ain the magnetic disk drive 8a,and issues a request for transfer of the data to the physical address range 46ato the I/O bus 5a.Since the physical address range 46ais provided in the physical address range register 35 in the I/O bus-local bus coupler 30 in the processor 9a,the I/O bus-local bus coupler 30 in the processor 9aresponds to the request, and the data are transferred from the disk controller 7ato the processor 9a.When the data are transferred to the processor 9a,the data are stored in the input buffer 37ain the local memory 33 (step S2).

[0100] Since the physical address range 46ais included in the physical address range provided in the lower bus address range register in the I/O bus coupler 6a,the I/O bus coupler 6adoes not respond to the request for transfer from the disk controller 7a.

[0101] Since the data in the input buffer 37ahas the local address range 56 in the local address of the microprocessor 32, the microprocessor 32 can operate the data directly.

[0102] After the data transfer, the CPU 1 instructs the microprocessor 32 in the processor 9ato perform the first accumulation of the data in the input buffer 37aafter (step S3).

[0103] The microprocessor 32 performs the first accumulation of the data in the input buffer 37a,and outputs the result from the first accumulation to the output buffer 38a(step S4).

[0104] When the block 62aas illustrated in FIG. 8 is transferred, the result 72afrom the first accumulation as illustrated in FIG. 9 is stored in the output buffer 38a.Since a plurality of records with same data in the key field 64 is in the block 62agenerally, the size of the result 72afrom the first accumulation is reduced from the size of the block 62a.

[0105] When the first accumulation is completed, the CPU 1 starts the DMA (Direct Memory Access) controller 36 in the processor 9a,and transfers the result 72afrom the first accumulation in the output buffer 38ato the buffer 10ain the main memory 2 (step S5). In this transfer, only data in the size of the result 72afrom the first accumulation is transferred. It is not necessary to transfer all the data in the output buffer 38a.

[0106] The DMA controller 36 sends a request for data transfer through the I/O bus 5ato the destination in the physical address range 48ain the buffer 10ain the main memory 2 (step S6). Since the physical address range 44ais provided in the lower layer I/O bus physical address range register 25 in the I/O bus coupler 6aand the physical address range 48ain the buffer 10ais not included in the physical address range 44a,the lower bus interface 22 in the I/O bus coupler 6aresponds to the request for transfer, and stores the transferred data in the buffer 23.

[0107] The I/O bus coupler 6asends a request for data transfer to the I/O bus 5d, to the destination in the physical address range 48ain the buffer 10ain the main memory 2. Since the physical address range 44dis provided in the I/O bus physical address range register 15 in the system bus-I/O bus coupler 4 and the physical address range 48ain the buffer 10ais not included in the physical address range 44d,the I/O bus interface 12 in the system bus-I/O bus coupler 4 responds to the request for transfer, and stores the transferred data in the buffer 13.

[0108] The system bus-I/O bus coupler 4 sends a request for transfer through the system bus 3 to the destination in the physical address range 48ain the buffer 10ain the main memory 2. Since the physical address range 48ais included in the physical address range 43 of the main memory 2, the main memory 2 responds to the request for transfer, and stores the transferred data in the physical address range 48ain the buffer 10a.

[0109] The CPU 1 performs a second accumulation of the result from the first accumulation in the buffer 10aand the previous result 82afrom the second accumulation in the last output buffer 101, and updates the previous result 82afrom the second accumulation to the result 82 from the second accumulation (step S7).

[0110] The CPU 1 performs the operations in steps S1-S7 for each of the blocks 62a-62d,etc. in the file 61a(step S8).

[0111] The operations in FIG. 15 are also performed for the file 61b,magnetic disk drive 8b,disk controller 7b,I/O bus 5a,processor 9a,I/O buffer 37b,output buffer 38b,and buffer 10b.

[0112] In this case, the file 61a,magnetic disk drive 8a,disk controller 7a,input buffer 37a,and output buffer 38ain FIG. 15 are replaced by the file 61b,magnetic disk drive 8b,disk controller 7b,input buffer 37b,and output buffer 38b.These operations can be performed in parallel with the operations shown in FIG. 15 through exclusive control in the queue 91.

[0113] The operations in FIG. 15 are also performed for the file 61c,magnetic disk drive 8c,disk controller 7c,I/O bus 5b,processor 9b,and buffer 10c.

[0114] In this case, the file 61a,magnetic disk drive 8a,disk controller 7a,I/O bus 5a,and processor 9aare replaced by the file 61c,magnetic disk drive 8c,disk controller 7c,I/O bus 5b,and processor 9b.These operations can be performed in parallel with the operations shown in FIG. 15 through exclusive control in the queue 91.

[0115] The operations in FIG. 15 are also performed for the file 61d,magnetic disk drive 8d,disk controller 7d,I/O bus 5b,processor 9b,input buffer 37b,output buffer 38b,and buffer 10d.

[0116] In this case, the file 61a,magnetic disk drive 8a,disk controller 7a,I/O bus 5a,processor 9a,input buffer 37a,and output buffer 38aare replaced by the file 61d,magnetic disk drive 8d,disk controller 7d,I/O bus 5b,processor 9b,input buffer 37b,and output buffer 38b.These operations can be performed in parallel with the operations shown in FIG. 15 through an exclusive control in the queue 91.

[0117] The operations in FIG. 15 are also performed for the file 61e,magnetic disk drive 8e,disk controller 7e,I/O bus 5c,processor 9c,and buffer 10e.

[0118] In this case, the file 61a,magnetic disk drive 8a,disk controller 7a,I/O bus 5a,and processor 9aare replaced by the file 61e,magnetic disk drive 8e, disk controller 7e,I/O bus 5c,and processor 9c.These operations can be performed in parallel with the operations shown in FIG. 15 through an exclusive control in the queue 91.

[0119] The operations in FIG. 15 are also performed for the file 61f,magnetic disk drive 8f,disk controller 7f,I/O bus 5c,processor 9c,input buffer 37b,output buffer 38b,and buffer 10f.

[0120] In this case, the file 61a,magnetic disk drive 8a,disk controller 7a,I/O bus 5a,processor 9a,input buffer 37a,and output buffer 38aare replaced by the file 61f,magnetic disk drive 8f,disk controller 7f,I/O bus 5c,processor 9c,input buffer 37b,and output buffer 38b.These operations can be performed in parallel with the operations shown in FIG. 15 through exclusive control in the queue 91.

[0121] Generally, the sizes of the results 72a-72dfrom the first accumulations are respectively smaller than the sizes of the blocks 62a∝62d.Therefore, the quantity of data transferred to the buffers 10a-10fin the main memory by the DMA transfer according to this embodiment is smaller than the quantity of the data transferred when the blocks 62a-62dare transferred directly. As the result, the sizes of the first accumulation result sequences 92a-92fare respectively smaller than the sizes of the files 61a-61f. Therefore, the quantity of data transferred to the I/O bus 5d,system bus-I/O bus coupler 4, system bus 3, and main memory 2 is smaller than the quantity of data transferred when all the blocks in the files 61a-61fare transferred to the main memory 2 before processing. The quantity of data processed by the CPU is also smaller than the quantity of data transferred when all the blocks in the files 61a-61fare transferred to the main memory 2 before processing.

[0122] As stated, according to this embodiment, when more devices are connected by the hierarchical bus, the ability of data transfer and the speed of data processing can be improved accordingly.

[0123] In embodiment 1, the processors 9a-9care only connected to the I/O buses 5a-5c.However, the processors 9a-9ccan be unified with the I/O bus couplers 6a-6c,and the same effect as in embodiment 1 can be realized.

[0124] FIG. 16 illustrates a configuration of a system for realizing embodiment 2 according to this invention.

[0125] In FIG. 16, the CPU 1, main memory 2, system bus 3, system bus-I/O bus coupler 4, I/O buses 5a-5d,disk controllers 7a-7f,disk drives 8a-8e,and files 61a-61fare illustrated. Each of the units has the same functions with a corresponding unit in embodiment 1. I/O bus couplers 106a-106cwith processors and the processors 9a-9care also illustrated. The processors 9a-9care included in the I/O bus couplers 106a-106crespectively.

[0126] FIG. 17 illustrates a configuration of the I/O bus coupler 106awith the processor according to this embodiment. The configuration of the I/O bus couplers 106band 106cthe same as in FIG. 17.

[0127] In FIG. 17, the I/O bus 5dat the upper layer, the I/O bus 5aat the lower layer, and the I/O bus coupler 106awith the processor are illustrated. The I/O bus coupler 6ais provided in the I/O bus coupler 106awith the processor. The configuration of the I/O bus coupler 6ais thee same as in FIG. 3, embodiment 1. I/O bus-local bus couplers 30aand 30bare provided in the I/O bus coupler 106awith the processor. The configuration of the I/O bus-local bus couplers 30aand 30bis the same as in FIG. 4, embodiment 1. The local bus 31, microprocessor 32, local memory 33, DMA controller 36, input buffers 37aand 37bin the local memory, and output buffers 38aand 38bin the local memory are also illustrated.

[0128] The operations in embodiment 2 are almost same as the operations in embodiment 1. The difference from embodiment 1 is described.

[0129] In embodiment 1, the result from the first accumulation in the output buffers 38aand 38bin the processors 9a-9care transferred to the buffers 10a-10fin the main memory 2 via the I/O bus couplers 6a-6cby the DMA transfer. However, in embodiment 2, since the local bus 31 connected to the local memory 33 is connected to the I/O bus 5aat the upper layer via the I/O bus-local bus coupler 30ain FIG. 17, the data are transferred via the I/O bus—local bus coupler 30ainstead of the I/O bus coupler 6a.Other operations and controls are same as in embodiment 1.

[0130] In embodiment 1, the data are processed by the processor at the same layer in the hierarchical bus, and sent to the CPU. However, the data can also sent to a processor at a different layer, if necessary.

[0131] FIG. 18 illustrates a configuration of the system according to embodiment 3.

[0132] In FIG. 18, the CPU 1, main memory 2, system bus 3, system bus-I/O bus coupler 4, I/O buses 5a-5d,I/O bus couplers 6a-6c,processors 9a-9d,and I/O devices 102a-102dare illustrated. Since locations of the buffers in the main memory 2 and internal configuration of the I/O devices 102a-102dare same as in embodiment 1, the illustrations are omitted in FIG. 18.

[0133] In embodiment 1, data from an I/O device connected to an I/O bus is transferred to an processor connected to the same I/O bus for processing. However, the data can be transferred to a processor which is not connected the same I/O bus. In FIG. 18, data from the I/O device 102aconnected to a bus can be transferred to processors 9b-9dconnected to different I/O buses instead of the processor 9a.The data from the I/O devices 102b-102dcan be processed by any one of the processors 9a-9d.

[0134] In embodiment 1, the data from the I/O device is transferred to the determined processor corresponding to the I/O device for processing. However, the data inputted from the I/O device can be transferred to a plurality of processors in a unit of blocks. It is also possible to send a part of the blocks to a buffer in the main memory for performing the first accumulation by the CPU.

[0135] A configuration of the system according to embodiment 4 is same as embodiment 3 in FIG. 18.

[0136] FIG. 19 illustrates an accumulation processing according to embodiment 4.

[0137] In FIG. 19, the files 61a-61dare stored in the magnetic disk drives in the I/O devices 102a-102d.The first accumulations 71a-71dare also illustrated. The first accumulations 71a-71dare assumed to be performed by the processors 9a-9drespectively. The first accumulation 71eis assumed to be performed by the CPU 1. The second accumulation 81 is assumed to be performed by the CPU 1.

[0138] Operations are explained.

[0139] In embodiment 4, the data in the file 61acan be processed in the first accumulations 71a-71eby any processor or CPU in the unit of blocks 62a-62d,etc.

[0140] For example, the block 62acan be transferred to the processor 9afor the first accumulation 71a,or to the processor 9bfor the first accumulation 71b,or to the processor 9cfor the first accumulation 71c,or to the processor 9dfor the first accumulation 71d.Or, the block 62acan be transferred to the main memory 2 for the first accumulation 71eby the CPU. The destination for transfer can be selected for each of the blocks 62b,62c,etc. arbitrarily, and the first accumulation of the blocks can be performed by the different processors or CPU.

[0141] In embodiment 4, blocks in any file can be transferred to any processor. However, it is also possible to restrict destination processors based on restriction in a hardware, efficiency in the transfer, and load condition during operation.

[0142] In embodiment 1, the result from the first accumulation is transferred to the main memory by the DMA transfer in each time when the result is generated. However, it is also possible to perform the second accumulation in the processor.

[0143] A configuration of the system and a procedure of initialization of the system in embodiment 5 are same as in embodiment 1. Difference from embodiment 1 is stated for embodiment 5.

[0144] FIG. 20 illustrated the accumulation processing according to embodiment 5.

[0145] In FIG. 20, the files 61a-61f,second accumulations 81a-81f,and results 82a-82ffrom the second accumulations are illustrated.

[0146] In embodiment 1, the first accumulation 71ais performed by the processor 9a,and the results 72a-72dfrom the first accumulation 71afor each of the blocks 62a-62dare transferred in the buffer 10ain the main memory 2 for processing. Then, the second accumulation is performed by the CPU 1.

[0147] However, in embodiment 5, the second accumulation 81aof the results 72a-72dfrom the first accumulation is also performed by the processor 9a.The result 82afrom the first accumulation 81ais stored in the output buffer in the processor 9a,and sent to the buffer 10ain the main memory 2 by the DMA transfer. Following processing is same as in embodiment 1.

[0148] FIG. 21 shows a flow chart of operations in embodiment 5.

[0149] In FIG. 21, the CPU 1 clears the result 82 from the second accumulation in the last output buffer 101. Accordingly, no record from the second accumulation is included in the result 82 from the second accumulation (step S100).

[0150] Then, the CPU 1 instructs the disk controller 7ato transfer a first block in the file 61ain the magnetic disk drive 8ato the physical address range 46a(step S101). The disk controller 7areads out the data from the file 61ain the magnetic disk drive 8a.Then, the data are stored in the input buffer 37ain the local memory 33 (step S102).

[0151] After the data are transferred, the CPU 1 instructs the microprocessor 32 in the processor 9ato perform first accumulation and second accumulation of the data in the input buffer 37a(step S103)

[0152] The microprocessor 32 performs first accumulation and second accumulation of the data in the input buffer 37a, and outputs the result from the second accumulation to the output buffer 38a(step S104) .

[0153] The CPU 1 starts the DMA controller 36 in the processor 9a,and transfers the result 82afrom the second accumulation in the output buffer 38ato the buffer 10ain the main memory 2 (step S105). Only the data in a size of the result 82afrom the second accumulation is transferred, and it is not necessary to transfer the whole data in the output buffer 38a.

[0154] The DMA controller 36 transfers the data to the destination in the physical address range 48aof the buffer 10ain the main memory 2 (step S106).

[0155] The CPU 1 performs a second accumulation of the result from the second accumulation in the buffer 10aand the result 82 from the second accumulation in the last output buffer 101, and updates the result 82 from the second accumulation (step S107).

[0156] The CPU 1 performs the operations in steps S101-S107 for each of the blocks 62a-62d,etc. in the file 61a(step S108).

[0157] It is also possible to perform the operations in FIG. 21 by a plurality of processors 9a-9cin parallel as in embodiment 1.

[0158] In embodiment 5, the second accumulation can be performed hierarchically. In FIG. 22, the second accumulation is performed hierarchically by a plurality of processors.

[0159] In FIG. 22, second accumulations 81a-81fat the lower layer and second accumulations 81gand 81hat the upper layer are performed by different processors or same processor.

[0160] As stated, in the data processing apparatus according to embodiments 1-5, a processor is provided at each layer in the hierarchical bus. Data are transferred from an I/O device connected to the hierarchical bus to one or all processors without being channeled through the main memory. The data are processed by the processor before being sent to the main memory, the result is transferred to the main memory.

[0161] In the data processing apparatus, the data are transferred from the I/O device connected to the hierarchical bus to the main memory without being channeled through the processor in the hierarchical bus.

[0162] In addition to the illustrated operation, the data can be transferred to an opposite direction from the stated operation in the data processing apparatus according to embodiments 1-5.

[0163] In that case, processors are provided at all or part of the layers in the hierarchical bus. The data are transferred from the main memory to the processors, and the data are processed by the processors. It is also possible to transfer the results from the processors to a part or all of the I/O devices connected to the hierarchical bus without being channeled through the main memory.

[0164] In the data processing apparatus, the data can be transferred from the main memory to the I/O device connected to the hierarchical bus without being channeled through the processor in the hierarchical bus.

[0165] As stated, processors are provided at a part or all of the layers in the hierarchical bus, and the data are processed by the processors before being sent to the I/O device. Accordingly, the data amount transferred to the upper layer in the hierarchical bus can be reduced, and the data amount processed by the CPU can be reduced. Hence, when more I/O devices are connected to the hierarchical bus, an appropriate transfer speed and process speed can be realized.

[0166] In embodiments 1-5, the accumulation processing with the selection-projection processing is stated for a purpose of illustration. However, any kind of processing, e.g., counting number of data with a certain condition, searching a maximum value of data, searching a minimum value of data, etc., is possible as far as the data amount can be reduced in preprocessing. Further, this invention can be also applied to a more complicated processing of a combination of the above-stated processing.

[0167] In embodiments 1-5, the accumulation processing with the selection-projection processing is stated for a purpose of illustration. This invention can also be applied, even if a part of the above processing is combined. Even if the processing is a combination of one or two of selection, projection, and accumulation, this invention can be still applied by performing a part of processing in the embodiments.

[0168] In embodiments 1-5, the result of processing by the processor is transferred to the main memory directly. However, the result can be sent from the processor to the I/O device temporally before processing.

[0169] In embodiments 1-5, the second accumulation is performed by the CPU 1. However, the second accumulation can be performed by any processor. Generally, even if the processing is other than the accumulation processing, the processing after a reduction of the data amount can be performed by any processor instead of the CPU 1.

[0170] In embodiments 1-5, a magnetic disk drive is connected to a disk controller. However, a plurality of magnetic disk drives can be connected to a disk controller.

[0171] In embodiments 1-5, a file is in a magnetic disk drive. However, a plurality of files can be in a magnetic disk drive.

[0172] In embodiments 1-5, a processor is connected to an I/O bus. However, a plurality of processors can be connected to an I/O bus.

[0173] In embodiments 1-5, a number of input buffers corresponding to files is same as a number of the I/O devices. However, a plurality of buffers can be provided for a file for performing a so-called double buffering control, etc.

[0174] In embodiments 1-5, a number of output buffers for storing the result from the first accumulation is same as a number of the I/O devices. However, a plurality of buffers for an I/O device can be provided for performing the double buffering control, etc.

[0175] In embodiments 1-5, a number of buffers 10a-10fin the main memory 2 is same as the number of I/O devices. However, even if the number of buffers is one or more, a same effect with the embodiments can be realized by performing an appropriate exclusive control.

[0176] In embodiments 1-5, the processor is connected to the I/O device. However, the processor can be also connected to the system bus directly.

[0177] In embodiments 1-5, the system bus and the I/O bus are different types of buses. However, the system bus and the I/O bus can be a same kind of bus with a same control procedure.

[0178] In embodiments 1-5, all the I/O buses are a same kind of bus. However, even if one of the I/O bus is controlled in a different control procedure, a same effect with the embodiments can be realized by providing an appropriate bus coupler.

[0179] In embodiments 1-5, the magnetic disk drive and the disk controller for controlling the magnetic disk drive are used as the I/O device for a purpose of illustration. However, the I/O device can be any kind of storage, e.g., magnetic tape drive, semi-conductor disk drive, etc. The I/O device is also possible to be connected through a network connected by a transmission line, network file system, etc.

[0180] In embodiments 1-5, the number of the CPU 1 connected to the system bus is one. However, the number of the CPU 1 can be more than one.

[0181] In embodiments 1-5, the CPU initiates the file transfer and DMA transfer. However, the microprocessor in the processor can also initiate such operations.

[0182] A processor is provided in a part or all of the layers in the hierarchical bus according to this invention. The data transferred from the I/O device is processed by the processors, and data amount transmitted to the upper layer in the hierarchical bus is reduced. Further, a processing amount of data by the CPU is reduced. Even if more number of I/O devices are connected to the hierarchical bus, an appropriate transfer speed and processing speed can be realized.

[0183] Having thus described several particular embodiments of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is limited only as defined in the following claims and the equivalents thereto.