Integrated circuit memory devices having improved sense and restore operation reliability

[0002] This application is related to Korean Application No. 98-39814, filed Sep. 24, 1998, the disclosure of which is hereby incorporated herein by reference.

[0003] The present invention relates to integrated circuits, and more particularly to integrated circuit memory devices.

[0004] Increases in the integration levels of integrated circuit memory devices may result in concomitant increases in the power consumption requirements of memory devices. Accordingly, attempts have been made to improve the power consumption efficiency of circuits that make up an integrated circuit memory device. Unfortunately, such attempts to improve power consumption efficiency may cause a reduction in the reliability of highly integrated memory devices.

[0005] FIG. 1 is a block diagram of a conventional integrated circuit memory device (e.g., DRAM device). As illustrated, the memory device includes control logic 80, an internal power supply voltage generator 90, a row address buffer 10, a column address buffer 20, a row decoder 30, a memory cell array 50, a sense amplifier 60, a column decoder 40, a data input buffer 70aand a data output buffer 70b. As illustrated by FIGS. 1-2, the internal power supply voltage generator 90 generates an internal supply voltage signal AIVC in response to an external supply voltage signal EVC. In particular, the internal power supply voltage generator 90 operates to actively pull up signal line AIVC when signal line PAIVCE is set to a logic 1 level, however, when signal line PAIVCE is set to a logic 0 level, the internal power supply voltage generator 90 does not supply pull-up current to signal line AIVC. The logic 1 pulse width of signal PAIVCE is typically directly related to the active pulse width of the row address strobe signal /RAS. As illustrated by FIG. 2, increases in the external supply voltage EVC above a predetermined clamping level (e.g., 2.5 volts) will not result in further corresponding increases in the magnitude of the signal provided to signal line AIVC.

[0006] Referring now to FIG. 3, an operation to read data from a memory cell within the array 50 includes the step of driving a corresponding word line WL to an active level (i.e., logic 1 level). In response, charge from within the memory cell will be transferred to a corresponding bit line BL and the bit line will rise slightly in potential. If the sense amplifier 60 is active (LANG=1, LAPG=0), the sense amplifier will use current provided by signal line AIVC to amplify and drive the differential bit lines BL and /BL to opposite logic levels, as illustrated. During this amplification operation, the voltage level on signal line AIVC may drop. Moreover, because the internal power supply voltage generator 90 may only operate to actively pull-up signal line AIVC while signal line PAIVCE is at a logic 1 level, the signal line AIVC may not return to a voltage level of 2.5 volts at the time the signal line PAIVCE transitions from 1-0. The reduction is illustrated by the amount “ΔV”. If this happens, the differential bit lines may not be driven to their full rail-to-rail levels and the reliability of data restore operations (when charge is transferred back into the selected memory cells to restore the data therein) may be reduced. This likelihood of reduced reliability may also be increased if the duration of the active row address strobe signal /RAS is decreased to achieve higher frequency of operation. Thus, notwithstanding attempts to develop more highly integrated memory devices, there continues to be a need for memory devices that can be more reliable when operating at relatively low voltage levels and at high frequencies.

[0007] It is therefore an object of the present invention to provide improved integrated circuit memory devices.

[0008] It is another object of the present invention to provide integrated circuit memory devices that can provide highly reliable data reading and data restore operations notwithstanding low voltage and/or high frequency operation.

[0009] These and other objects, advantages and features of the present invention can be provided by integrated circuit memory devices that preferably include a control circuit that generates an active first control pulse (e.g., PR) having a first duration, in response to an active strobe pulse (e.g., /RAS) that may be generated during a data reading operation. To allow improved reliability of the data reading operation and any subsequent data restore operation, particularly when the duration of the active strobe pulse is relatively short, a pulse width extension circuit is provided. The pulse width extension circuit converts the active first control pulse into an active second control pulse (e.g., PAIVCE2) having a second duration greater than the first duration. This active second control pulse is then provided as a control input to an internal voltage generator. In particular, the internal voltage generator is provided to drive a supply signal line (e.g., AIVC2) at a first supply voltage in response to the active second control pulse. The supply signal line may be provided as an internal supply line to one or more active circuits within the memory device.

[0010] For example, the supply signal line may be used to power a differential sense amplifier during data reading and data restore operations (i.e., when data is being sensed and amplified on a pair of differential bit lines). According to a preferred aspect of the present invention, these reading and restore operations may be performed with higher reliability if the additional pulse duration provided by the pulse width extension circuit is sufficient to enable a complete recharging of the differential bit lines of the sense amplifier prior to performance of a data restore operation.

[0011] FIG. 1 is a block diagram of an integrated circuit memory device according to the prior art.

[0012] FIG. 2 is a graph that illustrates a relationship between an external power supply reference voltage (EVC) and an internal power supply reference voltage (AIVC) according to the prior art.

[0013] FIG. 3 is a timing diagram that illustrates operation of the device of FIG. 1.

[0014] FIG. 4 is a block diagram of an integrated circuit memory device according to an embodiment of the present invention.

[0015] FIG. 5 is an electrical schematic of a preferred pulse width extension circuit, according to the device of FIG. 4.

[0016] FIG. 6 is an electrical schematic of a preferred internal voltage generator, according to the device of FIG. 4.

[0017] FIG. 7 is an electrical schematic of a preferred differential sense amplifier, according to the device of FIG. 4.

[0018] FIG. 8 is a timing diagram that illustrates operation of the device of FIG. 4.

[0019] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout and signal lines and signals thereon may be referred to by the same reference symbols.

[0020] Referring now to FIG. 4, an integrated circuit memory device according to a preferred embodiment of the present invention will be described. As illustrated, a control circuit 180 is provided to, among other things, generate an active first control pulse (PR) having a first duration (T1), in response to an active strobe pulse. As illustrated best by FIG. 8, this active first control pulse (PR) may be generated in response to an active row address strobe signal (/RAS). As will be understood by those skilled in the art, an active row address strobe signal (/RAS) is typically provided as a logic 0 pulse. This logic 0 pulse then initiates a data reading operation by, among other things, driving one or more word lines within the memory device with signals that turn on access transistors within memory cells. The duration of the active row address strobe signal (/RAS) may be inversely related to the frequency at which the memory device operates. The control circuit 180 may also be responsive to a column address strobe signal (/CAS) and a write enable signal (/WE) and operate in-sync with a clock signal (CLK).

[0021] A row address buffer 100 and a column address buffer 110 are also provided. The row address buffer 100 buffers a row address (RA) and provides buffered row addresses to a row decoder 120. Similarly, the column address buffer 110 buffers a column address (CA) and provides buffered column addresses to a column decoder 130. As will be understood by those skilled in the art, the row decoder 120 is electrically coupled to word lines within a highly integrated memory cell array 140. A sense amplifier 150 is also provided. The sense amplifier 150 may be electrically coupled to the memory cell array 140 by a plurality of pairs of differential bit lines (BL and /BL) and electrically coupled to a column decoder 130, as illustrated. The column decoder 130 may provide column select circuitry that enables read data to be passed from the differential bit lines to input/output lines (IO and /IO that are coupled to a data output buffer 170) and enables write data to be passed from a data input buffer 160 to the bit lines.

[0022] Referring still to FIG. 4, a preferred pulse width extension circuit 190 is also provided. The pulse width extension circuit 190 performs the function of converting the active first control pulse (PR) into an active second control pulse (PAIVCE2) having a second duration (T2) greater than the first duration (T1). As illustrated by FIG. 5, the pulse width extension circuit 190 preferably comprises a pair of delay inverters INV1 and INV2 electrically connected in series, a NOR gate G1 and an output inverter INV3. As will be understood by those skilled in the art, the pair of delay inverters INV1 and INV2 operate in combination with the boolean OR operation provided by the NOR gate G1 and inverter INV3, to provide an active second control pulse (PAIVCE2) (e.g., logic 1 pulse) having a greater duration than the duration of the active first control pulse (PR). In particular, a leading 0→1 transition on signal line PR will result in a corresponding 0→1 transition on signal line PAIVCE2, however, a trailing 1→0 transition on signal line PR will result in a delayed 1→0 transition on signal line PAIVCE2 because node N1 will remain at a logic 1 level for some time after node N2 transitions to a logic 0 level. The additional duration is equivalent to the delay provided by inverters INV1 and INV2. It will also be understood that other pulse extension circuits may be used.

[0023] The active second control pulse PAIVCE2 is provided as a control input to an internal power supply voltage generator 200. As illustrated best by FIGS. 4 and 6, the internal power supply voltage generator 200 preferably comprises a differential amplifier and a driver circuit. The differential amplifier has first and second differential inputs that are provided by the gate electrodes of NMOS transistors NM1 and NM2 and first and second differential outputs that are provided by the drain electrodes of NMOS transistors NM1 and NM2. The differential amplifier also comprises an NMOS pull-down transistor NM3 that operates as a current source and PMOS pull-up transistors PM1 and PM2. The source electrode of the NMOS pull-down transistor NM3 is electrically coupled to a ground reference signal line Vss. The driver circuit comprises a PMOS pull-up transistor PM3 that has a gate electrode electrically connected to the first differential output and a source electrode electrically connected to the output (signal line AIVC2) and the gate electrode of NMOS transistor NM2 (i.e., the second differential input). A reference voltage VREF is also provided to the gate electrode of NMOS transistor NM1. The differential amplifier and driver circuit are both powered by an external power supply signal line EVC. Other power supply voltage generator circuits may also be used.

[0024] As will be understood by those skilled in the art, the PMOS pull-up transistor PM3 operates to supply current to the output (AIVC2) of the internal power supply voltage generator 200 whenever the potential of the output drops below the potential of the reference voltage VREF and the NMOS pull-down transistor (acting as a current source) is conductive (i.e., the active second control pulse PAIVCE2 is being applied to the gate electrode of NMOS transistor NM3).

[0025] Referring now to FIGS. 7 and 8, an operation to read data from the zeroth memory cell MC0 (storing logic 1 data) takes place by driving the zeroth word line WL0 to a logic 1 level in response to an active row address strobe signal. When this occurs, a relatively small amount of charge will be provided to the bit line BL (but not the complementary bit line /BL). This small amount of charge will cause the potential of the bit line BL to rise slightly above the corresponding complementary bit line /BL. Because both the PMOS pass transistor PM6 and NMOS pass transistor NM6 are conductive (LAPG and LANG are set to logic 0 and logic 1 levels, respectively), and because the output of the voltage generator 200 (signal line AIVC2) is set at 2.5 volts, the PMOS and NMOS sense amplifiers will operate to amplify the differential potential established across the bit lines BL and /BL. The PMOS and NMOS sense amplifiers are formed by PMOS transistors PM4 and PM5 and NMOS transistors NM4 and NM5. This amplification operation will cause the voltage level at the output of the voltage generator 200 to drop as a relatively large amount of charge is transferred from signal line AIVC2 to the bit line BL during the amplify operation. But, because the duration of the active second control pulse PAIVCE2 is relatively long compared to the duration of pulse PAIVCE illustrated by FIG. 3, the PMOS pull-up transistor PM3 will remain conductive longer and thereby charge the bit line BL fully to a logic 1 level. This higher logic 1 level on the bit line BL will result in improved restore efficiency when the logic 1 level is written back into the zeroth memory cell MC0. Accordingly, the present invention advantageously uses a pulse width extension circuit to allow improved device reliability.

[0026] In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.