Slave circuit select device which can individually select a plurality of slave circuits with one data bus

[0002] 1. Field of the Invention

[0003] The present invention relates to a select circuit for selecting a circuit in a specific portion of a system formed of electronic circuits.

[0004] 2. Description of the Background Art

[0005] Some of systems formed of electronic circuits operate in such a manner that a specific device (e.g., a bus master circuit such as a CPU) selects one of a plurality of devices (e.g., slave circuits such as memories) with a select circuit for input/output of data through a data bus.

[0006] FIG. 6 is a schematic block diagram showing a system which employs a conventional select circuit and is formed of a master circuit such as a CPU or the like and slave circuits such as dynamic semiconductor memory devices which will be referred to as “DRAMs”, or static semiconductor memory devices which will be referred to as “SRAMS” hereinafter.

[0007] Referring to FIG. 6, a chip 0 which is a chip of a bus master carries a CPU issues onto a select signal line CM a signal specifying a chip to be selected among chips 1-3 of slave circuits, and transmits data to and from chips 1-3 through a data bus BUS.

[0008] Chips 1-3 which are slave chips formed of DRAMs or SRAMs output or input data onto or from data bus BUS through data I/O terminals DQc1-DQc3 when corresponding chip enable signal input terminals CE1-CE3 receive active signals at “H” level, respectively.

[0009] A select signal generating circuit S1 activates (i.e., sets to “H” level) one of chip select signals CS1-CS3, which are applied to chips 1-3 of the slave chips, respectively, in response to a signal sent from chip 0 of the master circuit through select signal line CM.

[0010] An operation in which chip 0 of the master chip receives data from chip 3 of the slave chip will now be described as an example of the operation of the structure shown in FIG. 6.

[0011] FIG. 7 is a timing chart showing the above operation.

[0012] Chip 0 of the bus master sends to select signal generating circuit S1 a signal instructing it to activate chip select signal CS3 to attain “H” level.

[0013] Select signal generating circuit S1 sets signal CS3 to the active state (“H” level) in response to the signal sent from chip 0 of the bus master at time τ0.

[0014] Due to delay on a signal interconnection, the potential level on chip enable signal input terminal CE3 of chip 3 of the slave chip (i.e., the potential level on a node P3 of the signal interconnection) attains the active state (“H” level) after a time period of 3×τ0 from time t0. Chip 3 of the slave chip sends the data to data I/O terminal DQc3 at time t2 after a constant time period, which is assumed to be equal to τ0 for simplicity reason, from activation of the potential level on chip enable signal input terminal CE3.

[0015] In the following description, it is assumed that the chips 1-3 of the slave chips continuously issue nine data with a cycle time of τ0.

[0016] At time t3 after a time period of 3τ0 from time t2, chip 0 of the bus master receives through data bus BUS the data, which is sent from chip 3 of the slave chip and takes the form of change in potential on node DQ0 between data bus BUS and chip 0.

[0017] Description will be further given on the case that bus master chip 0 receives the data from chip 1 of the slave chip subsequently to start of reception of the data from chip 3 of the slave chip at time t3.

[0018] Chip 0 of the bus master issues to select signal generating circuit S1 signal CM instructing deactivation (“L” level) of signal CS3 after a time period of 9×τ0 from issuance of the instruction for setting signal CS3 to the active state (“H” level).

[0019] At the same time, chip 0 of the bus master sends signal CM instructing activation (“H” level) of signal CS1 to select signal generating circuit S1.

[0020] Select signal generating circuit S1 keeps signal CS3 in the active state (“H” level) for a time period of 9×τ0 from time t0 to time t4 in accordance with the signal sent from chip 0 of the bus master, and subsequently keeps signal CS1 in the active state (“H” level) for a time period of 9×τ0 from time t4 to time t8.

[0021] Due to an interconnection delay, the potential level on chip enable signal input terminal CE3 of chip 3 of the slave chip (i.e., potential level on node P3) attains the inactive state (“L” level) at time t7 after a time period of 3×τ0 from time t4. The potential level on chip enable signal input terminal CE1 of chip 1 of the slave chip (i.e., potential level on node P1) attains the active state (“H” level) at time t5 after a time period of τ0 from time t4.

[0022] Further, chip 1 issues the data to data I/O terminal DQc1 at time t6 after a time period of τ0 from time t5.

[0023] As described above, chip 0 of the bus master receives the data issued from chip 3 through data bus BUS when a time period of 3×τ0 elapses after chip 3 starts output of the data. Chip 0 of the bus master receives the data when a time period of τ0 elapses after chip 1 of the slave chip starts output of the data.

[0024] However, chip 1 of the slave chip is located near bus master chip 0 so that the data sent from chip 1 of the slave chip arrives at chip 0 of the bus master in a shorter time than the data from the other slave chips. This may results in such a problem that the data sent from chip 1 of the slave chip arrives at the bus master while chip 0 of the bus master is receiving the data sent from chip 3 forming the slave ship, and therefore collision of data occurs.

[0025] For avoiding the above data collision, Japanese Patent Laying-Open No. 5-250280 (1993) has disclosed a structure in which output of data from slave chips starts in response to a start signal sent through a path of which is folded at a chip remotest from the bus master.

[0026] According to this structure, however, one start signal is supplied to all the slave chips, and the slave chips output the data after individually determined delay times, respectively. Therefore, one start signal operates to read or write the data from or into all the slave chips so that it is impossible to select one of the slave chips for reading or writing the data.

[0027] An object of the invention is to provide a select circuit for a system in which a master circuit transmits data to and from a plurality of slave circuits, and particularly the select circuit which can avoid collision of data sent from the slave circuits even when selection of arbitrary one of the slave circuits is performed successively.

[0028] Another object of the invention is to provide a select circuit which can be used for transmission of data by a master circuit with respect to a plurality of slave circuits, and can perform selection of slave circuits with a simple structure without increasing the number of buses for selecting the slave circuits.

[0029] In summary, the invention provides a slave circuit select device including a select signal generating circuit, a signal interconnection and select circuits.

[0030] The select signal generating circuit issues a select signal including two pulse signals in response to a control signal sent from a master circuit. The signal interconnection is divided into first and second interconnection portions, and is folded at a boundary between the first and second interconnection portions. The select circuits are provided correspondingly to a plurality of slave circuits to be selected in accordance with a signal transmitted through the signal interconnection, respectively, and are arranged at corresponding positions on the signal interconnection, respectively.

[0031] For selecting the slave circuit corresponding to the specific select circuit, the select signal generating circuit issues the two pulse signals to one end of the signal interconnection such that a time interval between the two pulse signals corresponds to a delay time in transmission of the pulse signal from the specific select circuit to the specific select circuit through the first interconnection portion, the boundary and the second interconnection portion. The select circuit selects the corresponding slave circuit in response to the active state of both the pulse signals sent from the first and second interconnection portions.

[0032] According to another aspect, a slave circuit select device includes a select signal generating circuit, a signal interconnection and select circuits.

[0033] The select signal generating circuit issues a select signal including two pulse signals in response to a control signal sent from a master circuit.

[0034] The signal interconnection has a length of L=2×n×UL (n: natural number, UL: a predetermined unit length). The signal interconnection includes a first interconnection portion extending from one end and having a length of n×UL, and a second interconnection portion folded with respect to the first interconnection portion and having a length of n×UL.

[0035] The select circuits are provided correspondingly to slave circuits of m (m: natural number, m<n) in number to be selected in accordance with the signal transmitted through the signal interconnection. The select circuit at an ith (i: natural number) position among the select circuits is arranged at a distance of j×UL (j: natural number) allocated to the same select circuit from the folded position of the signal interconnection along the signal line.

[0036] The select signal generating circuit issues the two pulse signals at a time interval of 2×j×t to the one end of the signal interconnection for selecting the slave circuit corresponding to the select circuit at the ith position, t being a time required for transmission of the pulse signal through a distance of UL.

[0037] The select circuit selects the corresponding slave circuit in response to the active state of both the pulse signals sent from the first and second interconnection portions.

[0038] According to still another aspect, a slave circuit select device includes a select signal generating circuit, a signal interconnection and select circuits.

[0039] The select signal generating circuit issues a select signal including two pulse signals in response to a control signal sent from a master circuit. The signal interconnection is folded at its central portion to divide the same into first and second interconnection portions. The plurality of slave circuits are provided correspondingly to a plurality of slave circuits to be selected in accordance with a signal transmitted through the signal interconnection, respectively.

[0040] The plurality of select circuits are arranged along the signal interconnection with a space DL between each other, and the select circuit nearest to the folded position of the signal interconnection is spaced by a predetermined distance Lp from the folded position.

[0041] The select signal generating circuit issues the two pulse signals at a time interval of 2×{τ1+τ2(j−1)} to one end of the signal interconnection for selecting the slave circuit corresponding to the select circuit at a jth position from the folded position of the signal interconnection, τ1 being a time required for transmission of the pulse signal through the distance of Lp and τ2 being a time required for transmission of the pulse signal through the distance of DL.

[0042] The select circuit selects the corresponding slave circuit in response to the active state of both the pulse signals sent from the first and second interconnection portions.

[0043] Accordingly, the invention can achieve such an advantage that the master circuit can arbitrarily select the plurality of slave circuits with the one signal line in a folded form.

[0044] As another advantage of the invention, collision does not occur between data sent from the plurality of slave circuits, because the time period from the time when the master circuit operates to issue the select signal from the select signal generating circuit to the time when the master circuit receives the data sent from the slave circuit is constant independently of the position of the slave circuit.

[0045] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0046] FIG. 1 is a schematic block diagram showing a structure of a select circuit 1000 of an embodiment 1 of the invention;

[0047] FIG. 2 is a schematic block diagram showing a structure of a select signal generating circuit S2;

[0048] FIG. 3 is a timing chart showing an operation of the select circuit 1000;

[0049] FIG. 4 is a timing chart specifically showing the operation of the select circuit 1000;

[0050] FIG. 5 is a schematic block diagram showing a structure of a select circuit 2000 of an embodiment 2 of the invention;

[0051] FIG. 6 is a schematic block diagram showing a structure of a select circuit in the prior art; and

[0052] FIG. 7 is a timing chart showing an operation of the select circuit in the prior art.

[0053] [Embodiment 1]

[0054] FIG. 1 is a schematic block diagram showing a structure of a select circuit 1000 of an embodiment 1 of the invention.

[0055] For simplicity reason, the following description will be given on a structure, in which one master circuit transmits data to and from three slave circuits (chips 1-3).

[0056] The select circuit 1000 includes a select signal generating circuit S2. Select signal generating circuit S2 responds to a signal, which is sent from a chip 0 of the bus master through a select signal line CM and indicates the chip to be selected among the chips 1-3 of the slave chips, and thereby issues onto a select signal line CEL two pulses at “H” level, each of which has a time width of τ0 and is spaced from the other by a time interval of 6×τ0, 4×τ0 or 2×τ0 depending on the slave chip to be selected, within a time period of 9×τ0.

[0057] Select circuit 1000 further includes a select signal line CEL, which extends from select signal generating circuit S2 along all the slave chips, is folded and returns toward select signal generating circuit S2, D-flip-flop circuits D-FF1-F-FF3 provided correspondingly to the slave chips, respectively, and a resistor Rt connected to an end of signal line CEL remote from a connection to select signal generating circuit S2. It is now assumed that the resistance value of resistor Rt is coincident with a characteristic impedance of select signal line CEL.

[0058] Owing to the above structure, the pulse signal issued from select signal generating circuit S2 is completely absorbed in resistor Rt at the remote end, and reflection of the pulse signal does not occur at the remote end of the select signal line CEL.

[0059] A trigger terminal of D-flip-flop circuit D-FF1 is connected to select signal line CEL at a position where the transmission delay of the signal sent from chip 0 of the bus master (or select signal generating circuit S2) is τ0. Likewise, a trigger terminal of D-flip-flop circuit D-FF2 is connected at a position where the transmission delay is 2×τ0, and a trigger terminal of D-flip-flop circuit D-FF3 is connected at a position where the transmission delay is 3×τ0.

[0060] A data terminal D of D-flip-flop circuit D-FF1 is connected to select signal line CEL at a position where the transmission delay of the signal sent from chip 0 of the bus master (or select signal generating circuit S2) is 7×τ0. A data terminal D of D-flip-flop circuit D-FF2 is connected at a position where the transmission delay is 6×τ0. A data terminal D of D-flip-flop circuit D-FF3 is connected at a position where the transmission delay is 5×τ0.

[0061] Output terminals Q of D-flip-flop circuits D-FF1-D-FF3 are connected to chip enable terminals CE1-CE3 of chips 1-3 of the slave chips, respectively.

[0062] FIG. 2 is a schematic block diagram showing a structure of select signal generating circuit S2 shown in FIG. 1.

[0063] In the following description, it is assumed that signal CM issued from chip 0 of the bus master includes a signal CMA for activating select signal generating circuit S2 and address signals CM0-CM1 designating the slave chip to be selected.

[0064] Select signal generating circuit S2 includes a one-shot pulse generating circuit 100 which is activated by signal CMA to issue a pulse signal of a time with of τ0, a delay circuit 102 which receives the output of one-shot pulse generating circuit 100 and issues the same with a delay of a time of 2×τ0, a delay circuit 104 which receives the output of delay circuit 102 and issues the same with a delay of a time of 2×τ0, a delay circuit 106 which receives the output of delay circuit 104 and issues the same with a delay of a time of 2×τ0, a select pulse generating circuit 110 which receives the output of one-shot pulse generating circuit 100 and the outputs of delay circuits 102, 104 and 106, and issues first and second pulse signals onto select signal line CEL, and a decoder 108 which receives signals CMO and CM1, and issues a decoded signal to select pulse generating circuit 110.

[0065] Select pulse generating circuit 110 further includes a AND circuit 112, which receives on one of its inputs the output of one-shot pulse generating circuit 100 and on the other input a signal at “H” level (potential level of a power supply potential Vcc), and has an output node connected to interconnection CEL, a AND circuit 114 which receives on one of its inputs the output of delay circuit 102 and on the other input the decoded signal sent from decoder 108, and has an output node connected to signal interconnection CEL, a AND circuit 116 which receives on one of its inputs the output of delay circuit 104 and on the other input the decoded signal sent from decoder 108, and has an output node connected to signal interconnection CEL, and a AND circuit 118 which receives on one of its inputs the output of delay circuit 106 and on the other input the decoded signal sent from decoder 108, and has an output node connected to signal interconnection CEL.

[0066] Therefore, select signal generating circuit S2 sends the pulse signal, which is issued from one-shot pulse generating circuit 100, to signal interconnection CEL through AND circuit 112 in response to signal CMA issued from chip 0 of the bus master, and thereafter responds to address signals CM0 and CM1 applied to decoder 108 by issuing onto the select signal line CEL one of the delayed pulse signals, i.e., the pulse signal issued from delay circuit 102 and delayed by the time of 2×τ0, the pulse signal issued from delay circuit 104 and delayed by the time of 4×τ0 and the pulse signal issued from delay circuit 106 and delayed by the time of 6×τ0.

[0067] FIG. 3 is a timing chart showing an operation of select circuit 1000 shown in FIG. 1.

[0068] For selecting chip 2 of the slave chip and receiving data therefrom by chip 0 of the bus master, select signal generating circuit S2 issues the pulse signal at time t0, and then issues the second pulse signal of the width of τ0 onto select signal line CEL after a time interval of 4×τ0. D-flip-flop circuit D-FF2 provided correspondingly to chip 2 of the slave chip receives on its trigger terminal the first pulse at time t2 after a time period of 2×τ0 from time t0, and receives on the same the second pulse at time t6 after a time period of 6×τ0 from time t0.

[0069] D-flip-flop circuit D-FF2 receives on its data terminal the first pulse at time t6 after a time period of 6×τ0 from time t0 and receives on the same the second pulse at time t9 after a time period of 10×τ0 from time t0.

[0070] The potential level on the output terminal of D-flip-flop circuit D-FF2 does not change and is held at “L” level because the potential level on the data terminal thereof is at “L” level when the first pulse arrives at the trigger terminal at time t2.

[0071] Therefore, the potential level on the chip enable signal input terminal of chip 2 of the slave chip is kept at “L” level so that chip 2 is yet not selected at this point of time.

[0072] When the second pulse arrives at the trigger terminal of D-flip-flop circuit D-FF2 at time t6 after a time period of 6×τ0 from time t0, the first pulse signal arrives at the data terminal of D-flip-flop circuit D-FF2. Therefore, both the potentials on the trigger and data terminals are at “H” level at this time so that the output terminal Q of D-flip-flop circuit D-FF2 carries the potential at “H” level. Thereby, the potential on the chip enable signal input terminal of chip 2 of the slave chip is driven to “H” level, and chip 2 is selected.

[0073] Chip 2 starts output of the data at time t7 after a time period of τ0 from time t6 owing to the fact that the potential on the chip enable signal input terminal attains “H” level, and thereafter continues output of the data for a time period of 9×τ0.

[0074] For a period from time t0 to time t7, the pulse signals are supplied to the data terminals and trigger terminals of D-flip-flop circuits D-FF1 and D-FF3 provided correspondingly to chips 1 and 3 of the slave chips, respectively. However, the potential levels on the data terminal and trigger terminal of D-flip-flop circuit D-FF1 or D-FF3 simultaneously attain “H” level only when the first and second pulse signals are spaced by the period of 6×τ0 or 2×τ0. Therefore, the chip 1 and chip 3 are not selected when chip 2 is selected, i.e., when the two pulse signals are spaced by 4×τ0.

[0075] The data issued from chip 2 of the slave chip first arrives at chip 0 of the bus master after a time period Td from time t0 when chip 0 starts selection of chip 2. This time Td can be expressed as follows.

[0076] Td=T1 (time required for arrival of the first pulse at the data terminal of D-flip-flop circuit D-FF2)+T2 (time between selection of chip 2 to output of data)+T3 (time required for arrival of data at chip 0)=6τ0+τ0+2τ0=9τ0

[0077] When chip 1 is selected and therefore select signal generating circuit S2 issues two pulses at a time interval of 6τ0, the following relationship is likewise exhibited. $\begin{array}{c}\mathrm{Td}=\mathrm{T1}+\mathrm{T2}+\mathrm{T3}\\ =7\mathrm{\tau 0}+\mathrm{\tau 0}+\mathrm{\tau 0}\\ =9\mathrm{\tau 0}\end{array}$

[0078] When chip 3 is selected and therefore select signal generating circuit S2 issues two pulses at a time interval of 2τ0, the following relationship is likewise exhibited. $\begin{array}{c}\mathrm{Td}=\mathrm{T1}+\mathrm{T2}+\mathrm{T3}\\ =5\mathrm{\tau 0}+\mathrm{\tau 0}+3\mathrm{\tau 0}\\ =9\mathrm{\tau 0}\end{array}$

[0079] Times Td are constant independently of chips 1, 2 and 3.

[0080] As shown in FIG. 3, therefore, collision of the outputs of chips 1 to chip 3 does not occur even in the case that chip select signal generating circuit S2, which issued the signal for selecting chip 2 at time t0, additionally issues the signal for selecting chip 3 at time t8 after a time period 9τ0 after time t0, and further issues the signal for selecting chip 1 at time t13 after a time period of 9τ0 from time t8.

[0081] Thus, fast and accurate data transmission can be performed between chip 0 of the bus master and chips 1-3 of the slave chips 1-3.

[0082] Further, select pulse generating circuit S2 can select one slave chip among the plurality of slave chips 1-3 to output data therefrom in accordance with the pulse interval between the two pulse signals applied onto select signal line CEL.

[0083] In the above description, it is assumed for simplicity reason that the delay time of τ0 is required for transmission of the pulse signal from select signal generating circuit S2 to chip 1 of the slave chip.

[0084] As can be seen from the above description, however, the invention is not restricted to this.

[0085] In the above description, the slave chips are equally spaced from each other. However, the invention is not restricted to this arrangement.

[0086] This is because the interval between two pulse signals for selecting, e.g., chip 1 of the slave chip depends on the delay time in transmission from a node P10 to the folded point of select signal line CEL.

[0087] When D-flip-flop circuits D-FF1-D-FF3 issuing the chip select signals are used for the corresponding slave chips, respectively, it is preferable that the delay time in transmission between the slave chip, i.e., chip 3 in FIG. 1, nearest to the folded point of the select signal line CEL and the folded point is shorter by a time a than the delay time in transmission other than the above, as shown in FIG. 1.

[0088] FIG. 4 is a timing chart specifically showing timings of the signals applied to the data terminal and trigger terminal of the D-flip-flop circuit D-FF1 provided correspondingly to chip 1 of the slave chip in the cases that time α is 0 and is a half of pulse width of τ0.

[0089] In the case of time α=0, as already described with reference to FIG. 3, the potential levels on node P10 and node Pi simultaneously rise to “H” level when select signal generating circuit S2 issues the pulse signal selecting chip 1 of the slave chip.

[0090] In response to the rising edge of the signal level on node P10, D-flip-flop circuit D-FF1 takes in the potential level on node P1i through the data terminal and issues an active signal to chip enable signal input terminal C1.

[0091] In the case of α=τ0/2, the potential level on node P1i already rose to “H” level at a time earlier by the time a than the rising edge of the signal level on node P10.

[0092] As already described, therefore, D-flip-flop circuit D-FF1 can output the data more stably if the time a is set not to 0 but to τ0/2.

[0093] The time a can take on an arbitrary value larger than 0 and smaller than a value τ0 of the pulse width of the pulse signal.

[0094] As can be understood from the above discussion, however, D-flip-flop circuit D-FF1 has a large operation margin when time a is equal to a half of pulse width τ0.

[0095] [Embodiment 2]

[0096] FIG. 5 is a schematic block diagram showing a structure of a select circuit 2000 of an embodiment 2 of the invention.

[0097] The structure of select circuit 2000 differs from select circuit 1000 of the embodiment 1 in that D-flip-flop circuits D-FF1-D-FF3 in the embodiment 1, which are provided for chips 1-3 of the slave chips, are replaced with AND circuits G1-G3, respectively.

[0098] Structures other than the above are the same as those of select circuit 1000 of the embodiment 1 shown in FIG. 1. The same parts and portions as those in FIG. 1 bear the same reference characters, and will not be described below.

[0099] According to the select circuit of the embodiment 2 shown in FIG. 5, when select signal generating circuit S2 issues two pulse signals at a time interval which sets both the potential levels on nodes P10 and O1i at select signal line CEL corresponding to chip 1 of the slave chip to “H” level, the potential level on a chip enable signal input terminal CE1 of corresponding chip 1 attains “H” level.

[0100] The above is true with respect to other chips 2 and 3 of the slave chips.

[0101] Owing to the above structure, accurate and fast data transmission can be performed between chip 0 of the bus master and chips 1 to 3 of the slave chips with a more simple structure. Further, one of chips 1 to 3 of the slave chips can be selected in accordance with the pulse interval of the pulse signals applied onto select signal line CEL.

[0102] In the above description of the embodiments 1 and 2, select circuits 1000 and 2000 each are formed of the chip of the bus master and the slave chips such as a CPU and memories. However, the invention is not restricted to this. For example, the invention can be applied to selection of a row or column of memory cells in a memory device as well as selection of a memory cell block.

[0103] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.