Semiconductor device and method of manufacture

[0002] The present invention relates, in general, to semiconductor devices and, more particularly, to power semiconductor devices.

[0003] Power semiconductor devices are well known and are used in many applications including automotive electronics, portable electronics, power supplies, and telecommunications. Manufacturers of these devices typically use a thick field oxide together with diffused field limiting rings and channel stop regions to reduce device leakage, reduce undesirable parasitic effects, and to enhance device breakdown. All of these approaches serve to address the same basic problem of maximum electric field relaxation of a planar junction. Each termination approach possesses a set of innate advantages and disadvantages, and the designer attempts to minimize the negative aspects of an approach while simultaneously exploiting the positive aspects. Among these approaches, field-limiting rings are one of the least costly in regards to semiconductor device manufacturing investment, as the same diffusion step used to form the PN junction of the main device can often be used to form the field-limiting rings.

[0004] Another device characteristic that semiconductor device manufacturers try to optimize is the on-resistance of the semiconductor devices. The value of this parameter is governed by the concentration of dopant in the semiconductor material in which the semiconductor device is fabricated as well as the thickness of this material. Since it is desirable to have a low on-resistance, it is preferable that the semiconductor material be thin and heavily doped.

[0005] Accordingly, it would be advantageous to have a semiconductor device and method for its manufacture that includes a termination structure and is designed to have a high breakdown voltage and a small on-resistance. It would be of further advantage for the method of manufacture to be cost efficient and integrable with available processing techniques.

[0006] FIG. 1 is a highly enlarged cross-sectional view of a semiconductor device at an early stage of manufacture in accordance with a first embodiment of the present invention;

[0007] FIG. 2 is a highly enlarged cross-sectional view of the semiconductor device of FIG. 1 at a later stage of manufacture;

[0008] FIG. 3 is a highly enlarged cross-sectional view of the semiconductor device of FIG. 2 at a later stage of manufacture;

[0009] FIG. 4 is a highly enlarged cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention; and

[0010] FIG. 5 is a highly enlarged cross-sectional view of a semiconductor device in accordance with a third embodiment of the present invention.

[0011] In general, the present invention relates to a method for manufacturing a power semiconductor device that includes a termination structure as well as structures to lower its on-resistance and increase its breakdown voltage. It should be understood that termination structures are also referred to as stress relaxation regions because they reduce the electric field at the edges of the semiconductor devices. More particularly, the present invention provides a semiconductor device having a field termination structure combined with a drift region that affords a lower on-resistance and a termination structure that helps reduce device leakage, reduces undesirable parasitic effects and enhances the breakdown voltage. Although specific materials, conductivity types, thicknesses, and other parameters are set forth herein, it should be understood that these are not meant to be limiting and only serve to show preferred embodiments of the present invention. Further, it should be understood that the same reference numerals are used in the figures to denote the same elements.

[0012] FIG. 1 is a highly enlarged cross-sectional view of a semiconductor device 10 at an early stage of manufacture in accordance with a first embodiment of the present invention. What is shown in FIG. 1 is a body of semiconductor material 11 that is comprised of a buffer layer 13 sandwiched between a substrate 12 and a drift layer 14. Preferably, substrate 12 is silicon of N-type conductivity and has a doping concentration of about 1×10¹⁹to 1×10²⁰atoms per cubic centimeter (atoms/cm³). Buffer layer 13 is silicon of N-type conductivity and formed on substrate 12 using a conventional technique such as, for example, an epitaxial growth technique. Similarly, drift layer 14 is of N-type conductivity and formed on buffer layer 13. By way of example, buffer layer 13 has a dopant concentration ranging from about 1×10¹⁶to 1×10¹⁸atoms/cm³and a thickness ranging from about 5 to about 20 micrometers and drift layer 14 has a dopant concentration ranging from about 1×10¹⁵to 1×10¹⁷atoms/cm³and a thickness ranging from about 30 to about 100 micrometers. For an n-channel device, substrate 12 and buffer layer 13 are preferably doped with arsenic and phosphorus, respectively. It should be understood that buffer layer 13 is an optional layer. Body of semiconductor material 11 has major surfaces 15 and 17.

[0013] A masking oxide layer 18 is formed on major surface 17. Masking oxide layer 18 is coated with a layer 19 of photoresist, which is then patterned to expose portions of masking oxide layer 18. Techniques for forming oxide and photoresist layers, as well as patterning the photoresist layers, are well known to those skilled in the art.

[0014] Now referring to FIG. 2, the exposed portions of oxide layer 18 and the portions of device layer 14 below oxide layer 18 are removed using, for example, a Reactive Ion Etch (RIE) to form trenches 22 and 23, which extend from major surface 17 through device layer 14 and into buffer layer 13. Photoresist layer 19 and oxide layer 18 are removed and the surfaces of trenches 22 and 23 are cleaned. In accordance with this embodiment, trench 23 is wider than trench 22 and will be used as a portion of a termination structure. Although trenches 22 and 23 are illustrated and described as extending into buffer layer 13, it should be understood this is not a limitation of the present invention. For example, trenches 22 and 23 can extend through buffer layer 13 into substrate 12 or their depth can be such that they do not extend into buffer layer 13.

[0015] Still referring to FIG. 2, a P doped polysilicon trench fill material 24 is formed in trenches 22 and 23, using techniques well known to those skilled in the art. Although not shown, polysilicon trench fill material 24 also conformally coats the remaining portion of oxide layer 18. Although trenches 22 and 23 are described as being filled by a polysilicon trench fill material, it should be understood this is not a limitation of the present invention. For example, trenches 22 and 23 can be filled with an epitaxial material, a polysilicon material, or a combination thereof.

[0016] Portions of polysilicon trench fill 24 and oxide layer 18 are removed using, for example, a Chemical Mechanical Polish (CMP) technique to form a planar surface 26. Preferably, the CMP etch terminates at oxide layer 18. Then, oxide layer 18 is removed using, for example, a buffered hydrofluoric acid (HF) solution. This type of etch is commonly referred to as a buffered HF etch. Further, it may be desirable to mask portions of oxide layer 18 prior to performing the buffered HF etch to prevent these portions from being etched. It should be understood that the CMP etch or the combination of the CMP and buffered HF etch serve to planarize the surface of body of semiconductor material 11. The reference number referring to the surface of drift layer 14 has been changed to 26 to reflect the fact that the planar surface includes the portion of polysilicon trench fill 24. Further, polysilicon trench fill 24 cooperates with trenches 22 to form active regions 21 and polysilicon trench fill 24 cooperates with trench 23 to form termination structure 25.

[0017] Now referring to FIG. 3, a layer 29 of dielectric material, commonly referred to as a gate oxide, is formed on planar surface 26. Gate electrodes 31 are patterned over first dielectric layer 29. Gate electrodes 31 are formed from an electrically conductive material such as polysilicon, aluminum, or the like.

[0018] A portion of planar surface 26 is exposed by forming windows in dielectric layer 29. More particularly, the windows expose the portions of planar surface 26 over active regions 21. A plurality of base wells or regions 27 of P-type conductivity are formed in drift layer 14. It will be understood that in an actual device 10 there can be a large number of base wells or P-type conductivity regions 27; however, only two base wells 27 are illustrated for a basic understanding of the invention. Base wells 27, also referred to as base regions, are spaced apart laterally from one another and extend from major surface 26 into polysilicon filled trenches 22. Base wells 27 have a surface concentration of P-type impurity material between approximately 1×10¹⁶and 1×10²⁰atoms/cm³and form PN junctions with portions of drift layer 14. Base wells 27 may have, for example, a maximum width of approximately 40 micrometers and a maximum depth of approximately 8 micrometers. For a 1,200 volt device, a maximum well width of approximately 30 micrometers and a well depth of approximately 4 micrometers have been employed.

[0019] A layer of photoresist (not shown) is patterned over subportions of the exposed portions of planar surface 26. The exposed portions of planar surface 26 adjacent gate electrodes 31 remain exposed after patterning the photoresist.

[0020] A source region 28, also referred to as a source or N-type conductivity region, is formed in each base well 27. Source region 28 is shaped as a toroid, in a plan view (not shown), and thus has a central opening. In the cross-sectional view shown in FIG. 3, this toroid is seen as two source wells of N-type conductivity. A channel is formed in the base region between source regions 27 and drift region 14 which is adjacent major surface 26. Source regions 28 extend from major surface 26 into base wells 27 and have a surface concentration of N-type dopant of between approximately 1×10¹⁷and 1×10²¹atoms/cm³. The doping concentration of source regions 28 is greater than that of base wells 27. By way of example, source regions 28 have a width ranging between approximately 1 and approximately 10 micrometers and a maximum depth of approximately 1.5 micrometers. For example, for a 1,200 volt device, a source width of approximately 3 micrometers and a source depth of approximately 1 micrometer have been employed.

[0021] Although source regions 28 have been described as being a toroid, it should be understood this is not a limitation of the present invention. For example, source regions 28 can be formed as stripes. The photoresist is then removed.

[0022] It should be noted that each gate electrode 31 extends laterally from a portion of a source well 28 in one base well 27 to a portion of a proximal source well 28 in an adjacent base well 27. Thus, gate electrodes 31 extend over two adjacent channels.

[0023] Gate electrodes 31 and exposed portions of dielectric layer 29 are covered by a layer 32 of dielectric material. A portion of planar surface 26 is exposed by forming windows in dielectric layers 29 and 32. More particularly, the windows expose the portions of planar surface 26 over active regions 21 and a portion of polysilicon filled termination well 30. Subsequently, a source electrode or contact 33 is formed over the exposed first portion of planar surface 26 and over dielectric layer 32. Thus, source electrode 33 forms an electrical contact which is over a portion of base wells or regions 27 and a portion of source regions 28. Preferably, source contact 33 is aluminum or an aluminum alloy as is well known in the art.

[0024] An ohmic or conductive layer 36 is formed over surface 15. In a preferred embodiment, ohmic layer 36 is a multi-layer structure comprising a titanium layer, a nickel layer, and a silver layer. The multi-layer structure has a total thickness of about 1-4 micrometers. Substrate layer 12 together with ohmic layer 36 provide a common drain for semiconductor device 10.

[0025] Techniques for the formation of base and source regions 27 and 28, respectively, dielectric layers 29 and 32, gate electrodes 31, source electrode 23, and ohmic layer 36 include conventional semiconductor processing steps such as masking, ion implantation, diffusion, photolithography, etc.

[0026] FIG. 4 is a highly enlarged cross-sectional view of a semiconductor device 40 in accordance with a second embodiment of the present invention. In this embodiment, semiconductor device 40 is an Insulated Gate Field Effect Transistor that is fabricated in the device region of body of semiconductor material 11′. The difference between IGFET 40 and IGFET 10 is that body of semiconductor material 11′ is comprised of substrate 12 and drift layer 14, i.e., buffer layer 13 is absent. In addition, termination structure 25 has been replaced by a plurality of trenches 25′ that are narrower than trench 25. Thus, polysilicon 24 cooperates with trenches 23′ to form a termination structure 25′.

[0027] FIG. 5 is a highly enlarged cross-sectional view of a semiconductor device 50 in accordance with a third embodiment of the present invention. In particular, FIG. 5 illustrates a highly enlarged cross-sectional view of an Insulated Gate Bipolar Transistor (IGBT) 50. Accordingly, the difference between semiconductor device 50 and semiconductor device 40 is that body of semiconductor material 11″ is comprised of a substrate layer 12′ of P-type conductivity on which a buffer layer 13 is formed. Drift layer 14 is disposed on buffer layer 13. Substrate layer 12′ together with ohmic layer 36 provide a common drain for IGBT 50.

[0028] It should be understood that the presence of buffer layer 13 is not a limitation of the present invention and that buffer layer 13 may not be present.

[0029] By now it should be appreciated that a semiconductor device having a termination structure and a reduced on-resistance and a method for manufacturing the semiconductor device have been provided. An advantage of the semiconductor device of the present invention is that it can be used to manufacture power semiconductor devices having a reduced on-resistance using fewer masking steps, thereby lowering the cost of manufacturing the semiconductor device.

[0030] While the invention has been described in specific embodiments thereof, it is evident that many alterations, modifications, and variations will be apparent to those skilled in the art. Further, it is intended to embrace all such alterations, modifications, and variations in the appended claims.