Clamped cascode level shifter circuit

[0002] This invention relates to the field of circuit designs, particularly to voltage level shifter circuits.

[0003] Level shifter circuits are frequently used to translate one voltage level to another. For example, to conserve power, the “core” voltage within an IC frequently operates at low voltage, but is scaled up at the output. A special class of level shifters is the “half bridge drivers” in which complementary signals are applied to an “upper” and “lower” device. In this application, typically the lower device does not require any special signal processing. The upper device requires level shifting in order to provide adequate Gate-Source enhancement, which is necessary because the source potential is not referenced to ground.

[0004] FIG. 1 illustrates a typical half-bridge circuit with a level shifter. Level shifter circuit 10 comprises a first inverter (V1) 16, a pair of control devices 20 and 28 (N1 and N2, respectively), and a cross-coupled pair devices 18 and 24 (P1 and P2, respectively). Complementary signals are applied to N1 and N2 which in combination with P1 and P2 allow node 26 (Q′) to swing between Vboost 11 and ground. A half-bridge circuit 108 comprising transistors 34 and 38 (N3 and N4, respectively) and a boost circuit is generated by diode 32(D1) in combination with “flying capacitor” 30 (C1). A major disadvantage of level shifter circuit 10 is that devices N1, N2, P1 and P2 are all vulnerable to the full voltage excursion from ground to Vboost. This requires special high voltage processing to minimize or avoid the potential of damages to these devices, which adds to manufacturing cost. Furthermore, since the gates of P1 and P2 are driven to twice the voltage as N1 and N2, toggling of these devices from one state to another are further aggravated and made more difficult. There is therefore a need for a level shifter circuit that provides the necessary voltage shifting while minimizing the vulnerability of the level shifter to voltage excursions that may damage the circuit devices, as well as improving performance and minimizing difficulties in toggling devices from one state to another.

[0005] An improved level shifter circuit is provided by toggling a “flying Flip-Flop” comprising a cross-coupled inverter pair with control devices driven out of phase through a pair of cascode transistors. The cross-coupled inverter pair provides pull-up to the positive rail, clamping to a High Side-Common (HSC), and providing Hysteretic Switching. The cascode transistors restrict the pull-down of the control devices, thereby preventing continuous current conduction.

[0006] FIG. 1 illustrates a typical prior art half bridge level shifter circuit;

[0007] FIG. 2 illustrates a clamped cascode level shifter in accordance with the principles of this invention; and

[0008] FIG. 3 illustrates a more detailed block diagram of the level shifter circuit of FIG. 2.

[0009] FIG. 2 illustrates a clamped cascode level shifter in accordance with the principles of this invention. Level shifter circuit 100 comprises a first inverter (V1) 16, a pair of control devices 20 and 28 (N1 and N2, respectively), and a first cascode clamp 102 (P1). In the preferred embodiment, a second cascode clamp (P2), not shown, is also provided for circuit symmetry and improved switching speed and performance (i.e., as shown in FIG. 3). A “flying Flip-Flop” 104 is provided comprising two back to back inverters 110 and 112 (V2 and V3, respectively) with ground return of each inverter coupled to an output of a half bridge circuit comprising switching devices 34 and 38 (N3 and N4, respectively).

[0010] As illustrated in FIG. 2, the source of device P1 is coupled at a voltage equivalent to a gate voltage above ground (i.e., Vg), thus allowing toggling of output node Q′ 113 of inverter pair V2 and V3 between a voltage source rail voltage 12, (i.e., Vboost, wherein Vboost=VDD−VD1) and ground, without current flow between V3 and ground. Consequently, P1 in combination with N2 prevent over current condition in devices V2110 and V4114, and accordingly, thereby limiting voltage excursion that would otherwise damage the gate oxides of devices exposed to excessively large voltage swings, i.e., such as twice the voltage of rail voltage VDD. Overdrive condition of devices V2110 and V4114 and also excessive power consumption in level shifter circuit 100 are also consequently avoided.

[0011] In operation, complementary signals are applied to N1 and N2 via first inverter 16 (V1). Thus, for example, as N2 is switched on, the source of P1 is clamped at one gate voltage (Vg) above voltage at the base of P1 (Vo), thus allowing node 113 (Q′) at an output of Flying Flip-Flop 104 to swing between Vboost and the output rail voltage (Vo) 121. Flip-Flop 104 is toggled by the conduction of N1 and N2, with output Q′ swinging to Vboost when input Q is driven low. Then as Q′ then swing towards voltage Vo, P1 shuts off, thereby preventing quiescent current flow from output of V3 through N2 to ground. In a half bridge driver application such as shown in FIG. 2, clamped cascode level shifter circuit 100 is coupled to a half-bridge circuit 108 comprising transistors 34 and 38 (N3 and N4, respectively) to provide voltage shift. In the preferred embodiment, an optional boost circuit comprising diode 32 (D1) in combination with “flying capacitor” 30 (C1) is also coupled to flying Flip-Flop 104 and cascode clamp P1 to provide current boost for faster transition and increased performance. Optionally, boost ther current circuit further comprises one or more inverters, i.e., V4114 and V5116, for added boost and faster transitions and increased performance.

[0012] In an alternative embodiment, as is illustrated in more detail in FIG. 3, a second cascode clamp P2 is also provided and coupled to N1, to provide similar voltage clamping and current limiting function described above with regards to P1 and N2. Adding P2 provides circuit symmetry and thus also improves switching time and performance.

[0013] FIG. 3 illustrates a sample detailed circuit schematic level implementation of the level shifter circuit of FIG. 2. Thus, the description provided above relative to the operation of cascode clamp level shifter circuit 100 of FIG. 2 also therefore applies to describe the operation of cascode clamp level shifter circuit shown in FIG. 3. Also shown in FIG. 3 is an optional implementation of a second cascode clamp device 103 (P2), not illustrated in FIG. 2, but which as discussed above with FIG. 2 would provide circuit symmetry and improved performance.

[0014] Foregoing described embodiments of the invention are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, Applicant(s) contemplate that functional implementation of invention described herein may be implemented equivalently in hardware, software, firmware, and/or other available functional components or building blocks. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but rather by Claims following.