5-volt tolerant 3-volt drive push-pull buffer/driver

[0002] The present specification generally relates to integrated circuits. More particularly, the present specification describes a buffer/driver system.

[0003] Technology advances in integrated circuit fabrication have led to more compact chip designs. Lower voltage processes come with the smaller size. CMOS devices can use low voltage power supplies to prevent damage to devices having small feature sizes, and to reduce the overall power consumption. For example, power supplies for CMOS devices are being reduced from 3.3 volts to 2.5 volts and lower. However, low voltage CMOS devices often interface with transistor—transistor logic (TTL) devices that operate at higher supply voltages, e.g., 5 volts.

[0004] The Peripheral Component Interconnect (PCI) bus standard, PCI Compliance Checklist, Revision 2.1, published Jan. 1, 1997, requires a minimum of 2.4 volts on the bus to identify a high transition. Typically, there are a large number of buffers and drivers tied to the bus, any of which can be a TTL device. Therefore, each device must be capable of driving at least 2.4 volts, and be able to withstand voltage levels as high as 6.5 volts.

[0005] Another issue with multiple supply voltages is that the different voltages have different characteristics. Some voltages may be stable before others. In a worst case scenario, the highest voltage, e.g., 5 volts, may stabilize first, and already be at its highest level while the other voltages, e.g., 3.3 volts and 1.8 volts, are still at ground or low level. Such an initial condition at power-up could expose low voltage CMOS devices to the full 5 volts. This can cause damage to the device or a shortened life. For example, this could damage the gate oxide in the transistors that form the devices. This situation can be exacerbated by the PCI specification, which requires some of the PIN's to power up at 5 volts.

[0006] The present disclosure describes a buffer/driver system that operates on an input signal to provide an output signal with a sufficient capability at an output terminal to drive a particular interface. The input signal is operated on to produce the output signal that has wider voltage swing than the input signal. Therefore, the devices in a circuit that is producing the input signal can operate with low voltages, while the output signal can drive other circuits with sufficient voltage levels.

[0007] Other embodiments and advantages will become apparent from the following description and from the claims.

[0008] These and other aspects of the invention will now be described with reference to the attached drawings, in which:

[0009] FIG. 1 is a block diagram of one embodiment of a buffer/driver apparatus;

[0010] FIG. 2 is a schematic diagram of a push-pull buffer/driver circuit;

[0011] FIG. 3 is a schematic diagram of an alternative embodiment of the push-pull buffer/driver circuit;

[0012] FIG. 4 is a schematic diagram of a gate voltage protect circuit in the push-pull buffer/driver circuit;

[0013] FIG. 5 is a schematic diagram of an over-voltage detect circuit;

[0014] FIG. 6 is a schematic diagram of a level shifter circuit and a power-up protection circuit;

[0015] FIG. 7 is a schematic diagram of a bias generator; and

[0016] FIG. 8 is a block diagram of a PCI bus system having multiple buffer/driver apparatuses.

[0017] The present disclosure describes one embodiment of a buffer/driver system that can tolerate a TTL voltage level, nominally 5 volts. The system also supplies sufficient drive capability at an output terminal to meet a minimum voltage required by the PCI bus specification. The nominal driving voltage is 3.3 volts. An input signal is level-shifted and divided to produce an output signal with wider voltage swing. For example, the system operates on a zero-to-1.8-volt input data signal to produce a zero-to-3.3-volt output signal.

[0018] FIG. 1 shows a block diagram of one embodiment of a buffer/driver apparatus. The apparatus includes a level shifter circuit 102, a push-pull buffer/driver circuit 104, an over-voltage detect circuit 106, and a power-up protection circuit 108.

[0019] The level shifter circuit 102 shifts and divides the small input voltage swing into two complementary signals, P_up120 and P_down122, each signal driving a pull-up or a pull-down signal for the push-pull circuit. For one embodiment, the input signal, Data-In 114, swings between zero and about 1.8 volts. When Data-In 114 is at logic high (1.8 volts) , P_downis set to zero volts while P_upis set to 1.9 volts. When Data-In 114 is at logic low (zero volts), P_downchanges to 1.8 volts while P_upchanges to 3.3 volts. When tri-state is enabled (i.e. {overscore (Tri-state Enable)} signal set to zero), both P_downand P_upis de-asserted with P_downset to zero volts and P_upset to 3.3 volts.

[0020] The push-pull buffer/driver circuit 104 is driven by two different level-shifted signals. One is a pull-up signal and the other is a pull-down signal. The circuit provides the PIN 112 with a wide voltage swing sufficient to drive other apparatuses that are tied directly to the PIN 112 or to a bus. The pull-down and the pull-up signals are combined in a push-pull transistor configuration to produce the wider voltage swing. The circuit also protects transistors from high voltage signals, such as 5 volts, on the PIN 112.

[0021] The over-voltage detect circuit 106 detects when the PIN 112 is receiving a high voltage, e.g., above 3.3 volts. If the PIN is already being subjected to a high voltage, the over-voltage detect circuit 106 generates a flag 124. The flag 124 prevents the push-pull buffer/driver circuit from trying to drive the PIN and thereby expose the low voltage supplies to the high voltage.

[0022] The power-up protection circuit 108 protects devices in the level shifter circuit 102 and the push-pull buffer/driver circuit 104 from being exposed to the full extent of the high voltages during power-up. The devices that need protection include CMOS devices that are highly susceptible to damage due to high voltages and static potentials. The power-up protection circuit generates a bias voltage from the first supply voltage that comes up at power up. The first supply voltage is usually the highest supply voltage, such as 5-volt supply. The generated bias voltage is applied to the other supply voltages at power-up to avoid exposing devices to high voltage differences.

[0023] An example of an operation of the power-up protection circuit is as follows: at power-up, the low voltage supplies, such as 1.8 volts and 3.3 volts, may still be at ground level while the PIN and the 5-volt supply is already at its peak level; the bias generator 110 generates 1.6 volts and 2.5 volts from the 5-volt supply and applies them to the low voltage supplies; the result is the reduction of exposure to high voltage differences for delicate devices by as much as 50%.

[0024] FIG. 2 is a schematic diagram of the push-pull buffer/driver circuit 104 according to one embodiment of the present disclosure. According to the disclosure, p-channel metal-oxide semiconductor (PMOS) transistor P21 act as a pull-up transistor that pulls up the node 224 when P_upis active. NMOS transistor N21, analogously acts as a pull-down transistor. Hence, the circuit is in a push-pull configuration. Transistors P22 and N22 are voltage protection transistors that protect transistors P21 and N21 by limiting the voltage swings across the terminals of those transistors P21 and N21.

[0025] The voltage at node 224 is limited to the voltage at the gate terminal of transistors P22 plus a p-channel threshold voltage. The voltage at node 226 is limited to the voltage at the gate terminal of transistor N22 minus an n-channel threshold voltage.

[0026] Pass-gate transistor PP1 controls cut off of node 224 from the PIN 112 when a high voltage is present on the PIN. The gate terminal of the pass-gate transistor PP1 is protected by GPROT 212. When the PIN 112 is at 5 volts, GPROT 212 is biased at about (3+V_tp) volts, where V_tpis a PMOS threshold voltage. The bias at GPROT 212 passes the 5 volts present on the PIN 112 to the PROTECT node 206. This, in turn, cuts off transistor P22 and isolates node 224. This operation protects transistor P21 which could otherwise short between the 3.3-volt supply 202 and the 5 volts present on the PIN 112. Therefore, the 5 volts can only appear on the PIN when the buffer/driver system is in a receiving mode with the output in tri-state. The gate terminal of transistor P21 is protected by the {overscore (Tri-state Enable)} signal 116. Logic low on the {overscore (Tri-state Enable)} 116 keeps P_up204 at 3.3 volts, thereby turning off transistor P21 and isolating V_pp202 from node 224.

[0027] Transistor N22 is a vertical double-diffused n-channel MOSFET (VDNMOS) device that has two or more of the semiconductor regions formed by diffusion. Source and drain electrodes are on opposite wafer surfaces so that a current flow is substantially perpendicular to the wafer surfaces. VDNMOS devices are typically used in power switching applications where the source electrode is near ground potential and the drain electrode is biased at very high potential.

[0028] The pull-down transistor N21 is protected by voltage protection transistor N22 in a cascode configuration. Node 226 is limited to (1.8−V_tn) volts by transistor N22, where V_tnis an NMOS threshold voltage. VDNMOS transistor N22 can tolerate 5 volts on its drain terminal with its source terminal at (1.8−V_tn) volts. If VDNMOS transistor N22 can tolerate over 6 volts, then the transistor N21 can be eliminated with node 226 tied to the ground. The gate terminal of N22 then should be tied to P_downinstead of the 1.8-volt supply.

[0029] FIG. 3 is a schematic diagram of an alternative embodiment of the push-pull buffer/driver circuit 104. This embodiment is similar to the embodiment of FIG. 2, but with additional transistors that control PROTECT node 322 shown. Transistors N33, P33 and N34 enable transistor P32 to drive the PIN 112 to 3.3 volts and disable transistor P32 when the PIN 112 is already at 5 volts.

[0030] When the PIN 112 is at 5 volts, ‘PIN Below 3V’ signal 324 is de-asserted and set to zero volts. The low ‘PIN Below 3V’ signal turns off pull-down transistor N34 through an AND gate 320. This allows transistor PP2 to pass the 5 volts on the PIN 112 to PROTECT node 322 and to turn off transistor P32. This configuration yields a circuit in high-impedance, tri-state mode. Generation of the ‘PIN Below 3V’ signal is described in detail under description for FIG. 5.

[0031] When the PIN 112 needs to be driven to 3.3 volts, in response to a logic high in Data-In 114 signal, P_up204 is at 1.9 volts, P_down210 at zero volts, and {overscore (P_down+L )} 326 at 1.8 volts. In response to above voltages on the gate terminals of transistors P31, N31 and N34, transistors P31 and N34 turn on while transistor N31 turns off.

[0032] Transistor N34 turns on and pulls PROTECT node 322 toward ground potential. Node 328 is driven to zero volts. However, transistor P33 prevents node 330 from going too low. The bias of 1.6 volts on the gate terminal of transistor P33 keeps node 330 at approximately 1.9 volts (1.6+V_tp). The biasing of node 330 is important in protecting the source terminal of VDNMOS transistor N33 since VDNMOS is a directional device. With node 330 biased at 1.9 volts, the PROTECT node 322 is also pulled to about 1.9 volts. This turns on transistor P32 and drives the PIN 112 to 3.3 volts with current flowing from the PIN 112 terminal to V_pp202. Transistor N32 protects node 336 and transistor N31 with cascode configuration.

[0033] When the PIN 112 needs to be driven to zero volts, in response to a logic low in Data-In 114 signal, P_up204 is at 3.3 volts, P_down210 at 1.8 volts, and {overscore (P_down+L )} 326 at zero volts. This turns transistors P31 and N34 off and turns transistor N31 on. The pull-down stack, N33/P33/N34, tied to the PROTECT node 322 is disabled. Transistor N32 has its gate tied to 1.8 volts, keeping it always on. Transistor N31 therefore turns on to pull the PIN 112 to zero volts. If VDNMOS transistor N32 can tolerate over 6 volts, then the transistor N31 can be eliminated with node 336 tied to the ground. The gate terminal of N32 then should be tied to P_downinstead of the 1.6-volt supply.

[0034] The gate voltage protect circuit 300 drives GPROT 212 to (1.8−V_tp) volts, thereby protecting transistor PP2 from high voltage bias. The PROTECT node 322 is biased to about 1.8 volts via transistor PP2. This, in turn, keeps node 334 biased to about 2.5 volts (1.8+2V_tp) and protects the gate terminal of transistor P31 which is at 3.3 volts.

[0035] The case of receiving zero volts is substantially the same as the driving zero volt case. The differences are the P_downsignal 210 is at zero volts, turning off transistor N31.

[0036] The inputs to AND gate 320 turn transistor N34 on only if the tri-state mode is disabled, the PIN 112 is below 3.3 volts, and the pull-down signal is at logic low. Therefore, transistor N34 is turned off when the circuit is in voltage receiving mode.

[0037] FIG. 4 is a schematic diagram of the gate voltage protect circuit 300 in the push-pull buffer/driver circuit 104 according to the preferred embodiment of the present disclosure. This circuit pushes and pulls the signal GPROT 212 to protect the gate terminal of the pass-gate transistor PP2. The circuit pulls GPROT 212 high to about 3 volts when 5 volts is on the PIN 112 and pushes GPROT 212 low to about two volts when the PIN 112 is at zero volts. Therefore, GPROT 212 swings between two and three volts.

[0038] During normal operation, transistor N41 drives node 400 to about 3 volts (V_pp−V_tn). However, during power-up, if V_ppis at zero volts, P41 turns on and node 400 gets driven through P41 to 2.5 volts.

[0039] When the PIN 112 is at zero volts, transistor P44 turns off and transistor N43 turns on, making a current path from GPROT 212 to the PIN via P43 and N43. This pulls GPROT 212 low. Transistor P43 limits GPROT 212 voltage to about two volts (1.6+V_tp). VDNMOS transistor N44 clamps GPROT above (1.6−V_tn) volts.

[0040] When the PIN 112 is at 5 volts, transistor P44 turns on and transistor N43 turns off, pulling GPROT 212 high. Transistor N42 limits GPROT 212 voltage to about (3.0+V_tn) volts. Transistor P42 clamps GPROT below (3.3+V_tp) volts.

[0041] The clamp devices P42 and N44 are desirable due to high Miller capacitance on transistor PP2 in the push-pull buffer/driver circuit. The devices prevent the gate of transistor PP2 from swinging too far and too hard. Furthermore, during fast operation, the Miller capacitance of PP1 becomes the primary mover of the GPROT 212 signal, making P42 and N42 critical.

[0042] FIG. 5 shows a schematic diagram of the over-voltage detect circuit 106 according to the preferred embodiment of the present disclosure. A main function of this circuit is to avoid driving PROTECT node 322 below two volts when the PIN 112 is at 5 volts. That is, if the PIN is at 5 volts, this circuit prevents the buffer/driver from driving PIN to 3.3 volts. Otherwise, the pull-up circuitry would be stressed from attempting to drive the circuitry in this way.

[0043] PIN 112 is connected to the source of the transistor P51. When the PIN 112 goes to zero volts, p-channel metal-oxide semiconductor field-effect transistors (PMOSFETs) P51 to P53 turn off. Node 500 is pulled low via transistor N53. Transistor P54 and inverter 502 “latch” the logic low on node 500 to a logic high on node 504. The logic high voltage of 1.8 volts on node 504 turns transistor N51 on and pulls ‘PIN Above 3 V’ node 506 to an inactive logic low of 0 volts. This drives ‘PIN Below 3 V’ signal to an active logic high of 1.8 volts via inverters 508 and 510. Transistors P51 and P53 protect transistor P52 when the PIN 112 and ‘PIN Above 3 V’ node 506 are at zero volts, respectively.

[0044] When the PIN 112 is at 5 volts, node 500 is pulled high via cascode transistor N53. Transistor P54 and inverter 502 “latch” the logic high on node 500 to a logic low on node 504. This turns transistor N51 off. At the same time, PMOSFET transistors P51 to P53 are turned on, pulling ‘PIN Above 3 V’ node 506 up via VDNMOS transistor N52. Transistor P52 allows ‘PIN above 3V’ node 506 to pull up only when the PIN 112 is above 3.3 volts. Transistor N52 limits the pull-up voltage to about (1.6−V_tn) volts to avoid high voltages on ‘PIN above 3V’ node 506.

[0045] FIG. 6 is a schematic diagram of the level shifter circuit 102 and the power-up protection circuit 108 according to the preferred embodiment of the present disclosure. The power-up protection circuit 108 includes a diode chain 604 and transistors P61 to P66. The diode chain 604 is preferably formed from diode-connected parasitic PNP transistors.

[0046] Initially, at power-up, the diode chain 604 is forward biased. Therefore, the transistor P61 is turned on. This, in turn, charges node 602 to about 2.2 volts. There is a DC current path between the diode chain 604 and V_ppbecause transistor P66 is turned on initially. Transistor P65 balances the differential stage formed by P66 and P67. Once all the voltages are powered up, the diode chain 604 will shut-off and remain quiescent.

[0047] During power-up, a 5-volt supply can be at its highest level while V_ppis still at a ground level. In this situation, the gate terminals of transistors P61 to P64, which are connected to V_pp, are at zero volts. Hence, PMOS transistors P61 to P64 are turned on. The pull-up nodes 606, 608 and 204 are immediately charged to 2.5 volts, since 2.5 volts is generated from the 5-volt supply.

[0048] The charging of the pull-up node 204 to 2.5 volts turns transistor P31 off when V_ppis at 0 volts. Node 334 is isolated from V_ppand is charged to (2.5+V_tp) volts. Since the PIN also powers up at 5 volts, charging of node 334 to (2.5+V_tp) volts protects transistor P32 from being exposed to full 5 volts across its source-to-gate and source-to-drain terminals.

[0049] Once all the voltage supplies power up to their peak level, the level shifter circuit enters normal operation and PMOSFET transistors P61 through P64 are turned off. In normal level shifter operation, the input data switches between zero and 1.8 volts. This allows VDNMOS differential transistor pair N61 and N62 to direct current through current paths 610 or 612. Assuming {overscore (Tri-state Enable)} 116 signal is inactive high, selecting the tri-state mode to disabled, a NAND gate 622 and a NOR gate 624 act as inverters. Therefore, when Data-In 114 is a logic high, the gate terminal of transistor N61 is a logic low and the gate terminal of transistor N62 is a logic high. Transistor N61 is off and transistor N62 is on. As transistor N62 turns on, it pulls node 606 toward ground by discharging current 612 through the voltage protection transistor P611. When the node 606 drops to about (1.6+V_tp) volts, transistor P611 turns off and prevents further discharging of the node 606. Thus, the voltage protection transistor P611 bounds the voltage swing of node 606 to between about 1.9 and 3.3 volts.

[0050] Since the gate of transistor P66 is tied to node 606, the low level on node 606 turns transistor P66 on and pulls node 602 up toward V_pp, which is at 3.3 volts. The logic high on node 602, which is tied to the gate of transistor P67, turns transistor P67 off. As node 602 rises, transistor P610 turns off and halts discharging of the current 610.

[0051] Logic low on Data-In 114 operates similarly with transistor N61 on and transistor N62 off. Node 606 is charged to high voltage near 3.3 volts. Hence, the node 606 is the pull-up node that responds inversely to Data-In 114 signal, producing about 1.9 volts when Data-In 114 is at logic high and 3.3 volts when Data-In 114 is at logic low.

[0052] Transistors P68, P612, N63 and P69, P613, N64 represent two stages of gain amplifiers to give greater drive for the level-shifted pull-up output 204. The level-shifted pull-up output 204 follows node 606. If node 606 is 1.9 volts, transistor P68 turns on pulling node 608 to 3.3 volts, thereby turning P69 off. P_upnode 204 gets biased to 1.9 volts by P613. On the other hand, if node 606 is 3.3 volts, transistor P68 turns off, and biases node 608 to 1.9 volts via transistor P612, thereby turning transistor P69 on. P_upnode 204 gets pulled up to 3.3 volts through transistor P69.

[0053] A series of inverters 620 are used to synchronize the pull-down signal 210 with the pull-up signal 204. The inverters are powered by a 1.8-volt supply 660 and a ground voltage supply 662. When the tri-state mode is disabled, node 630 is at logic high or 1.8 volts. Thus, when Data-In 114 is at logic low, node 632 is also at logic low and the output of a NAND gate 622 becomes logic high. On the other hand, when Data-In 114 is at logic high, node 632 is at logic high and the output of the NAND gate 622 becomes logic low. Therefore, the NAND gate 622 acts as an inverter when the tri-state mode is disabled.

[0054] Node 634 is pulled to logic high when Data-In 114 is at logic low. This, in turn, drives node 636 to logic low via a NOR gate 624. Similarly, when Data-In 114 is at logic high, node 636 is at logic high. Therefore, when Data-In 114 is at logic low, the gates 622 and 624 turn transistor N61 on and transistor N62 off. When Data-in 114 is at logic high, the gates 622 and 624 turn transistor N61 off and transistor N62 on.

[0055] Nodes 638 and 640 are driven to logic high and logic low, respectively, in response to Data-In 114 at logic low. Similarly, nodes 638 and 640 are driven to logic low and logic high, respectively, in response to Data-In 114 at logic high. Thus, transistor N63 turns on and transistor N64 turns off when Data-In 114 is at logic low.

[0056] When the node 638 is at logic high, in response to logic low at Data-In 114, a NAND gate 626 and five inverters 620 drive the pull-down signal to logic high, or 1.8 volts. However, the pull-down signal is slightly delayed to synchronize it with the delayed pull-up signal 204. Similarly, a logic high at Data-In 114, drives node 638 and the pull-down signal to logic low, or zero volts.

[0057] The NAND gates 622 and 626 and the NOR gate 624 are used to disable pull-up and pull-down stacks of the push-pull buffer/driver circuit during high-impedance, tri-state mode. With {overscore (Tri-state Enable)} 116 signal at logic low, meaning the tri-state mode is enabled, the outputs of NAND gates 622 and 626 are forced to logic high while the output of NOR gate 624 is forced to logic low. This configuration keeps P_up204 at 3.3 volts and P_down210 at zero volts when 5 volts or zero volts is being received on the PIN out 112 to protect pull-up and pull-down transistors.

[0058] FIG. 7 shows a schematic diagram of a bias generator. The bias generator generates two intermediate voltages, 1.6 volts and 2.5 volts, from 3.3-volt and 5-volt supplies respectively. The 2.5-volt output is used during power up to protect transistor devices when 5-volt supply is fully charged and 3.3-volt supply is not charged at all. The 1.6-volt output is used as an intermediate bias voltage.

[0059] FIG. 8 shows a block diagram of a PCI bus system having multiple buffer/driver apparatuses. The PCI bus system can interconnect a large number of electronic devices. The system must maintain, manage and communicate bi-directional data from one device to another device or several devices at once. Each device may output different voltage levels while maintaining capability to read data on the bus. Some devices may even be of low voltage type that are incapable of driving the bus by itself. Therefore, each device may require a buffer/driver apparatus, such as the one described above, for effective management and communication of data.

[0060] The buffer/driver apparatus described above can also be used in many other applications similar to the PCI bus system including an integrated drive electronics (IDE) interface system, a parallel port computer interface system, and input/output (I/O) pads.

[0061] Although only a few embodiments have been described in detail above, those of ordinary skill in the art certainly understand that modifications are possible. All such modifications are intended to be encompassed within the following claims, in which: