Method for forming polycide dual gate

[0002] 1. Field of the Invention

[0003] The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a polycide dual gate.

[0004] 2. Description of the Related Art

[0005] When integration of elements in integrated circuit (IC) increases to achieve deep sub-micron processes, a dual gate having N-type gate and P-type gate is necessary. A tungsten silicide layer having low resistance is formed on a doped polysilicon layer, and then the tungsten silicide layer and the doped polysilicon layer are defined to form a polycide gate.

[0006] FIG. 1 is schematic three-dimensional view showing a conventional polycide dual gate. Referring to FIG. 1, a substrate 40 is provided, a gate oxide layer 42 is deposited on the surface of the substrate 40, and a polysilicon layer 44 is formed on the gate oxide layer 42. An N-type and P-type ion implantation step is performed on the polysilicon layer 44 to form a dual gate 48; the dual gate 48 comprises an N-type (or P-type) gate 44′ and P-type (or N-type) gate 44″. The tungsten silicide layer 46 is directly formed on the polysilicon layer 44 to increase conductivity of the dual late 48. The method causes the interdiffusion 50 of N-type and P-type ions in the dual gate 48 through the tungsten silicide layer 46 while a thermal process is performed, and the interdiffusion 50 phenomenon will induce devices failure.

[0007] FIGS. 2A through 2C are schematic. cross-sectional views showing the progression of another conventional manufacturing steps for a polycide dual gate. Referring to FIG. 2A, a substrate 10 that has an isolation structure 11 is provided; the isolation structure 11 is filled with insulation material. A gate oxide layer 12 is deposited on the surface of the substrate 10, a polysilicon layer 14 is deposited on the gate oxide layer 12, and an oxide layer 16 is formed on the polysilicon layer 14 by chemical oxidation (or chemical vapor deposition or thermal oxidation). A amorphous silicon layer 18 (α-Si layer ) is formed on the surface of the oxide layer 16, and an N-type and P-type ions implantation step is performed. An annealing step is performed to restore the surface crystal structure of the α-Si layer 18, and then a tungsten silicide layer 20 is formed over the α-Si layer 18. Since the N-type and the P-type ions in the dual gate diffuse through the tungsten silicide layer 20 while a thermal process is performed, in this invention, the oxide layer 16 is provided as a impurity diffusion barrier layer in order to prevent the interdiffusion. Because the tungsten silicide layer 20 does not have good adhesion with the oxide layer 16, hence the α-Si layer 18 having low resistance is formed between the tungsten silicide layer 20 and the oxide layer 16 to improve the adhesion and the conductivity, then a stack structure comprising the tungsten silicide layer/α-Si layer/oxide layer/polysilicon layer/gate oxide layer is made. However, the stack structure results in increased RC time delay of the polysilicon layer 14 and easily changes the original MOS structure into an E²PROM structure. This change will affect device performance.

[0008] Referring to FIG. 2B, the tungsten silicide layer 20, the α-Si layer 18, the oxide layer 16, the polysilicon layer 14 and the gate oxide layer 12 are defined to become a tungsten silicide layer 20a, an α-Si layer 18a, an oxide layer 16a, a polysilicon layer 14aand a gate oxide layer 12aby dry etching to form a gate region. The gate region is used as a mask, and a lightly doped source/drain region 22 is formed beside the gate in the substrate 10 by an ion implantation step. A silicon dioxide layer 24 is formed conformal to the substrate 10.

[0009] As shown in FIG. 2C, a spacer 24ais formed on the sidewall of the gate when the silicon dioxide layer 24 is etched back by dry etching. The spacer 24aand the gate are used as a mask, and a heavily doped source/drain region 26 is formed beside the spacer 24ain the substrate 10 by an ion implantation step. An annealing step is performed to restore the surface crystal structure of the heavily doped source/drain region 26 by rapid thermal processing (RTP).

[0010] Semiconductor miniaturization results in increasing the contact resistance of the interface between different layers. Therefore the dopant concentration of contact surface must be sufficient high to attain sufficient low contact resistance. In the conventional method for forming a polycide dual gate, the α-Si layer has a low dopant concentration, hence the RC time delay of polysilicon gate is still high. The oxide layer prevents interdiffusion of dopants but results in changing the original MOS structure into an E²PROM or EPROM structure, which change will affect device performance. The α-Si layer is formed between the tungsten suicide and the oxide layer to enhance adhesion between both of them, but the structure becomes complicated.

[0011] Accordingly, the present invention provides a method for forming a polycide dual gate. This method can reduce RC time delay and simplify the structure of devices to favor the electrical performance of devices and decrease the capital expenditure.

[0012] To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a polycide dual gate. A substrate that has an isolation structure is provided, a polysilicon layer (or a α-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a doped polysilicon layer that has both N-type and P-type. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a gate, and a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0014] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0015] FIG. 1 is schematic, three-dimensional view showing a conventional polycide dual gate;

[0016] FIGS. 2A through 2C are schematic, cross-sectional views showing the progression of another conventional manufacturing steps for a polycide dual gate;

[0017] FIG. 3 is schematic, top view showing a polycide dual gate according to the preferred embodiment of this invention; and

[0018] FIGS. 4A through 4C are schematic, cross-sectional views showing the progression of manufacturing steps for a polycide dual gate according to FIG. 3 of cross-sectional line 4—4 in the preferred embodiment of this invention.

[0019] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0020] FIG. 3 is schematic, top view showing a polycide dual gate according to the preferred embodiment of this invention. Referring to FIG. 3, a substrate 200 having a gate 202 is provided, N-type and P-type ions are implanted into the gate 202 to form a dual gate 204 having a first type gate 202′ such as an NMOS gate and a second type gate 202″ such as a PMOS gate. A first type source/drain region 206 and a second type source/drain region 208 are formed in the substrate 200.

[0021] FIGS. 4A through 4C are schematic. cross-sectional views showing the progression of manufacturing steps for a polycide dual gate according to FIG. 3 of cross-sectional line 4—4 in the preferred embodiment of this invention. Referring to FIG. 4A, a substrate 100 that has an isolation structure 101 is provided. The isolation structure 101 is filled with insulation material. A gate oxide layer 102 is deposited on the surface of the substrate 100, a polysilicon layer 104 (or an α-Si layer) is deposited on the gate oxide layer 102, for example, by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0022] N-type dopants such as arsenic or phosphorus and P-type dopants such as boron ions are implanted into the polysilicon layer 104 of a dual gate to form a doped polysilicon layer having N-type and P-type dopants. An annealing step is performed to restore the surface crystal structure of the polysilicon layer 104, an oxide layer 106 is formed on the polysilicon layer 104, for example, by chemical oxidation (or CVD or thermal oxidation), and a suicide layer 108 such as a titanium silicide (TiSi_x) or a cobalt silicide (CoSi_x) layer is formed over the oxide layer 106. In the conventional method for forming a polycide dual gate, the doped polysilicon layer and the tungsten silicide (WSi_x) constitute the polycide because the conductivity of the tungsten silicide is better than the conductivity of the doped polysilicon layer. However, the resistance of the tungsten silicide is still high, and the resistance of the titanium silicide is lower than the tungsten silicide by about 3-5 times, therefore the RC time delay of polysilicon layer 104 and the conductivity are better than before when a complex stack gate is made.

[0023] When integration of elements in integrated circuit (IC) increases to achieve deep sub-micron processes, the interdiffusion of dopants through the tungsten silicide layer is more serious. Therefore, the present invention relates to a method for forming a polycide dual gate using a titanium silicide or a cobalt silicide instead of the tungsten silicide used in the conventional method. In addition to the silicide layer 108 such as a titanium silicide and the oxide layer 106 preventing interdiffusion of N-type and P-type dopants implanted into polysilicon layer in the dual gate during thermal processes, the titanium silicide 108 and the oxide layer 106 also have good adhesion, so the process of forming an α-Si layer is not necessary. This invention can eliminate interdiffusion and simplify the structure to maintain device performance and reduce capital expenditure. Also, the titanium silicide 108 reacts with the oxide layer 106 to produce spiking and penetrate through the oxide layer 106 (the thickness of the oxide layer cannot be thick). The method does not allow the original MOS structure to change into an E²PROM or EPROM structure by the spiking.

[0024] Referring to FIG. 4B, the silicide layer 108, the oxide layer 106, the polysilicon layer 104 and the gate oxide layer 102 are defined to become a silicide layer 108a, an oxide layer 106a, a polysilicon layer 104aand a gate oxide layer 102ato form a gate region. The gate region is used as a mask, and a lightly doped source/drain region 110 is formed beside the gate in the substrate 100, for example, by an ion implantation step. An oxide layer 112 such as silicon dioxide is formed conformal to the substrate 100.

[0025] As shown in FIG. 4C, a spacer 112ais formed on the sidewall of gate when the oxide layer 112 is etched back, for example, by dry etching. The spacer 112aand the gate are used as a mask; a heavily doped source/drain region 114 is formed beside the spacer 112ain the substrate 100, for example, by an ion implantation step. An annealing step is performed to restore the surface crystal structure of the heavily doped source/drain region 114, for example, by rapid thermal processing (RTP).

[0026] (1) The invention for manufacturing a polycide dual gate provides a titanium silicide instead of tungsten silicide, in order to reduce the RC time delay when the complex stack gate is made.

[0027] (2) The invention for manufacturing a polycide dual gate provides a titanium silicide or a cobalt silicide and an oxide layer to prevent interdiffusion of N-type and P-type dopants implanted into polycide layer in the dual gate during thermal processes, therefore the invention can maintain device performance.

[0028] (3) The invention for manufacturing a polycide dual gate provides a titanium silicide layer, because the titanium suicide layer has a good adhesion with the oxide layer, the processes of forming a α-Si layer is not necessary, this invention can simplify the structure and reduce capital expenditure.

[0029] (4) The invention for manufacturing a polycide dual gate provides a titanium silicide layer; the titanium silicide reacts with the oxide layer to result in spiking and penetrates through the oxide layer. The method can prevent the original MOS structure from changing into an E²PROM or EPROM structure by the spiking so that device performance is maintained.

[0030] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.