Method for the fabrication of a doped silicon layer

[0002] The invention relates to a method for the fabrication of a doped silicon layer.

[0003] Low-impedance conductive elements are needed in a diversity of applications, for example as contacts or electrodes. Examples of such applications are a gate electrode of an MOS transistor in a CMOS configuration or a selector transistor in a DRAM, a contact for a bipolar transistor or a conductive connection between a selector transistor and a storage capacitor in a DRAM memory cell.

[0004] The use of conductive elements containing a silicide layer is known for applications of that kind (see, for example, a book entitled “Technologie hochintegrierler Schaltungen” [Technology of Large-Scale Integrated Circuits], by D. Widmann et al., Springer Verlag 1988, pages 95-96 and 215-216). The use of silicide requires additional equipment and it furthermore increases the costs of the fabrication process as a result.

[0005] It is accordingly an object of the invention to provide a method for the fabrication of a doped silicon layer, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and which can be used in the fabrication of low-impedance conductive elements as well as a microelectronic structure with a low-impedance conductive element.

[0006] With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the fabrication of a doped silicon layer, which comprises depositing a silicon layer by using a process gas containing SiH₄, Si₂H₆and a doping gas; and carrying out the deposition in a CVD reactor within a temperature range between 600° C. and 680° C. and within a pressure range between 100 torr and atmospheric pressure.

[0007] It was established that, in the method, the addition of Si₂H₆to a process gas containing SiH₄and a doping gas promotes the incorporation of dopant into the deposited silicon layer. In this way lower resistivities are achieved in the deposited layer than would be the case when using a process gas containing SiH₄and a doping gas. The addition of Si₂H₆also increases the rate of deposition. Thus the method achieves lower resistivities at higher deposition rates.

[0008] In accordance with another mode of the invention, the ratio of Si₂H₆to SiH₄preferably has a value between 1:1.5 and 1:6. The ratio of Si₂H₆to SiH₄is preferably 1:3 to 1:6. The doped silicon layer deposited according to this method is essentially polycrystalline.

[0009] In accordance with a further mode of the invention, an activation of the dopant preferably takes place through heat treatment after the deposition. The heat treatment is carried out in a temperature range between 1000° C. and 1200° C., preferably between 1050° C. and 1100° C.

[0010] In accordance with an added mode of the invention, the doped silicon layer is especially suitable as a starting material for the fabrication of a conductive element of doped silicon that has a resistivity less than or equal to 0.5 mΩcm at a layer thickness between 50 nm and 200 nm. In this case the ratio of Si₂H₆to SiH₄during deposition is set at 1:3 to 1:6.

[0011] Due to its resistivity, the conductive element can be used as a gate electrode, a bipolar contact or a connection between electrical components. Due to the deposition rate of 50 nm per minute achieved in the method according to the invention, the conductive element can be fabricated inexpensively.

[0012] In accordance with an additional mode of the invention, the conductive element can be disposed on any required surface, especially on a level surface, above a step, or in a trench.

[0013] In accordance with a concomitant mode of the invention, when depositing the doped silicon layer above a step in a surface of a substrate, a good conformity is achieved in covering the edge of the step. The conformity, i.e. the ratio of the thickness of the layer at the essentially vertical surfaces to the thickness of the layer at the essentially horizontal surfaces, is at least 50 percent.

[0014] Other features which are considered as characteristic for the invention are set forth in the appended claims.

[0015] Although the invention is illustrated and described herein as embodied in a method for the fabrication of a doped silicon layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

[0016] The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

[0017] FIG. 1 is a fragmentary, diagrammatic, cross-sectional view of a substrate on which a doped silicon layer has been deposited;

[0018] FIG. 2 is a fragmentary, cross-sectional view of an MOS transistor; and

[0019] FIG. 3 is a fragmentary, cross-sectional view of a DRAM memory cell.

[0020] Referring now to the figures of the drawings in detail and first, particularly, to FIG. 1 thereof, there is seen a doped silicon layer 3 which is deposited on a substrate 1 of monocrystalline silicon in a CVD process. The substrate 1 includes a main surface having a step with a side 2 essentially perpendicular to the main surface. A process gas which is used for this purpose contains SiH₄, Si₂H₆, PH₃and H₂or N₂as a carrier gas. The flow of SiH₄is 295 sccm, the flow of Si₂H₆is 100 sccm and the flow of PH₃is 295 sccm. At a deposition temperature of 650° C. and a pressure of 650 torr, the doped silicon layer 3 is deposited in a thickness of 159 nm with a deposition rate of 53 nm per minute. In this way a dopant concentration of 1.8×10²¹cm⁻³is achieved. After activation by heating at 1050° C., the doped silicon layer 3 a resistivity ρ of 0.46 mΩcm. The conformity of the deposition is 58 percent. The conformity is defined as the quotient of a thickness Δx of the doped silicon layer 3 at the side 2 and a thickness Δy of the doped silicon layer 3 at the horizontal surface of the substrate 1.

[0021] If the deposition proceeds with the same parameters and an activation heat treatment is carried out at 1100° C., a resistivity ρ of 0.402 mΩcm is achieved at a layer thickness of 156 nm.

[0022] If the doped silicon layer is deposited through the use of a process according to the state of the art in which only SiH₄without Si₂H₆is used in the process gas, a deposition rate of 16 nm per minute is achieved with a flow of 295 sccm of SiH₄, 295 sccm of PH₃and 13 liters of carrier gas containing H₂. After activation heat treatment at 1100° C. with a layer thickness of 58 nm, a dopant concentration of 1.3×10²¹cm⁻³and a resistivity ρ of 0.510 mΩcm is achieved.

[0023] The conformity Δx/Δy is increased by reducing the proportion of the doping gas. Thus a conformity Δx/Δy of 86 percent is achieved in a deposition with 295 sccm SiH₄, 100 sccm Si₂H₆and 50 sccm PH₃. A conformity Δx/Δy of 90 percent is achieved in a deposition with 295 sccm SiH₄, 100 sccm Si₂H₆and 5 sccm PH₃.

[0024] Upon deposition of the doped silicon layer 3 with 295 sccm SiH₄, 20 sccm Si₂H₆, 295 sccm PH₃and 13 liters of H₂a deposition rate of 21 nm per minute is observed. After activation heat treatment at 1100° C. with a layer thickness of 105 nm, a dopant concentration of 1.6×10²¹cm⁻³and a resistivity ρ of 0.54 mΩcm is achieved.

[0025] Upon deposition of the doped silicon layer 3 with 295 sccm SiH₄, 200 sccm Si₂H₆, 295 sccm PH₃and 13 liters of H₂a deposition rate of 102 nm per minute is observed. After activation heat treatment at 1050° C. with a layer thickness of 152 nm, a dopant concentration of 1.05×10²¹cm⁻³and a resistivity ρ of 0.51 mΩcm is achieved.

[0026] The doped silicon layer 3 has an essentially polycrystalline grain structure. As is seen in FIG. 2, through deposition of a doped silicon layer in a CVD process and subsequent structuring of the doped silicon layer, a gate electrode 24 is formed through addition of the Si₂H₆into an MOS transistor. The MOS transistor has source/drain regions 22 in a silicon substrate 21 and has a gate oxide layer 23 at a surface of the silicon substrate 21. The doped silicon layer is deposited in a CVD process with SiH₄, Si₂H₆, PH₃and H₂as a process gas. The gas flows which are used are:

[0027] The deposition temperature is 650° C. and the deposition pressure is 650 torr. The doped silicon layer is created at a deposition rate of 52 nm per minute in a layer thickness of 156 nm. After heat treatment at 1100° C. it has a dopant concentration of 1.8×10²¹cm⁻³and a resistivity ρ of 0.402 mΩcm. Structuring of the doped silicon layer is performed through anisotropic etching, for example with Cl₂, HBr. The MOS transistor is especially suitable as a selector transistor in a DRAM memory cell.

[0028] A memory cell has a selector transistor and a storage capacitor. According to FIG. 3, two source/drain regions 32 of the selector transistor are provided in a silicon substrate 31. A gate oxide 33 and a gate electrode 34 of the selector transistor are provided at a surface of the silicon substrate 31. One of the source/drain regions 32 is connected to a bit line. The other source/drain region 32 is connected over a conductive connection 36 with a first electrode 37 of the storage capacitor. In addition, the storage capacitor includes a memory dielectric 38 and a second electrode 39. The conductive connection 36 is completely surrounded by an intermediate oxide layer 40.

[0029] A contact hole is opened in the intermediate oxide layer 40 in order to make the conductive connection 36. The contact hole is filled through deposition of a doped silicon layer followed by planarization. The doped silicon layer is deposited in a CVD process using a process gas that contains SiH₄, Si₂H₆, PH₃and H₂. The gas flows which are used are:

[0030] The deposition temperature is 650° C. and the deposition pressure is 650 torr.

[0031] Deposition proceeds with a deposition rate of 52 nm per minute. After the deposition an activation heat treatment is carried out at 1100° C.

[0032] A conformity of 90 percent is achieved with these process parameters. As a result, the contact hole in the intermediate oxide layer 40 is filled out free of cavities.

[0033] The method for deposition of a doped silicon layer was described by using the example of an n-doping with phosphorus. The method according to the invention can also be performed for an n-doped silicon layer with arsenic as a dopant and for a p-doped silicon layer with boron as a dopant. In this case AsH₃and B₂H₆are used, respectively.