Oscillator with automatic gain control

[0002] The present invention pertains to the field of oscillators and clock generators. More particularly, the present invention relates to gain control of an oscillator.

[0003] An oscillator with an adjustable (“pullable”) output frequency is useful in many applications. In a conventional crystal-based oscillator, the output frequency is a function of the load capacitance seen by the crystal. To make the output frequency adjustable, therefore, the load capacitance can be made variable. A variable capacitance is often provided by a varicap, i.e., a diode which is designed to provide a wide range of junction capacitance within a narrow range of reverse voltages. The reverse voltage controls the frequency and is often generated by a digital-to-analog converter.

[0004] One problem with this technique is that the varicap is not available in digital processes. Consequently, the varicap and supporting circuitry are provided externally. To build this type of oscillator using only one varicap requires a type of circuit that is not easily integrated in a digital Complementary Metal-Oxide-Semiconductor (CMOS) process, because it requires floating capacitors (i.e., capacitors which have neither end coupled to Vcc or Vss).

[0005] Another problem associated with certain prior art oscillators is that they tend to waste power. To ensure proper start-up under all conditions, many prior art oscillators are designed to have excess gain, beyond what is needed to start and maintain oscillation in most situations. As a result, the oscillation amplitude increases until limited by non-linearities and usually exceeds the supply voltage. This level of drive wastes power, which can be particularly problematic in battery-powered applications. Further, this approach stresses the crystal. This approach also complicates integration of the required load capacitances in a digital CMOS process, due to the wide voltage swing across the capacitors. Consequently, external capacitors are normally provided.

[0006] The present invention includes an oscillator having an adjustable gain. The oscillator includes a first amplifier, a second amplifier, and an oscillation detector. The first amplifier can be coupled to a resonator to amplify oscillations of the resonator according to a gain. The oscillation detector is coupled to the first amplifier and outputs a detection signal in response to oscillations of the resonator. The second amplifier is coupled to receive the detection signal and to provide feedback to the first amplifier to control the gain based on a level of the detection signal. Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.

[0007] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

[0008] FIG. 1 illustrates an oscillator.

[0009] FIG. 2 illustrates an oscillator with digital frequency control.

[0010] FIG. 3 illustrates the shift-cap block 5 of FIG. 2 in greater detail.

[0011] FIG. 4 illustrates a switchable capacitor 8.

[0012] FIG. 5 illustrates the initial bit settings of the shift register 7 at RESET.

[0013] FIG. 6 illustrates the logic associated with three adjacent bits of the shift register 7.

[0014] FIG. 7 illustrates the clocker unit 6 of FIG. 2 in greater detail.

[0015] FIG. 8 illustrates one of the clocker segments 6L of FIG. 7 in greater detail.

[0016] FIG. 9 illustrates the inverting amplifier 2 of FIGS. 1 and 2.

[0017] FIG. 10 illustrates the oscillation circuit of FIGS. 1 and 2 with automatic gain control.

[0018] FIGS. 11 through 14 illustrate exemplary waveforms that occur at power-up of the oscillator when using gain control.

[0019] FIG. 15 illustrates an example of a PLL circuit in which an oscillator can be used.

[0020] FIG. 16 is a timing diagram showing signals associated with the PLL circuit of FIG. 15.

[0021] FIG. 17 shows an embodiment of a DCO, which includes four additional switchable capacitors outside the shift register, for use in a PLL.

[0022] FIG. 18 is a timing diagram showing signals associated with the embodiment of FIG. 17.

[0023] A technique for providing an oscillator with all-digital frequency control and automatic gain control is described. As is described in greater detail below, the oscillator includes a variable load capacitance coupled to a resonator, such as a quartz crystal. The variable capacitance is provided in the form of two banks of switchable capacitors, which are controlled by a shift register. The shift register is operable to control the switching states of the switchable capacitors, such that the logic state of each bit of the shift register determines the switching state of one corresponding switchable capacitor from each of the two banks. By clocking the bits of the shift register left or right, the load capacitance is varied, resulting in adjustment of the output frequency of the oscillator.

[0024] In addition, the oscillator can be provided with automatic gain control (i.e., self-adjusting gain) to achieve low power consumption. More specifically, an automatic gain control circuit provides abundant gain when the oscillator is first powered up but reduces the gain substantially below its startup value once oscillations build up, thereby substantially reducing the current drawn. In accordance with the present invention, the automatic gain control can (but is not required to) be combined with the digital frequency control, as will be apparent from the description which follows.

[0025] In one exemplary embodiment, an oscillation circuit is a pullable crystal oscillator. Throughout this description, numerous references are made to this “exemplary embodiment”, along with specific values for certain components and parameters associated with it. Note, however, that many, if not all, of these specific values may be changed for alternative embodiments of the present invention.

[0026] The oscillator of the exemplary embodiment operates at a frequency of 24.576 MHz ±100 ppm and draws approximately 0.6 mW of power in steady-state with approximately 8 pF load capacitance on the crystal. The frequency is determined mainly by the crystal but is pullable to approximately ±100 ppm using the arrangement of switchable capacitors. No external components are required except for the crystal, and the frequency is pulled by purely digital logic. Low power consumption is achieved by an automatic gain control circuit that detects oscillations and reduces the current from its startup value of approximately 1 mA to a level that just sustains oscillation, i.e., approximately 200 μA.

[0027] FIG. 1 illustrates a simple crystal oscillator without the frequency control of the present invention. The oscillator of FIG. 1 includes a resonator 1, an inverting amplifier 2, and a buffer 3 in a standard Pierce configuration. Specifically, the resonator 1 is connected between the input xi and the output xo of the inverting amplifier 2. The resonator may be a quartz crystal, for example, as is henceforth assumed in this description. Alternatively, the resonator may be a ceramic resonator, an LC circuit, or any other suitable type of resonator. Note that in an embodiment in which the crystal is replaced by an external clock, the output xo of the amplifier 2 does not need to be connected. The amplifier input xi is provided to the buffer 3. The output signal out of the buffer 3 is the output of the oscillator. The output may be used to drive a PLL. Signal ENABLE is applied to the amplifier 2 and can be used to enable or disable the oscillator.

[0028] FIG. 2 illustrates an oscillator identical to that illustrated in FIG. 1 but with the addition of digital frequency control of the present invention, i.e., the addition of frequency control circuit 4. Frequency control circuit 4 includes a shift register/variable capacitance (“shift-cap”) block 5 and a clocker unit 6. Frequency adjustability is provided by a variable capacitance in the shift-cap block 5. The variable capacitance is in the form of two banks of switchable capacitors. The shift-cap block 5 also contains a shift register, which controls the switching (on/off) states of the capacitors. Each left shift of the shift register decreases the total capacitance of each bank by one variable capacitor (one ΔC), and each right shift increases the total capacitance of each bank by one ΔC. The clocker unit 6 provides clock signals UP and DN to the shift register in response to external inputs XSHFT_CLK and XUP to clock the shift register. Signals UP and DN each consist of a pair of complementary, non-overlapping clock signals, as will be discussed below. If XUP is high, XSHFT_CLK is used to generate pulses of UP. If XUP is low, XSHFT_CLK is used to generate pulses of DN. If XSHFT_CLK is held at one level, no UP or DN pulses are generated. Pulses of the UP signals are used to increase the output frequency of the oscillator (the frequency of signal OUT), while pulses of the DN signals are used to decrease the output frequency of the oscillator. Signal RESET is used to set the initial logic state of the shift register.

[0029] In general, the normalized oscillation frequency can be defined as p=(ω−ω)/ω_m, where ω_mis the series resonant frequency of the crystal 1 and ω is the actual oscillation frequency of the entire oscillator. The value of ω(and, hence, the value of p) is controlled by circuit capacitance according to the formula p=C/(2Co+Cm). In the preceding formula, C is the capacitance associated with the motional arm of the crystal 1. The value of C is approximately 20 fF for the exemplary embodiment. Co is the crystal holder capacitance plus any other stray capacitance there may be between the xo and xi pins. The value of Co is estimated to be approximately 5 pF for the exemplary embodiment. Cx represents all capacitance from either xi or xo to AC ground.

[0030] Based on the above formulas, p varies from 770 ppm when Cx=16 pF to 480 ppm when Cx=32 pF. If the crystal has fm=24.576 MHz for the exemplary embodiment, then p=770 ppm corresponds to f=24.595 MHz, and p=480 ppm corresponds to f=24.588 MHz. The oscillation frequency, therefore, is controlled by varying Cx. Cx includes the variable capacitance in the shift-cap block 5, a 16 pF (in the exemplary embodiment) capacitor in the inverting amplifier 2, plus any stray capacitance.

[0031] The variable capacitance in the shift-cap block 5 is an array of small capacitors that can be switched on or off by the shift register, as shown in FIG. 3. FIG. 3 shows three adjacent bits of the shift register 7 and the switchable capacitors 8 associated with those bits. In the exemplary embodiment, the shift register 7 has 128 bits. The state of each bit determines the on/off state of two capacitors 8, one connected between xi and supply voltage Vcc and the other connected between xo and Vcc. If a bit has Q=1, the capacitors to which it is connected are off (switch open). If the bit has Q=0, the capacitors to which it is connected are on (switch closed). Each bit has a {overscore (Q)}_Linput coupled to the {overscore (Q)} output of the adjacent bit to the left and a Q_Rinput coupled to the Q output of the adjacent bit to the right.

[0032] Each bit also has and L input and an R input. The L input receives either signal LCLK or {overscore (LCLK)}, depending on the bit's position in the shift register 7, while the R input receives either signal RCLK or {overscore (RCLK)}, also depending on the bit's position in the shift register 7. Specifically, alternate bits receive either LCLK and RCLK or {overscore (LCLK)} and {overscore (RCLK)}, as shown in FIG. 3. LCLK, {overscore (LCLK)}, RCLK and {overscore (RCLK)} are generated by the clocker unit 6 of FIG. 1. In FIG. 1, LCLK and {overscore (LCLK)} together represent the UP signals in FIG. 2, because left shifts cause Cx to decrease and the output frequency to increase. RCLK and {overscore (RCLK)} together represent the DN signals in FIG. 2, because right shifts cause Cx to increase and the output frequency to decrease. Each bit further has direct set ({overscore (S)}_D) and reset ({overscore (R)}_D) inputs (not shown in FIG. 3), which are driven by the RESET signal.

[0033] FIG. 4 illustrates a schematic diagram of an exemplary one of the switchable capacitors 8. Each switchable capacitor 8 includes an n-channel Metal-Oxide Semiconductor Field-Effect Transistor (n-channel MOSFET, or NFET) swn with its source-to-drain path connected in parallel with that of a p-channel MOSFET (PFET) swp between signal xi or signal xo and the gate of a second PFET C1. The gate of transistor swn is coupled to the {overscore (Q)} output of the associated shift register bit, while the gate of transistor swp is connected to the Q output. The source, drain, and substrate of transistor C1 are all coupled to Vcc.

[0034] Upon assertion of the RESET signal, the shift register 7 is preset by the direct inputs to a state which sets the variable capacitance in the middle of its range. Specifically, as shown in FIG. 5, the left half of the shift register 7 is set to all logic 0s and the right half is set to all logic 1s. Thereafter, every change in the state of LCLK shifts the shift register 7 left by one bit, thereby decreasing Cx by one ΔC and increasing the output frequency, where ΔC is the value of the gate capacitance of transistor C1 in FIG. 4. Every change in the state of RCLK shifts the shift register 7 right by one bit, thus increasing Cx by one ΔC and decreasing the output frequency.

[0035] FIG. 6 shows the shift register logic for three adjacent bits. As shown, alternate bits are clocked by LCLK and {overscore (LCLK)}, and by RCLK and {overscore (RCLK)}, as noted above. LCLK and {overscore (LCLK)} are non-overlapping, as are RCLK and {overscore (RCLK)}. Also shown in FIG. 6 are the direct inputs {overscore (S)}_Dand {overscore (R)}_D, which are driven by the RESET signal shown in FIG. 2. Pulling {overscore (S)}_Dlow causes Q of that bit to go high, while pulling {overscore (R)}_Dlow causes Q to go low. Pulling either {overscore (R)}_Dor {overscore (S)}_Dhigh causes nothing to happen; the bit retain its value. Thus, for each of the leftmost half of the bits of the shift register 7, the {overscore (S)}_Dinput is tied to Vcc, and the {overscore (R)}_Dinput is tied to the inverted form of the RESET signal, which is an active high signal. For each of the rightmost half of the bits of the shift register 7, the {overscore (R)}_Dinput is tied to Vcc, and the {overscore (S)}_Dinput is tied to the inverted form of the RESET signal.

[0036] The operation of the shift register logic will now be described. First, assume all of the direct inputs to be at logic high, so that these inputs will have no effect on the circuit. Now consider just the middle bit, Q_n, of the three illustrated bits. The latch for the middle bit has {overscore (S)}_n={overscore (Q_n+L ·Q_n+1+L ·LCLK)} and {overscore (R)}_n={overscore (Q_n−1+L ·Q_n+L ·RCLK)}. If LCLK and RCLK are both low, then S_nand R_nare both deasserted ({overscore (S)}_nand {overscore (R)}_nare both high), and the latch just holds its value. Now suppose LCLK goes high, as when performing a left shift. If Q_n+1is 0, LCLK being high has no effect. LCLK being high also has no effect if Q_nis 1. LCLK has no effect unless Q_nis 0 and Q_n+1is 1. In that case, LCLK being high produces S_n=1, which changes Q_nto 1. In other words, the only bit which responds to LCLK going high is the bit whose current value is 0 and whose adjacent bit to the right is 1. In that event, the responding bit changes its current value to 1. In that case, LCLK can be left high if no further left shift is desired. No bit responds to LCLK being left high, because the only bit whose current value is 0 and whose neighboring bit to the right is 1 is Q_n−1, and its L input is {overscore (LCLK)}, which is low at this time. On the other hand, if another left shift is desired, LCLK is toggled from high to low. As a result, {overscore (LCLK)} goes high, and Q_n−1changes from 0 to 1. Q_n−2(not shown) does not change in that case, because Q_n−2is controlled by LCLK, which is 0.

[0037] The logic for a right shift is similar to that described above. The only bit which responds to RCLK going high is the bit whose current value is 1 and whose adjacent bit to the left is 0. In that event, the responding bit changes its current value to 0.

[0038] LCLK and RCLK are generated by the clocker unit 6 FIG. 2. The clocker unit 6 converts XSHFT_CLK into a pair of non-overlapping clock pulses, i.e., LCLK and {overscore (LCLK)} if XUP is high, and RCLK and {overscore (RCLK)} if XUP is low. If the UP signals are toggling, both DN signals are low. If the DN signals are toggling, both UP signals are low. Note that LCLK and {overscore (LCLK)} should never be high at the same time, so that a left shift does not propagate uncontrolled. Similarly, it is important that RCLK and {overscore (RCLK)} never be high at the same time. The outputs UP and DN of the clocker unit 6 are derived from, and have the same frequency as, its XSHFT_CLK input. To not shift the shift register 7 at all, XSHFT_CLK is simply stopped.

[0039] FIG. 7 illustrates the clocker unit 6 in greater detail. The clocker unit 6 includes a left segment 6L for generating signals LCLK and {overscore (LCLK)} and a right segment 6R for generating signals RCLK and {overscore (RCLK)}. Segments 6L and 6R each receive the input signal XSHFT_CLK as input. Segments 6L and 6R each have a disable input which, when asserted, prevents the segment from generating any output pulses. The disable input of the right segment 6R receives signal XUP, and the disable input of the left segment receives the inverted form of signal XUP, as illustrated, so that only one of the two segments 6L and 6R is enabled at a time.

[0040] FIG. 8 illustrates the left segment 6L in greater detail. The right segment 6R is identical to left segment 6L, except for the names of its output signals, and is therefore not illustrated at this level of detail. As shown, signal XSHFT_CLK is input to an inverter 10, the output of which is provided to a NOR gate 12 and to a second inverter 11. The NOR gate 12 also receives as input the signal applied to the disable input and the output signal LCLK. The output of the NOR gate 12 is applied to a delay line formed by a series of inverters 14, the final output of which forms signal LCLK. The output of the second inverter 11 is applied to a second NOR gate 13, which also receives as input the signal applied to the disable input and the output signal {overscore (LCLK)}. The output of NOR gate 13 is applied to a second delay line formed by a series of inverters 15, the final output of which forms signal {overscore (LCLK)}. Thus, if XSHFT_CLK is static, the enabled one of segments 6L and 6R has a 1 on one of its outputs and a 0 on the other output. If XSHFT_CLK is a rectangular waveform, the outputs LCLK and {overscore (LCLK)} are complementary, non-overlapping rectangular waveforms.

[0041] It will be recognized that there are numerous other ways of implementing the clocker unit 6 and other elements of the present invention. For example, the number of inverters 14 or 15 used to form the delay lines may easily be altered to suit the intended application.

[0042] FIG. 9 illustrates the inverting amplifier 2 of FIGS. 1 and 2, according to one embodiment. As shown, the amplifier 2 also includes no gain control. The amplifier 2 includes an NFET M1 and PFETs M2, MRF, MCXI, and MCXO. The source of transistor M1 is connected to supply voltage Vss, while the source of transistor M2 is connected to supply voltage Vcc. The drains of transistors M1 and M2 are connected to each other. The gate of transistor M1 is connected to the input xi of the amplifier 2, while the gate of transistor M2 is tied to Vss. Output xo is connected to the drains of transistors M1 and M2. The amplifier 2 of FIG. 2 is held in its active or transition region by the feedback resistor formed by transistor MRF. Transistor MRF is connected with one of its source/drain contacts connected to the input xi and the other source/drain contact connected to the output xo. The gate of transistor MRF is connected to Vss, and the substrate of MRF is connected to the output xo. Transistors MCXI and MCXO form capacitors that are part of the load capacitance for the crystal. Transistors MCXI and MCXO are connected with their sources, drains, and substrates all coupled to Vcc. The gate of transistor MCXI is coupled to the input xi, and the gate of transistor MCXO is coupled to the output xo.

[0043] FIG. 10 illustrates the oscillation circuit of FIG. 2 with the addition of an automatic gain control circuit 12 of the present invention. Note that the automatic gain control may be used in combination with the digital frequency control described above, although these two features can also be used separately. The automatic gain control circuit 12 of the present invention provides the oscillator with excess gain when the oscillator is first powered up, before oscillation begins. However, when the circuit begins to oscillate, the automatic gain control circuit 12 detects the oscillation build-up and decreases the gain to a level that supports peak-to-peak amplitude of, in the exemplary embodiment, approximately ⅓ the supply voltage.

[0044] As shown, the automatic gain control circuit 12 includes transistors M3 through M10. NFETs M3, M4, and M5 form an oscillation amplitude detector. NFET M6 is a common-gate amplifier which provides feedback to the basic inverting amplifier formed by M1 and M2. PFET M7 forms a load for M6, while PFET M10 and NFETs M8 and M9 provide biasing for M6.

[0045] Transistor M3 and M4 are source followers which use transistor M5 as a resistive load. In the exemplary embodiment, transistor M5 has a value of approximately 30 kΩ. Transistor M3 and M4 are connected with their source-to-drain paths in parallel between Vcc and a node n1. Specifically, the drains of transistors M3 and M4 are connected to each other and to Vcc. The sources of transistors M3 and M4 are connected to each other and to node n1. Transistor M5 has its drain connected to node n1 and its source connected to Vss. The gate of transistor M3 is coupled to the input xi, while the gate of transistor M4 is coupled to the output xo. The gate of transistor M5 is coupled to the ENABLE signal. Transistor M6 has its source connected to node n1 and its drain connected to node n3, which is the gate of transistor M2. The gate of transistor M6 is node n2. Transistor M7 has its source connected to Vcc, its drain connected to node n3, and its gate connected to Vss. Transistor M8 has its source connected to Vss and its drain connected to the source of transistor M9. Transistor M9 has its drain connected to node n2 and Vss. The gate of transistor M8 is connected to the ENABLE signal, while the gate of transistor M9 is connected to node n2. Transistor M10 has its source connected to Vcc, its drain connected to node n2, and its gate coupled to Vss.

[0046] When ENABLE is low, all current paths are turned off, such that the oscillator does not operate. When ENABLE is high, the oscillator can operate normally. When ENABLE is first asserted, in the absence of oscillation, the xo and xi pins are at approximately 1.1 VDC, and the sources of transistors M3 and M4 are at approximately 0.4 V, for the exemplary embodiment in which Vcc equals 3.3 V and Vss is ground (0 V). As oscillations build, transistor M4 conducts the positive half of its gate signal onto transistor M5, thus operating essentially as a half-wave rectifier. Transistor M3 does the same with its gate signal. Since the two gate signals are inverse of each other, the resultant waveform on transistor M5 appears, at least initially, as a full-wave rectified sinusoid with its base at approximately 0.4 V and its peaks growing with the oscillations. The increasing amplitude of this full-wave rectified signal results in a rising DC voltage at node n1.

[0047] As noted above, transistor M6 is a common-gate amplifier. The gain of transistor M6 is less than one at the oscillation frequency, and approximately +3 or +4 at 0 Hz in the exemplary embodiment. Transistor M6 amplifies the rising DC voltage at node n1 to produce a rising DC voltage at node n3. The rise in the DC voltage at node n3 decreases the drive on the gate of transistor M2, which reduces the current through the source-to-drain path of transistor M1. The reduction in the current available to transistor M1 lowers the gain of transistor M1, limiting the amplitude of the oscillations. In addition, when the circuit is oscillating, transistor MRF pumps a charge through its drain/substrate junction, which reduces the voltage at the input xi by approximately 0.5 VDC in the exemplary embodiment. This effect further reduces the drive level of transistor M1.

[0048] FIGS. 11 through 14 illustrate exemplary waveforms that occur at power-up of the oscillator when using gain control according to the present invention. Specifically, FIG. 11 illustrates the voltage at the input xi, and FIG. 12 illustrates the voltage at the output xo on linear scales. FIG. 13 illustrates the signals at nodes n1 and n3 (curves 18 and 19, respectively), while FIG. 14 illustrates a waveform representing the source current of transistor M2, both on linear scales. The shaded regions in these figures represent oscillations of the illustrated waveforms. Oscillations begin at approximately time t₁and reach their steady-state amplitude at approximately time t₂. When oscillations begin at time t₁, the voltage at both xi and xo is V₁, which is approximately 1.1 V in the exemplary embodiment. When oscillations begin, the DC voltage at node n1 begins to increase, as do its AC components. The voltage at node n1 is amplified by transistor M6; however, the amplification factor is less than one for the AC components and greater than one for the DC component. The DC voltage at node n3 then increases by approximately 1 V in the exemplary embodiment. In the exemplary embodiment, the approximately 1 V increase in voltage at node n3 reduces the source current in transistor M2 from approximately 1 mA (I₁) to approximately 200 μA. As a result, the oscillation build-up is self-limited at approximately 1 V peak-to-peak.

[0049] Note the effect of the charge pumping across the drain/substrate junction of MRF is to lower the DC voltage of xi from its initial value of 1.1 V to approximately 0.6 V in the exemplary embodiment. This effect contributes to the reduction in the source current of M2; however, most of the reduction in current is caused by M6.

[0050] An oscillator such as described herein be used in many types of applications, including applications which require virtually any type of clock signal. For example, such an oscillator may be used as a digitally controlled oscillator (DCO) in a phase-locked loop (PLL) circuit. FIG. 15 illustrates an example of such a circuit. The PLL circuit of FIG. 15 includes a conventional phase and frequency detector (PFD) 20, a clock logic block 21, and a DCO 22. The PFD 20 receives a reference frequency F_INas input and outputs signals UP′ and DN′ to the clock logic block 21. The clock logic block 21 also receives as input a clock signal CLOCK and outputs signals XSHFT_CLK and XUP (described above) to the DCO 22. The output of the DCO 22 is provided as an input to the PFD 20.

[0051] The operation of the PLL circuit is as follows, for one embodiment. Assertion of signal UP′ causes the DCO 22 to increase its oscillation frequency. More specifically, assertion of UP′ causes the internal logic of clock logic block 21 to generate signals XSHFT_CLK and XUP in such a manner as to increase the number N of logic ones in the shift register 7 of shift-cap block 5. Assertion of signal DN′ causes the DCO 22 to decrease its oscillation frequency. More specifically, assertion of DN′ causes logic in the clock logic block 21 to generate signals XSHFT_CLK and XUP in such a manner as to decrease the number N of logic ones in the shift register 7 of shift-cap block 5. If neither UP′ nor DN′ is asserted, DCO 22 maintains its current frequency. Note that PPD 20 includes appropriate logic to prevent simultaneous assertion of UP′ and DN′.

[0052] FIG. 16 is a timing diagram showing signals UP′ (a), CLOCK (b), XSHFT_CLK (c), XUP (d), and the number N of ones in the shift register (e), for one illustrative case. In the illustrated case, UP′ is asserted to cause the DCO 22 to increase its frequency. As shown, XUP is asserted at the same time UP′ is asserted and is deasserted at the same time UP′ is deasserted. The number N of ones in the shift register 7 reaches its maximum just before UP′ and XUP are deasserted. Following deassertion of UP′ and XUP, the number N of ones in the shift register decreases, causing the oscillation frequency of the DCO 22 to decrease. Note that waveform (e), which represents the number N of ones in the shift register, approximates an exponential rise in response to assertion of UP′ and XUP. This exponential approximation is accomplished, at least in part, by providing logic in clock logic block 21 to generate XSHFT_CLK at either of two different frequencies, as shown in FIG. 16.

[0053] In another embodiment of the PLL, the frequency of the DCO 22 is controlled by including four additional switchable capacitors in the DCO 22, as shown in FIG. 17. This embodiment does not require logic in the clock logic block 21 to provide XSHFT_CLK at two different frequencies. Two of the additional four capacitors are switchably connected to the input xi, while the other two are switchably connected to the output xo. Each of the four additional capacitors has a value several times larger than the switchable capacitors 8 of the switch-cap block 5. The four additional capacitors include two normally on (switch closed) capacitors 25 and two normally off (switch open) capacitors 26. One of each of capacitors 25 and 26 is connected to input xi and one of each of capacitors 25 and 26 to output xo. The switching state of the normally on capacitors 25 is controlled by signal UP′, while the switching state of the normally off capacitors 26 is controlled by signal DN′. More specifically, when UP′ from the PFD 20 is asserted, the normally on capacitors 25 are switched off. When UP′ is deasserted, the normally on capacitors 25 are switched back on. When DN′ from the PFD 20 is asserted, the normally off capacitors 26 are switched on. When DN′ is deasserted, the normally off capacitors 25 are switched back off.

[0054] FIG. 18 is a tiling diagram of signals UP′ (f), CLOCK (g), XSHFT_CLK (h), XUP (i), and the total capacitance C provided by the shift-cap block 5 (j), for the illustrative case in which UP′ is asserted and then deasserted. The capacitance C is illustrated in FIG. 18, rather than the number N of ones in the shift register, because in this embodiment, the capacitance is not determined solely by the value stored in the shift register, due to the addition of the four larger switched capacitors.

[0055] Thus, a technique for providing an oscillator with all-digital frequency control and automatic gain control has been described. Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.