Rate 32/33 (D=0, K=6) run length limited modulation code having optimized error propagation

[0002] The present invention relates to modulation codes, methods and modulation encoding/decoding apparatus. More particularly, the present invention relates to a high rate run length limited modulation code with a small maximum run length (e.g. k=6), with optimized error propagation properties and with a simple implementation within a magnetic recording system, such as a digital linear magnetic tape recording and playback system.

[0003] Modulation codes have been employed within magnetic recording channels in order to achieve a more even distribution of magnetic flux transitions within a data track in view of data patterns of particular user information being encoded and recorded. In particular, run length limited (RLL) modulation codes have been employed within partial response, maximum likelihood sampling detection (PRML) data recording and playback channels, decision feedback equalization (DFE) detection channels, and fixed delay tree search (FDTS) detection channels.

[0004] Canonical partial response targets of interest for magnetic data storage channels have included a (1−D) di-code target, a PR4 (1−D²) target, an EPR4 (1+D−D²−D³) target and an E²PR4 target, where D represents a unit delay operator. One drawback of a canonical target of form (1−D)(1+D)^Nis that it is only an approximate match to the magnetic channel but is relatively easily implemented; and it manifests a spectral null at the Nyquist sampling frequency. Other targets useful in magnetic recording channels include minimum mean square error (MMSE) type targets. A new class of fixed partial response targets is described in a pending patent application by Fisher et al, U.S. Ser. No. 09/034,933, filed on Mar. 4, 1998, entitled: “Disk Drive Using New Class of Fixed Partial Response Targets in a PRML Sampled Data Detection Channel”, the disclosure thereof being hereby incorporated by reference.

[0005] In PRML sampling data detection systems Viterbi detectors are conventionally employed to achieve “maximum likelihood” detection of user data being played back from a magnetic recording medium. For example, a Viterbi detector having an eight state trellis (nominal EPR4 target) generally employs an iterative method in determining a maximum likelihood path or route along the various branches of the detector trellis. “Maximum likelihood” generally means a particular path through the trellis creating a minimum mean square error.

[0006] A modulation code for a PRML data recording and playback channel is selected to impose certain desired signal playback conditions desired or needed to achieve robust and reliable data sampling and to limit the span of information corrupted by errors in the recording/playback process, at the expense of some additional overhead information added to the coded data stream. The amount of additional overhead information directly relates to the “rate” or efficiency of the modulation code. The less overhead information added by the modulation code, the higher the rate or efficiency of the code. As efficiency increases less recording space is consumed by overhead information needed by the modulation code.

[0007] The “rate” of a particular modulation code is defined as the ratio of unencoded bits to encoded bits in the coded output data stream. For example, a rate 2/3 code would have two user bits translated into three code bits, and would have an efficiency of only 0.667 i.e., considered to be a low rate. A rate 8/9 modulation code would have a higher efficiency of 0.889. The rate is said to increase as the efficiency approaches unity, and modulation codes having efficiencies in excess of 0.889 are called “high rate” codes.

[0008] A rate 16/17 (=0.941) modulation code achieves an approximate six percent (6%) increase in recording density over a standard rate 8/9 modulation code. The increased rate realized with a rate 16/17 modulation code means that each code bit recorded on the magnetic recording medium (disk or tape) contains approximately 6% more user data information than contained within a similar code bit in accordance with a rate 8/9 modulation code. One example of a rate 16/17 modulation code is provided in commonly assigned U.S. Pat. No. 5,635,933 to Fitzpatrick, et al., entitled: “Rate 16/17 (D=0, G=6/I=7) Modulation Code for a Magnetic Recording Channel”, the disclosure thereof being incorporated herein by reference. Another example of a rate 16/17 modulation code is provided by U.S. Pat. No. 5,757,822, by Fisher et al., entitled: Bit-Interleaved Rate 16/17 Modulation Code with Three-Way Byte-Interleaved EC”, the disclosure thereof being incorporated herein by reference.

[0009] An example of a rate 24/25 modulation code is provided by U.S. Pat. No. 5,737,294, by Fisher et al., entitled: “Rate 24/25 Modulation Code for PRML Recording Channels”, the disclosure thereof being incorporated herein by reference. An article by Wijngaarden and Immink entitled: “Combinatorial Construction of High Rate Runlength-limited Codes”, IEEE Proceedings of Globecom1996, pages 343-347, describes techniques for constructing high rate modulation codes. In the paper the authors described examples including a rate 16/17 (d=0,k=4) code and a rate 16/17 (d=0,k=6) code. One difficulty arising from the adoption of a very high rate modulation code is the considerable complexity usually required to realize practical hardware implementations of the encoding and decoding processes.

[0010] Added complexities are presented in the instance of multi-channel linear digital magnetic tape recording. Tape recording differs from rigid disk recording in that moving recording tape has relatively very low mass and is susceptible to substantial variation in instantaneous tape velocity. On the other hand, one or more rigid recording disks mounted to a rotating spindle manifest substantial angular momentum which impedes instantaneous change in angular velocity.

[0011] A number of circumstances have been found to contribute to tape velocity differentials. Eccentric spooling of the tape onto the supply or take up reel can result in repeatable velocity variations as the tape is fed from its eccentrically mounted spool or pancake. Defects in reels or other elements of the tape guide path can also contribute to tape differential velocity. Further, tape that has been spooled in e.g. a relatively dry or humidity-free environment and later stored for a time in a high humidity environment may experience constrained expansion from absorption of moisture, leading to unpredictable behavior causing sharp velocity differentials as the tape is fed from the spool.

[0012] One consequence of the variation in tape velocity is that the frequency of the recorded data becomes modulated by the velocity changes. In detecting the bits recorded on a tape, a phase locked loop is used to track any frequency variations, thus enabling reliable detection of bits recorded at very high recording densities as is commonly employed within PRML sampling data detection channels. To ensure that the phase locked loop works satisfactorily it is important to provide frequent phase error information. As considered at an input to a write preamplifier (output of precoder) a one corresponds to one polarity of write current, e.g. positive, and a zero corresponds to an opposite polarity of write current, e.g. negative. Whenever a one follows a zero, or a zero follows a one, a reversal of magnetization is written to the magnetic media, and a bell-shaped pulse approximately shaped like a Lorentzian function results in the sensed waveform during playback. In order to provide frequent timing and gain information needed during playback, long runs of no magnetic flux transitions, and long runs of consecutive magnetic flux transitions, are to be avoided. This objective is conventionally accomplished by run length limiting the bits at the input to a 1/(1+D²) precoder, where D is a unit delay operator.

[0013] In a modulation code for a PRML sampling magnetic tape recording channel, for example, it is desirable that a maximum run length constraint be sized in order to provide acceptable timing information to assure reasonably accurate sampling of the recorded waveform during playback. The maximum number of consecutive zero bits permitted by the modulation code is referred to as the “k” constraint, while the minimum number of zero bits between one bits permitted by the code is referred to as the “d” constraint.

[0014] Information written onto a track of a magnetic tape is first modulation encoded before recording. In the detection process the analog playback signal is converted into modulation coded bits using the Viterbi detector process described above (or a similar device such as a decision feedback equalizer or a fixed delay tree search detector). The coded bits are decoded into information bits by passing through a modulation decoder. When errors occur in the detection process they can be further propagated into more errors in passing through the modulation decoder. One desired characteristic of a modulation code is that it limit or restrict the propagation of errors as much as possible. Limiting error propagation to a small amount of the recorded information desirably aids subsequent block error correction processes which are typically applied at the drive system level.

[0015] Magnetic storage systems typically include block memories and embedded control microprocessors. Currently, block memory arrays and control microprocessors used to handle data transfers within data storage systems are based upon 32 or 64 bit width bus architecture. As a consequence, the memory array's and the microprocessor's basic unit of data (data word) is 32 (or 64) bits. It is therefore desirable to provide a high rate modulation code which is congruent with the bus width of the block memory array and the control microprocessor in order to limit the complexity of circuitry interfacing the recording channel to the block memory and to the control microprocessor.

[0016] Therefore, a hitherto unsolved need has remained for a very high rate modulation code for a magnetic recording channel which meets the foregoing requirements and solves the problems associated with the prior approaches.

[0017] A general object of the present invention is to provide a rate 32/33 (d=0, k=6) run length limited modulation code having optimized error propagation for use in a magnetic recording channel in a manner and form overcoming limitations and drawbacks of the prior art.

[0018] Another object of the present invention is to provide a practical rate 32/33 modulation code and implementation which achieves a very high code rate without sacrificing reliability of detected data in a manner overcoming limitations of prior approaches.

[0019] A further object of the present invention is to provide simplified, reliable encoding and decoding methods for encoding 32 bit data words into 33 bit code words in consonance with predetermined modulation coding constraints, including minimum zero run length, and maximum zero run length and in a manner effectively limiting error propagation.

[0020] In accordance with principles and aspects of the present invention a method is provided for generating a (d=0, k=6) rate 32/33 channel code for use in a partial response, sampling data detection channnel, such as a multi-channel linear digital magnetic tape recording/playback channel, to encode a series of user digital data bits. The method most preferably comprises the steps of:

[0021] forming a sequence of 32-bit user data words,

[0022] dividing each 32-bit user data word into eight four-bit data nibbles,

[0023] determining whether any of the data nibbles contain all zeros,

[0024] if no data nibbles are found to contain all zeros, then mapping the eight four-bit data nibbles to seven four-bit code nibbles and one five-bit code sub-word, and setting a first control bit of the code sub-word, comprising a fifth bit position thereof, to one, or

[0025] if a single data nibble is determined to contain all zeros as a code violation, then embedding location of the code violation within at least the five-bit code sub-word, and mapping a data nibble otherwise mapping to the five-bit code sub-word to a code nibble otherwise receiving the data nibble determined to have a code violation, or

[0026] if two data nibbles are determined to contain all zeros, then setting the first control bit to zero, setting a second control bit of the code sub-word to zero, and setting a third control bit within a second code sub-word to one, setting the remaining three bits of the first code sub-word to identify one of the two data nibbles containing all zeros within a first predetermined range of data nibbles, and setting the remaining three bits of the second code sub-word to identify the other of the two data nibbles containing all zeros within a second predetermined range of data nibbles, relocating a data nibble otherwise mapping to the first code sub-word to a code sub-word otherwise receiving the data nibble identified by the first code sub-word to contain all zeros, and relocating a data nibble otherwise mapping to the second code sub-word to a code sub-word otherwise receiving the data nibble identified by the second code sub-word to contain all zeros, or

[0027] if three or more data nibbles are determined to contain all zeros, then generating an eight-bit flag wherein each bit position of the flag identifies a data nibble determined to contain all zeros, and writing the eight bit flag into predetermined control bit positions defined in the first code sub-word, the second code-sub word, and a third code sub-word. This step may also include the step of writing a fourth code sub-word to all ones to provide maximum timing information for a timing loop of the magnetic recording channel.

[0028] A modulation encoder, and a modulation decoder, operating in consonance with the described modulation encoding method also form a part of the present invention.

[0029] These and other objects, advantages, aspects and features of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of a preferred embodiment, presented in conjunction with the accompanying drawings.

[0030] In the Drawings:

[0031] FIG. 1 is a block diagram of a magnetic data storage device, such as a multi-channel digital linear tape drive, employing partial response sampling data detection and a channel modulation code in accordance with aspects and features of the present invention.

[0032] FIG. 1A is a block diagram comprising a slight architectural variant of the magnetic data storage device shown in FIG. 1.

[0033] FIG. 2 is a table associating user bits to nibbles in accordance with principles of the present invention.

[0034] FIG. 3 is a table associating code bits to nibbles in accordance with principles of the present invention.

[0035] FIG. 4 is a table summarizing the four coding rules in accordance with the present invention.

[0036] FIG. 5 is a table summarizing probability that a 32 bit user word at the modulation encoder of FIG. 1 contains k violations.

[0037] FIG. 6 is a table of statistics of maxentropic (0,k) constrained sequences.

[0038] As noted above one purpose of a modulation code is to ensure that user information recorded on a magnetic storage medium, such as a tape moving linearly across a non-moving recording head structure, is optimized for the detection process. A relevant portion of a tape recording and playback system 10 is shown in FIG. 1. Therein, a multi-channel linear tape recording system 10 simultaneously writes and check reads a plurality of parallel magnetic recording tracks t formed on a relatively moving magnetic recording tape 12, such as one-half inch magnetic recording tape having desired magnetic remanence and coercivity properties enabling high density digital magnetic recording and playback. A multi-channel magnetic recording head structure 14 may follow one of a variety of useful implementations. In one exemplary arrangement the recording head structure 14 may include e.g. at least 24 magnetic write elements and 24 magnetic read elements are arranged alternately in two transverse rows such that twelve write elements are followed by twelve read elements during both forward and reverse travel of the tape across the head structure 14. In an alternative arrangement twelve write elements may be provided on one side of twelve centrally located read elements, and twelve write elements may be provided on the other side of the read elements such that twelve data tracks may be simultaneously written and write-checked during movement of the tape across the head structure 14 in both forward and reverse directions. In a further alternative arrangement, twelve read elements may be provided on one side of twelve centrally located write elements, and twelve read elements may be provided on the other side of the write elements such that twelve data tracks may be simultaneously written and read during forward and reverse tape travel. A bidirectional arrow in FIG. 1 denotes bidirectional travel of the tape 12, and the Δv symbol adjacent thereto denotes the presence of undesired differential tape velocity caused by one or a number of influences discussed hereinabove.

[0039] An internal system bus 50 interconnects an interface structure 52 and a block buffer memory 54. An embedded control microprocessor 56 controls various functions of the tape system 10 including tape transport and lateral head positioning functions (not further described herein). The microprocessor 56 also controls the flow of user information to and from the interface 52 and buffer memory 54. While a single microprocessor 56 is shown in FIG. 1, those skilled in the art will appreciate that the control functions of system 10 may be distributed among several embedded microprocessors or digital signal processors, etc. The bus 50 has a predetermined word size, such as 32 or 64 bits bus width. Presently, 32-bit width is preferred, and the interface 52, buffer memory 54 and microprocessor 56 are designed to match the bus bit width (e.g. 32-bit) thereby minimizing the complexity of any internal bus interface or “glue” logic.

[0040] A write portion of the system 10 includes a data scrambler 60 which receives e.g. 32-bit words from the bus 50 and scrambles the words in accordance with a predetermined conventional scrambling algorithm such as modulo two. In this manner repetitive or constant bit patterns frequently found to complete or fill user data blocks or repetitive command patterns will be avoided in the resultant bit stream leaving the scrambler. While it is theoretically possible for a user data pattern to be scrambled into a periodic sequence, the likelihood that such a pattern would extend for more than N bits is approximately 2^(−N).

[0041] A parallel data word output from the scrambler 60 leads through a modulation encoder 62. The modulation encoder 62 imposes a modulation code upon the scrambled data words coming in from the data scrambler 60. The modulation encoder 62 converts incoming 32-bit scrambled user data bit words into 33-bit code words in accordance with principles of the present invention. Implementation details of the modulation encoder 62 are given hereinafter. The 33-bit code words are then selectively directed to each one of 12 parallel write channel paths. Channel zero is shown at the block implementation level, and channel 11 is shown in block outline in FIG. 1. It should therefore be understood that channels 0-11 are substantially identical. A selector 63 directs each 33-bit code word from the modulation encoder 62 to one of the 12 write channels 0-11, in accordance with a predetermined data recording pattern for the tracks t. In this manner only one modulation encoder 62 need be implemented for all of the write channels 0-11.

[0042] Each write channel path includes e.g. a parallel-to-serial converter 64 which puts out each received 33-bit code word as a serial stream of 33 sequential bits c_n. This bit stream then passes through a suitable precoder 66. If the bit sequences {c_n} and {b_n} are respective input and output bit sequences of the precoder 66, then the Output of the precoder 66 at time n can be expressed as b_n=XOR(b_n−2, c_n). While the precoder 66 simplifies the design of modulation codes that are both DC and high frequency constrained, the precoder 66 has the negative impact of lengthening the longest recorded magnets on the tape to k+2 bits. The modulation coded and precoded serial bit stream b_nis then passed through a conventional write equalization and write precompensation process 68 and then amplified by a write driver 70 into a digital write current before being applied over a path 72-0 to one of the twelve write elements of the head structure 14. In the FIG. I example write head select circuitry has been omitted but would be included in a practical implementation having two write heads per track, the circuitry to select a particular write element for each recording direction.

[0043] As shown in FIG. 1 there are 12 identical read channels, each connected to a read element of the head structure 14. Read channel zero is shown in block level detail, and the other 11 channels are symbolized by the single dashed-line block labeled “Read Channel 11” in FIG. 1. In each read channel, a gain-controlled amplifier 80 and an analog equalizer 82 normalize the gain and response of the analog read back signal to the preferred PRML target, and an analog to digital converter 84 then samples the analog signal in accordance with the target. A timing loop 85 derives timing clock information from the samples and thereby controls the sampling of the analog to digital converter 84. A Viterbi detector 86 decodes the quantized samples into coded values x_n. Preferably, the Viterbi detector 86 implements an NPR target as one of the classes of PRML targets described in the referenced, pending U.S. patent application Ser. No. 09/034,933.

[0044] A postcoder 88 receives and postcode processes the coded values x_ninto values y_n. The output of postcoder 88 {y_n} can be written in terms of the postcoder input {x_n} as y_n=XOR(x_n, x_n−2). The postcoded samples y_nare then passed through a modulation decoder 90. The modulation decoder 90 applies an inverse function of the function applied by the modulation encoder and therefore is within the principles and aspects of the present invention. The decoded serial data stream is then passed through a conventional data descrambler 92 also operating as an inverse of the scrambling function applied by the data scrambler 60. A serial-to-parallel converter 94 accumulates the serial bit stream into 32-bit words and passes the words onto the data bus 50 e.g. for temporary storage in the buffer 54. A block error correction process may be applied to each block of the recovered user data information in order to detect and correct any error bursts. The block error correction process is conventional and is not a part of the present invention and is therefore not described in any detail.

[0045] FIG. 1A sets forth an alternative read channel architecture in which 12 identical read channels have outputs from postcoders 88 feeding directly into a multiplexer 89. The multiplexer 89 has a single output which feeds into a single modulation decoder 90. A single data descrambler 92 and serial-to-parallel converter 94 complete this alternative architecture. In this alternative embodiment only one modulation decoder need be implemented, with some savings of gates in VLSI read channel implementations. In yet another alternative embodiment, a single VLSI chip contains four read channels feeding into a single multiplexed modulation decoder. Further multiplexing circuitry enables three of these four-channel chips to form a 12 channel implementation.

[0046] It has been found particularly advantageous to match the word width of the modulation encoder 62 and the modulation decoder 90 to the word width of bus 50, microprocessor 56 and block buffer 54. In one design considered during a development leading to the present invention a rate 24/25 code was proposed for a 12 head multi-channel tape drive architecture. That approach, in which a single 24 bit encoder was used for 12 heads required approximately ten thousand gates more than were required in the encoder implementations of FIGS. 1 and 1A.

[0047] Unconstrained user data is received in user data words of 32 bits and is encoded into code words of 33 bits. With reference to the FIG. 2 table, each unencoded 32-bit data word is defined as U, and a corresponding 33-bit code word is defined as C. The 32 user bits are parsed into eight four-bit nibbles that are named u7, u6, u5, u4, u3, u2, u1, and u0. As shown in the FIG. 3 table, the user nibbles are encoded into coded nibbles c7, c6, c5, c4, c3, c2, c1, and c0. It is important to note in this example that the code sub-word c5 comprises five bits, while all of the other code nibbles comprise four bits each. In this example an additional, fifth bit position of code sub-word c5, e.g. a least-significant-bit c5[0], forms a control bit.

[0048] Each user nibble u7, u6, . . . u0 is said to have a code violation if it is equal to “0000”. An eight bit variable, FLAG, is created. The nth bit of FLAG is set equal to one if a nibble un is equal to all zeros. For example, if U=(u7 u6 u5 u4 u3 u2 u0)=(0000 1000 0110 0000 1111 0010 0000 0111), then FLAG=(10010010), meaning that code violations are present at user nibbles u7, u4 and u1.

[0049] Encoding of the 32-bit user data word is carried out in accordance with the following four rules, depending upon the number of violations found to be present in the word U presently to be encoded. The FIG. 3 table summarizes the four coding rules. The following cases illustrate each of the four rules.

[0050] Case 1: No violations in U (59% likelihood of occurrence (upon the assumption that ones and zeros are equally likely to occur at the input to the modulation encoder)). The FLAG variable is set equal to 00000000. The control bit of code sub-word c5, i.e. c5[0], is set equal to one and the remaining nibbles are passed unencoded. Thus, c7 equals u7, c6 equals u6, c5[5−1] equals u5, c4 equals u4, c3 equals u3, c2 equals u2, c1 equals u1 and c0 equals u0.

[0051] Case 2: One violation in U (31.8% likelihood of occurrence). The FLAG variable is set equal to one of {00000001, 00000010, 00000100, . . . 10000000 } depending upon the location of the nibble containing the code violation. The bits c5[0] and c5[2] are set to be equal to zero and one respectively. The remaining c5 bits are used to indicate in which of the eight locations the single violation occurred. For example, if FLAG indicates that the third low order nibble u2 contained the single code violation (FLAG=00000100), then c5[0]=0, c5[2]=1, and c5[4:3, 1]=010 to indicate that the third nibble u2 contains four zeros. Since the nibble c5 is used to indicate in this example that the nibble u2 is all zeros, the information in user nibble u5 is mapped into the third code nibble position c2. Encoding is completed as c7 equals u7, c6 equals u6, c5 equals [01110], c4 equals u4, c3 equals u3, c2 equals u5, c1 equals u1 and c0 equals u0.

[0052] Case 3: Two violations in U (7.4% likelihood of occurrence). The FLAG variable has two bit positions set, e.g. {00000011, 00000101, . . . 11000000}. The bits c5[0] and c5[2] are set to zero, and the bit c4[3] is set to one. The remaining c5 bit positions are used to indicate in which of the eight locations the left side violation occurred, and the bits c4[2:0] indicate the nibble position of the right side violation. For example, if violations occurred in nibbles u7 and u0, FLAG is equal to 10000001, and c5[0] equals zero, c5[2] equals zero, c4[3] equals 1, c5[4:3,1] equals 111 and c4[2:0] equals 000. Since the user nibble u7 is all zeros, the nibble c5 is used to indicate that nibble u7 is all zeros, and the information in nibble u5 is mapped into c7 (i.e. the 8th code nibble). Similarly, the information in user nibble u4 is mapped into cO (the first code nibble). The final encoding of this example is therefore c7 is equal to u5, c6 is equal to u6, c5 is equal to [01100], c4 is equal to [1000], c3 is equal to u3, c2 is equal to u2, c1 is equal to u1 and c0 is equal to u4. In this example, the mapping of u5 to c7, u4 to c0 and u3 to c3 is carried out in a manner to minimize gate count of the modulation encoder 62.

[0053] Case 4: Three or more violations in U (1.1% likelihood of occurrence). The control bits c5[0], c5[2] and c4[3] are all set equal to zero. The bits c5[4:3], c4[2:0] and c3[2:0] are set equal to the eight flag bits. Bits c5[1] and c3[3] are both filled with ones to ensure that the k constraint (k=6) is satisfied. As an example, four code violations are found to occur at nibbles u7, u6, u4, and u3 (FLAG=1011000). The encoded 33-bit word becomes c7 equal to u5, c6 equal to all ones, c5 equal to [11010], c4 equal to [0011], c3 equal to [1000], c2 equal to u2, c1 equal to u1 and c0 equal to u0. Note that c6 has been set to all ones to provide maximum timing information for the timing loop 85.

[0054] The decoding process carried out by modulation decoder 90 comprises the step of examining bits c5[0], c5[2] and c4[3] in order to determine the number of original nibbles that contained violations detected in the encoding process. For example, if c5[0] equals zero, c5[2] equals one and c4[3] equals zero, only a single nibble was in violation in the encoding process and that bits c5{4:3,1] identify the code nibble to be set to all zeros during decoding. Additionally, the nibble location indicated by c5[4:3,1] is mapped onto the u5 code nibble.

[0055] The logic of modulation encoder 62 and modulation decoder 90 was developed with the aid of Verilog and Synthesis circuit design tools. FIG. 5 sets forth a listing in Verilog of logic equations implementing the encoder 62, and FIG. 6 sets forth a listing in Verilog of logic equations implementing the decoder 90. As implemented the encoder 62 requires approximately 415 gates and the decoder 90 requires approximately 325 gates.

[0056] When the Viterbi detector 86 makes an incorrect decoding decision, bad information is passed into the postcoder 88. As already noted above, operation of the postcoder 88 lengthens the error event by two additional bits. Errors going into the modulation decoder 90 result in errors in the decoded user bit stream leaving the decoder 90. Generally speaking, more errors result at the output of the modulation decoder 90 than were present at its input. This multiplication of error sizes is referred to herein as error propagation. The presently preferred code described herein has limited error propagation.

[0057] The nature of error propagation for the (0,6) rate 32/33 code depends upon the probability that the erroneous bits include control bits c5[0], c5[2] or c4[3], and whether the control bits are being used in the decoding of the word of present interest. If the erroneous code bits do not impact code nibbles c3, c4 or c5, then the number of errors at the output of the decoder 90 does not multiply. However, if bit c5[0] is in error, it is very likely that most of the 32 decoded bits will be in error. The probability of bit c5[0] being in error is a function of the errors entering the decoder 90. The probability that a five bit error affects bit c5[0] is approximately 5/33. The table set forth as FIG. 5 shows the probability that bits at the input of the encoder 62 will contain 0, 1, 2, . . . or 8 violated nibbles. This probability indirectly relates to error propagation in the sense that the likelihood that corrupted bits effect the control bits depends upon which bits are control bits. The table of FIG. 5 shows the likelihood that the encoder 62 will have to encode with a case 1, case 2, case 3, or case 4 type violation. Because all of the control bits of the preferred embodiment are located toward the center of the coded word, errors that straddle word boundaries do not further propagate into longer bursts at the output of the decoder 90. However, in some cases the code nibble c7 is mapped as far away as user nibble u3. Therefore, it is possible for an error which straddles two 33-bit code words to result in two errors separated by two uncontaminated bytes.

[0058] To be certain that the k constraint of the presently preferred code is six, the four different categories of encoding discussed above and summarized in the FIG. 3 table must be considered. If each of the eight nibbles u0, u1, . . ., u7 contains at least a single one, and c5[0] is equal to one, then the maximum run of zeros arises when the nibble having a bit value of 1000 is immediately followed by a nibble having a value of 0001 In this example the k=6 constraint is satisfied. When a single violation is found in a user nibble, then c5[2] is set equal to one, and all other nibbles are ensured to contain at least a one; and, in this case the k=6 constraint is also satisfied.

[0059] When two violations are present in a user word of interest, then c5[2]=c5[0]=0, and c5[4:3,1] is used to indicate the position of the left most nibble in violation. Consequently, there are two situations to consider. In a first situation the left violation is in location 001, i.e. nibble u1. In this first situation c5=[00010] and the k=6 constraint is met. In the second situation the left most violation is in position 100, i.e. nibble u4, and c5=[10000], yet c4[3] is equal to one and the k=6 constraint is also met.

[0060] Finally, consider the situation where there are three or more code violations in the user word U of present interest at the input to encoder 62. In this situation c5[1] is equal to one, and c3[3] is equal to one, which ensures that even if c4 is all zeros, the k=6 constraint is not violated.

[0061] The statistical data presented in the table of FIG. 6 has been calculated in order better to understand the value of the k constraint on the timing loop 85 of the read channel. In FIG. 6 some statistical properties of (0,k) constrained sequences were calculated as a function of values of k from 3 through 10 and k equal to infinity (no maximum zero run length constraint). The calculations underlying the data of FIG. 6 do not specifically use the coding rules of the presently preferred code described herein, but rather rely on the statistical properties of generic (i.e. maxentropic) (0,k) constrained sequences, see T. D. Howell, “Statistical Properties of Selected Recording Codes”, IBM Journal of Research and Development,Vol. 33, No. 1, January 1989, pp. 60-73. The values of the second column of the FIG. 6 table indicate the likelihood that an arbitrarily selected bit is equal to one (as opposed to a zero). The values of the third column of the FIG. 6 table represent the probability that any given bit will provide timing information to the phase locked loop of the timing circuit 85. The FIG. 6 fourth column values indicates a bound on the code rate possible for each k constraint.

[0062] It is interesting to note that the k constraint does not significantly influence the statistical properties of the data (assuming equally likely ones and zeros at the input of encoder 62). If a larger k constraint were considered allowable, it is easy to extend the presently preferred rate 32/33 code to higher rates by padding unencoded bits between code nibbles c0, c1, . . ., c7. One specific case of value results from padding four unencoded bits between each coded nibble to make a (0,10) 64/65 code, which is particularly well suited if the bus structure 50 had a bit width of 64 bits (and so with memory 54 and/or microprocessor 56), for example. In this latter example the error propagation properties are nearly identical to the presently preferred (0,6) 32/33 code and rate.

[0063] Encoder Implementation: The following is a listing in the Verilog language of logic definitions and equations implementing a modulation encoder in accordance with coding rules of the present invention.

[0064] Decoder Implementation: The following is a listing in the Verilog language of logic definitions and equations implementing a modulation decoder for decoding code words formed in accordance with coding rules of the present invention.

[0065] Having thus described an embodiment of the invention, it will now be appreciated that the objects of the invention have been fully achieved, and it will be understood by those skilled in the art that many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the invention. The disclosure and the description herein are purely illustrative and are not intended to be in any sense limiting.