US 6,181,355 B2Grant

Graphics processing with transcendental function generator

Issue Date:2001-01-30

•18 Claims

•3 Drawing Sheets

Abstract

A graphics processor for processing vertices of a polygon includes an input for receiving an instruction for processing a given vertex, memory for storing a first lookup table and a second lookup table, and an interpolation engine that, responsive to receipt of the instruction from the input, selects one of the lookup tables, determines table output from the one of the lookup tables, and produces an output value based upon the table output and data relating to the given vertex. Each of the first and second lookup tables may correspond to a selected function and contains table output as a function of an input value. The input value corresponds to data relating to the given vertex.

Metadata

Assignee

3Dlabs Inc. Ltd.

Inventors

Vernon Brethour
Stacy Moore

Application Information

Application Number:US 09/354,083

Filing Date:1999-07-15

Priority Date:1998-07-17

Art Unit:7

Classifications

IPC:

G06F 1300

Field of Search:

345501345507345508345513345503345199358518358520358523

Patent Drawings (3 sheets)

Description

Priority

[0002] This application claims priority from U.S. provisional patent application serial number 60/093,185, filed Jul. 17, 1998, entitled “GRAPHICS PROCESSING WITH TRANSCENDENTAL FUNCTION GENERATOR” and bearing attorney docket number 1247/A01, the disclosure of which is incorporated herein, in its entirety, by reference.

Field of the Invention

[0003] The invention generally relates to computer systems and, more particularly, the invention relates to processing graphics request data for display on a computer display device.

Background of the Invention

[0004] Three dimensional graphics request data commonly is processed in a computer system as a plurality of polygons having vertices. Each of the vertices have associated attribute data (e.g., color, transparency, depth, etc . . . ) that is utilized to rasterize pixels on a computer display device.

[0005] Vertices commonly are subjected to a plurality of different types of geometry calculations prior to being rasterized. Common functions typically include addition and multiplication functions. Specialized geometry accelerators often are utilized to perform such functions. Additionally, some transcendental functions commonly are required in vertex processing. Such calculations, for example, may be to determine an inverse square root of a number, or 2 raised to a power. Many geometry accelerators include a lookup table for each transcendental or elementary used function. Each lookup table typically has accompanying interpolation hardware for enhancing the accuracy of the transcendental functions by interpolating the results of the lookup table.

Summary of the Invention

[0006] In accordance with one aspect of the invention, a graphics processor for processing vertices of a polygon includes an input for receiving an instruction for a processing step, memory for storing a first lookup table and a second lookup table, and an interpolation engine that, responsive to receipt of the instruction from the input, selects one of the lookup tables, determines table output from the one of the lookup tables, and produces an output value based upon the table output and data relating to the given vertex. In preferred embodiments, each of the first and second lookup tables corresponds to a selected function and contains table output as a function of an input value. The input value corresponds to data relating to the given vertex.

[0007] In other embodiments, the graphics processor also includes a multiplexer for enabling the interpolation engine to couple to either of the first and second lookup tables. The graphics processor also may have a plurality of additional lookup tables, where the interpolation engine is selectively coupled with any of the first, second or additional lookup tables.

[0008] In accordance with other aspects of the invention, an apparatus for processing computer graphics requests includes a graphics request input, and a processor coupled to the graphics request input. The processor is responsive to instructions and has an output. Among other things, the processor preferably includes a transcendental function generator with a plurality of lookup tables, and an interpolator engine selectably coupled to one of the plurality of lookup tables. Each table preferably corresponds to a particular transcendental function and contains interpolation coefficients.

[0009] In preferred embodiments, the apparatus includes a multiplexer for enabling the interpolator engine to selectively couple to any one of the plurality of lookup tables.

Brief Description of the Drawings

[0010] The foregoing and other objects and advantages of the invention will be appreciated more fully from the following further description thereof with reference to the accompanying drawings wherein:

[0011] FIG. 1 schematically shows a portion of an exemplary computer system on which preferred embodiments of the invention may be implemented.

[0012] FIG. 2 schematically shows a preferred graphics accelerator that may be utilized in accord with preferred embodiments of the invention.

[0013] FIG. 3 shows a preferred embodiment of a transcendental function generator within a geometry accelerator shown in FIG. 2.

[0014] FIG. 4 shows a preferred method utilized by the transcendental function generator shown in FIG. 3 for producing output data.

Description of Preferred Embodiments

[0015] FIG. 1 shows a portion of an exemplary computer system 100 on which preferred embodiments of the invention may be implemented. More particularly, the computer system 100 includes a host processor 104 (i.e., a central processing unit) for executing application level programs and system functions, volatile host memory 102 for short term data storage (i.e., random access memory), a graphics accelerator 106 for processing graphics request code in accord with preferred embodiments of the invention (see FIG. 4), and a bus coupling all of the prior noted elements of the system 100. The system 100 further includes a display device 108 for displaying the graphics request code processed by the accelerator 106. The graphics accelerator 106 preferably utilizes any well known graphics processing application program interface such as, for example, the OPENGL™ application program interface (available from Silicon Graphics, Inc. of Mountain View, Calif.) for processing three dimensional (“3D”) and two dimensional (“2D”) graphical request code. In preferred embodiments, the host processor 104 executes a graphical drawing application program such as, for example, the PLANT DESIGN SYSTEM™ drawing program, available from Intergraph Corporation of Huntsville, Ala.

[0016] FIG. 2 shows several elements of the graphics accelerator 106. In preferred embodiments, the graphics accelerator 106 includes a double buffered frame buffer 200 (i.e., having a back buffer and a front buffer) for storing the processed graphics request code in accord with the OPENGL™ interface. Among other things, the graphics accelerator 106 also preferably includes a geometry accelerator 202 for performing geometry operations that commonly are executed in graphics processing, a rasterizer 204 for rasterizing pixels on the display device 108, and a resolver 206 for storing data in the frame buffer 200 and transmitting data from the frame buffer 200 to the display device 108. As noted above, the graphics accelerator 106 preferably is adapted to process both 2D and 3D graphical data. For more information relating to preferred embodiments of the graphics accelerator 106, see, for example, copending patent application entitled “WIDE INSTRUCTION WORD GRAPHICS PROCESSOR”, filed on Jul. 15, 1999 and claiming priority from provisional patent application serial number 60/093,165, and copending U.S. patent application entitled “MULTI-PROCESSOR GRAPHICS ACCELERATOR”, filed on Jul. 15, 1999 and claiming priority from provisional U.S. patent application serial number 60/093,247, the disclosures of which are incorporated herein, in there entireties, by reference.

[0017] FIG. 3 shows a preferred embodiment of a transcendental function generator (“function generator 300”) within the geometry accelerator 202 shown in FIG. 2. As is known to one skilled in the art, a transcendental function may be represented by the combination of elementary functions, such as addition and multiplication, in conjunction with coefficients values specific to the transcendental function. The function generator 300 includes first, second, and third lookup tables 302A, 302B, and 302C for producing output coefficient values based upon an input variable, an interpolation engine 304 for calculating an output value based upon the output coefficient values in selected ones of the lookup tables 302A-302C, and a multiplexer 306 for enabling the interpolation engine 304 to selectively couple with any one of the three lookup tables 302A-302C. The input variable preferably is a vertex data value such as, for example, an input lighting datum. The lookup tables are used to represent the output coeffiecents of the transcendental function. The interpolation engine includes hardware to perform elementary functions on the input variable and the output coefficients to form the output value. The geometry accelerator may use the transcendental function generator to perform lighting calculations, geometry transformations or clipping on the vetex data prior to the rasterization stage.

[0018] In preferred embodiments, each lookup table 302A-302C is directed to a different function. For example, the following lookup tables 302A-302C may be used to determine the following functions:

[0019] first lookup table 302A: 1/T^½ (i.e., the inverse square root of the variable T);

[0020] second lookup table: 302B: 2^T(i.e., 2 raised to the power of the variable T); and

[0021] third lookup table 302C: log₂T (i.e., the log base 2 of the variable T).

[0022] It should be noted that although three functions are provided, other functions adaptable to graphics processing may be utilized in the lookup tables 302A-302C. In some embodiments, the lookup tables 302A-302C are stored in read only memory (“ROM”) on the graphics accelerator. In a preferred embodiment, the lookup tables 302A-302C are stored in memory created gates. The term “lookup table” is utilized herein to describe any data structure for enabling data to be retrieved based upon input data. Accordingly, input data having a value of “1” should produce output coefficients that yield the value of “2” from the interpolation engine 304 when utilized in the second lookup table 302B. Each of the values calculated in the lookup tables 302A-302C preferably were calculated for a relatively small range of the input variable, thus controlling the size of the tables 302A-302C. In preferred embodiments of the invention, each table 302A-302C has sixty-four entries that each produce three output table values.

[0023] As discussed in greater detail below, the interpolation engine 304 receives processing instructions from another portion of the geometry accelerator, and responsively selects the appropriate lookup table 302A-302C via a select input of the multiplexer 306. Upon receipt of the output table data, the interpolation engine 304 calculates an output value by means of the output table value and the input data. In preferred embodiments, the interpolation engine 304 calculates an output value in accordance with the below quadratic formula:

[0024] Y=AX²+BX +C (Equation 1)

[0025] where A, B, and C are coefficients produced by either one of the tables 302A-302C; and X is an input variable that is based upon data relating to the vertex being processed.

[0026] In alternative embodiments, the formula implemented by the interpolation engine 304 is a linear equation. In still other embodiments of the invention, the interpolation formula implemented is a cubic formula. Other embodiments include other formulas.

[0027] FIG. 4 shows a preferred method utilized by the transcendental function generator 300 shown in FIG. 3 for producing output data. The process begins at step 400 in which an instruction is received by the interpolation engine 304 relating to a given vertex currently being processed. In preferred embodiments, the instruction is five bits of a wide word having at least 128 bits. Specifically, two bits are used to select the appropriate table, and three additional bits select the input argument from one of eight possible sources, ranging from the processor to a crossbar (not shown) or other bus. Among other things, the vertex may have some lighting data that is processed by the geometry accelerator at step 400.

[0028] The instruction preferably includes at least two lookup table bits that, when read by the interpolation engine 304, direct it to select one of the three lookup tables 302A-302C. For example, the bit sequence “00” may direct the engine 304 to the first table 302A, the bit sequence “01” may direct the engine 304 to the second table 302B, and the bit sequence “10” may direct the engine 304 to the third table 302C. Accordingly, the process continues to step 402 in which the interpolation engine 304 reads the two lookup table bits to determine which lookup table 302A-302C to access.

[0029] The process continues to step 404 in which the coefficients “A”, “B”, and “C” are ascertained from the selected lookup table 302A-302C. Three entries preferably are associated with the input variable entry in each lookup table 302A-302C. Accordingly, in preferred embodiments, the input variable is entered into all of the tables 302A-302C to produce respective sets of output variables “A”, “B”, and “C.” The input variable is associated with the vertex data being processed. The interpolation engine 304 then selects the appropriate lookup table 302A-302C via the select input of the multiplexer 306, and then retrieves the set of coefficients from the output of such selected lookup table 302A-302C.

[0030] The process then continues to step 406 in which both the input variable and retrieved coefficients are utilized in equation 1 (above) by the interpolation engine 304 to calculate an output value.

[0031] In some embodiments, the individual tables 302A-302C may be implemented as different address ranges in a common addressable storage device. This effectively eliminates the need for the multiplexer 306 described above. In such case, the bits from the instruction word that select the table are simply incorporated into the table address. In some embodiments that do not utilize the multiplexer 306, the table access time undesirably may be slower.

[0032] Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the true scope of the invention. These and other obvious modifications are intended to be covered by the appended claims.

Claims

We claim:

1. A graphics processor for processing vertices of a polygon, the graphics processor comprising:

an input for receiving an instruction for processing a given vertex;

memory for storing a first lookup table and a second lookup table, each of the first and second lookup tables corresponding to a selected function and containing table output as a function of an input value, the input value corresponding to data relating to the given vertex; and

an interpolation engine, responsive to receipt of the instruction from the input, selects one of the lookup tables, determines table output from the one of the lookup tables, and produces an output value based upon the table output and data relating to the given vertex.

2. The graphics processor as defined by claim 1 further including a multiplexer for enabling the interpolation engine to couple to either of the first and second lookup tables.

3. The graphics processor as defined by claim 1 further comprising a plurality of additional lookup tables, the interpolation engine being selectively coupled with any of the first, second or additional lookup tables.

4. The graphics processor as defined by claim 1 wherein the instruction is a wide word.

5. The graphics processor as defined by claim 4 wherein the wide word has at least 128 bits.

6. The graphics processor as defined by claim 5 wherein the wide word has 256 bits.

7. An apparatus for processing computer graphics requests, the apparatus comprising:

a graphics request input;

a processor, coupled to the graphics request input, having an output, and responsive to instructions, the processor including a transcendental function generator, the generator having:

a plurality of lookup tables, each table corresponding to a particular transcendental function and containing interpolation coefficients;

an interpolator engine, selectably coupled to one of the plurality of lookup tables.

8. The apparatus as defined by claim 7 further including a multiplexer for enabling the interpolator engine to selectively couple to any one of the plurality of lookup tables.

9. The apparatus as defined by claim 7 wherein each instruction is a wide word.

10. The apparatus as defined by claim 9 wherein each instruction includes up to 256 bits.

11. A graphics processor for processing vertices of a polygon, the graphics processor comprising:

an input for receiving an instruction for processing a given vertex;

memory for storing a plurality of lookup tables that each correspond to a selected function;

an interpolation engine that produces an output value based upon the contents of at least one of the lookup tables and data relating to the given vertex, the different tables being stored in different address ranges of the memory, the instruction having bits that are incorporated into the memory address to enable table selection.

12. A method for processing vertices of a polygon, the method comprising:

receiving an instruction for processing a given vertex with a function;

selectively connecting to a corresponding lookup table containing coefficient values for the function from a group of lookup tables;

selecting coefficient values from the corresponding lookup table based on data representative of the given vertex; and

calculating an output in an interpolation engine based on data representative of the given vertex and the coefficient values.

13. The method according to claim 12, wherein the instruction is a wide word.

14. The method according to claim 13, wherein the wide word is at least 128 bits.

15. A method for using a graphics processor to process vertices, the method comprising:

receiving data corresponding to a given vertex into an interpolation engine of a graphics processor;

receiving an instruction corresponding to the given vertex into an interpolation engine of a graphics processor;

accessing at least a first lookup table from a group of lookup tables based on at least part of the instruction;

ascertaining at least a first coefficient value from the first lookup table based on data corresponding to the given vertex; and

calculating an output value in the interpolation engine based on the data and the first coefficient value.

16. The method according to claim 15, wherein the step of accessing requires connecting the first lookup table with the interpolation engine based on part of the instruction.

17. The method according to claim 16, wherein the step of accessing results from setting a select input of a multiplexer which connects the interpolation engine to the first lookup table from the group of lookup tables.

18. A method for processing computer graphics requests, the method comprising:

receiving instructions at a graphics request input that is coupled to a transcendental function generator;

selectively accessing, based on one of the instructions, at least one of a group of lookup tables corresponding to a particular transcendental function, each lookup table containing interpolation coefficients;

retrieving interpolation coefficients based on vertex data; and

calculating a transcendental function based on the vertex data and the interpolation coefficients.

Patent Citations (64)

Patent	Date	Inventor	Cited By
US4434437	1984-02-01	Strolle et al.	Applicant
US4615013	1986-09-01	Yan et al.	Applicant
US4646232	1987-02-01	Chang et al.	Applicant
US4908780	1990-03-01	Priem et al.	Applicant
US4918626	1990-04-01	Watkins et al.	Applicant
US4991122	1991-02-01	Sanders	Applicant
US5107415	1992-04-01	Sato et al.	Applicant
US5123085	1992-06-01	Wells et al.	Applicant
US5224064	1993-06-01	Henry et al.	Examiner
US5239654	1993-08-01	Ing-Simmons et al.	Applicant
US5287438	1994-02-01	Kelleher	Applicant
US5293480	1994-03-01	Miller et al.	Applicant
US5313551	1994-05-01	Labrousse et al.	Applicant
US5363475	1994-11-01	Baker et al.	Applicant
US5371840	1994-12-01	Fischer et al.	Applicant
US5394524	1995-02-01	DiNicola et al.	Applicant
US5398328	1995-03-01	Weber et al.	Applicant
US5412491	1995-05-01	Bachar	Examiner
US5446479	1995-08-01	Thompson et al.	Applicant
US5485559	1996-01-01	Sakaibara et al.	Applicant
US5511165	1996-04-01	Brady et al.	Applicant
US5519823	1996-05-01	Barkans	Applicant
US5544294	1996-08-01	Cho et al.	Applicant
US5555359	1996-09-01	Choi et al.	Applicant
US5557734	1996-09-01	Wilson	Applicant
US5561749	1996-10-01	Schroeder	Applicant
US5572713	1996-11-01	Weber et al.	Applicant
US5631693	1997-05-01	Wunderlich et al.	Applicant
US5664114	1997-09-01	Krech, Jr. et al.	Applicant
US5666520	1997-09-01	Fujita et al.	Applicant
US5684939	1997-11-01	Foran et al.	Applicant
US5701365	1997-12-01	Harrington et al.	Applicant
US5706481	1998-01-01	Hannah et al.	Applicant
US5721812	1998-02-01	Mochizuki	Applicant
US5737455	1998-04-01	Harrington et al.	Applicant
US5757375	1998-05-01	Kawase	Applicant
US5757385	1998-05-01	Narayanaswami et al.	Applicant
US5764237	1998-06-01	Kaneko	Applicant
US5821950	1998-10-01	Rentschler et al.	Applicant
US5841444	1998-11-01	Mun et al.	Applicant
US5870567	1999-02-01	Hausauer et al.	Applicant
US5883641	1999-03-01	Krech, Jr. et al.	Applicant
US5914711	1999-06-01	Mangerson et al.	Applicant
US5956047	1999-09-01	Krech, Jr. et al.	Examiner
EP311798A2	1989-04-01		Applicant
EP397180A2	1990-11-01		Applicant
EP438194A2	1991-07-01		Applicant
EP448286A2	1991-09-01		Applicant
EP463700A2	1992-01-01		Applicant
EP566229A2	1993-10-01		Applicant
EP631252A2	1994-12-01		Applicant
EP627682A1	1994-12-01		Applicant
EP637813	1995-02-01		Examiner
EP693737A2	1996-01-01		Applicant
EP734008A1	1996-09-01		Applicant
EP735463A2	1996-10-01		Applicant
EP810553A2	1997-12-01		Applicant
EP817009A2	1998-01-01		Applicant
EP825550A2	1998-02-01		Applicant
EP840279A2	1998-05-01		Applicant
WO86/07646	1986-12-01		Applicant
WO92/00570	1992-01-01		Applicant
WO93/06553	1993-04-01		Applicant
WO97/21192	1997-06-01		Applicant

Non-Patent Literature (15)

Iwashita, et al., “A Fine Grained Data Flow Machine and Its Concurrent Execution Mechanism” NEC Reg. & Develop., No. 93, Apr. 1989, pp. 63-72.Applicant
Fujita, et al., “A Dataflow Image Processing System TIP-4”, Proceedings of the 5th International Conference on Image Analysis and Processing, pp. 735-741.Applicant
Rathman, et al., “Processing the New World of Interactive Media”, IEEE Signal Processing Magazine 1053-5888/98/510.00 Copyright Mar. 1998, vol. 15, No. 2, XP-002121705, pp. 108-117.Applicant
IBM Technical Disclosure Bulletin “Effective Cache Mechanism for Texture Mapping” vol. 39, No. 12, Dec. 1996, XP-002065152, pp. 213, 215 and 217.Applicant
“Advanced Raster Graphics Architecture” XP-002118066, pp. 890-893.Applicant
IBM Technical Disclosure Bulletin “Data Format Conversion: Intel/Non-Intel”, vol. 33, No. 1A, Jun. 1990, XP-000117784, pp. 420-427.Applicant
IBM Technical Disclosure Bulletin “Address Munging Support in a Memory Controller/PCI Host Bridge for the PowerPC 603 CPU Operating in 32-Bit Data Mode” vol. 38, No. 09, Sep. 1995, XP-000540250, pp. 237-240.Applicant
Auel, K., “One frame ahead: frame buffer management for animation and real-time graphics”, Presented at Computer Graphics: Online Publications, Pinner, Middlesex, UK, 1988, XP-000749898, pp. 43-50.Applicant
Abram, et al., “Efficient Alias-free Rendering using Bit-masks and Look-up Tables”, San Francisco, Jul. 22-26, vol. 19, No. 13, 1985, XP-002115680, pp. 53-59.Applicant
Schilling, A., “A New and Efficient Antialiasing with Subpixel Masks” XP-000562430, pp. 133-141.Applicant
Ueda, H., et al., “A Multiprocessor System Utilizing Enhanced DSP's For Image Processing”, Central Research Laboratory, Hitachi, Ltd., 1988 IEEE, XP-2028756, pp. 611-620.Applicant
Cook, R.L., et al., “The Reyes Image Rendering Architecture”, Computer Graphics, vol. 21, No. 4, Jul. 1987, XP-000561437, pp. 95-102.Applicant
Haeberli, P., et al., “The Accumulation Buffer: Hardware Support for High-Quality Rendering”, Computer Graphics, vol. 24, No. 4, Aug. 1990, XP-000604382, pp. 309-318.Applicant
Watt, A., et al., “Advanced Animation and Rendering Techniques Theory and Practice”, ACM Press, NY, pp. 127-137.Applicant
Carpenter, L., “The A-buffer, an Antialiased Hidden Surface Method”, Computer Graphics, vol. 18, No. 3, Jul. 1984, pp. 13-18.Applicant

Abstract