Method for performing a high-temperature burn-in test on integrated circuits

[0002] 1. Technical Field

[0003] The present invention relates to testing integrated circuits in general, and in particular to a method for performing reliability tests on integrated circuits. Still more particularly, the present invention relates to a method for performing a high-temperature burn-in test on integrated circuits.

[0004] 2. Description of the Prior Art

[0005] A metal oxide semiconductor field effect transistor (MOSFET) or MOS transistor has two regions in a silicon substrate, namely, a source and a drain, which are disposed at a certain distance from each other. The MOS transistor also has an insulated gate disposed between the source and the drain. The gate is characterized by a threshold voltage (V_TH) that determines the boundary between an ON state and an OFF state in the drain current.

[0006] It is well-known in the art that the threshold voltage of a MOS transistor changes as a function of temperature due to the availability of mobile electrons and other factors. Specifically, the threshold voltage decreases as temperature increases. This creates a problem for most integrated circuit (IC) designs because some qualification tests, such as a burn-in test, are required to be performed at high temperatures. Because the threshold voltages of the transistors are generally lower at high temperatures, the leakage currents and on-state drain currents of the transistors become significantly higher under burn-in conditions. In the prior art, this problem is solved by biasing the body of the transistors with additional contacts to the body of the transistors. This solution results in a much larger circuit and a reduction in the overall performance of the IC. Consequently, it is desirable to provide a method to maintain the threshold voltage of transistors within an integrated circuit during a high-temperature burn-in test without compromising the integrity of the test.

[0007] In accordance with a preferred embodiment of the present invention, a thin-film is placed on top of an integrated circuit having multiple transistors. An infra-red filter is then placed on top of the thin-film. All the transistors of the integrated circuit are radiated by an infra-red source through the thin-film and the infra-red filter when a high-temperature burn-in test is being performed.

[0008] All objects, features, and advantages of the present invention will become apparent in the following detailed written description.

[0009] The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

[0010] FIG. 1ais an energy band diagram of the p-doped material of an n-channel transistor, in accordance with a preferred embodiment of the present invention;

[0011] FIG. 1bis an energy band diagram of the n-doped material of a p-channel transistor, in accordance with a preferred embodiment of the present invention; and

[0012] FIG. 2 is a chart of elements that are good candidates for use as partially ionized dopants according to the present invention;

[0013] FIG. 3 is a pictorial diagram of a physical arrangement for performing a high-temperature burn-in test on ICs, in accordance with a preferred embodiment of the present invention; and

[0014] FIG. 4 is a pictorial diagram of a physical arrangement for performing a high-temperature burn-in test on ICs, in accordance with an alternative embodiment of the present invention.

[0015] In order to maintain the threshold voltage of transistors within an integrated circuit (IC) during a high-temperature burn-in test, a two-step solution is provided by the present invention. First, a partially ionized dopant is introduced to the transistors such that the transistors become double doped. As a result, the threshold voltage of the transistors will not decrease significantly at high temperatures. Second, the IC is exposed to an infra-red (IR) radiation during the burn-in test in order to photoionize the partially ionized dopant that has not yet fully ionized at that point. As a result, the threshold voltage of the transistors remains high during the high-temperature burn-in test because the extra dopants within the body and channels of the transistors are ionized.

[0016] A. Double Doped Transistors

[0017] Referring now to the drawings and in particular to FIG. 1a, there is illustrated an energy band diagram of the double p-doped material of an n-channel transistor, in accordance with a preferred embodiment of the present invention. As shown, E_vrepresents the energy level of the valence band, E_crepresents the energy level of the conduction band, E_Frepresents the Fermi energy level, E_A1represents the energy level of a first acceptor, and E_A2represents the energy level of a second acceptor. At room temperature, the energy level of the first acceptor is closer to the valence band, and the energy level of the second acceptor is closer to the conduction band.

[0018] In a preferred embodiment, the first acceptor (or first dopant) and the second acceptor (or second dopant) for the double p-doped n-channel transistor are Boron and Platinum, respectively. Boron has an ionization energy of 0.045 eV above the valence band E_v, and Platinum has an ionization energy of 0.25 eV below the conduction band E_c. Boron and Platinum are merely illustrative and many other elements, such as Magnesium or Cadmium, could also be utilized without departing from the scope of the present invention.

[0019] The desired ionized impurity concentration for the double p-doped n-channel transistor can be estimated by: $N_{\mathrm{A1}}^{*}=\frac{N_{\mathrm{A1}}}{1+4\exp \left(\frac{E_{\mathrm{A1}}-E_F}{\mathrm{kT}}\right)}$ $N_{\mathrm{A2}}^{*}=\frac{N_{\mathrm{A2}}}{1+4\exp \left(\frac{E_{\mathrm{A2}}-E_F}{\mathrm{kT}}\right)}$

[0020] where N_A1is the impurity concentration of the fully ionized first acceptor and N_A2is the impurity concentration of the partially ionized second acceptor. At low temperatures, such as room temperature, the ionized impurity concentration is close to the impurity concentration of the partially ionized second acceptor (i.e., N_A*≈N_A1). At higher temperatures, such as 140° C., the total ionized impurity concentration for the double p-doped n-channel transistor is the sum of the impurity concentration of the fully ionized first acceptor and the impurity concentration of the partially ionized second acceptor (i.e., N_A*=N_A1+N_A2).

[0021] The equation for threshold voltage of the double p-doped n-channel transistor at high temperatures is given by: $V_{{\mathrm{TH}}_N}=V_{\mathrm{FB}}+2{\psi }_{\mathrm{BN}}+\frac{2\sqrt{e{\epsilon }_s\left(N_{\mathrm{A1}}^{*}+N_{\mathrm{A2}}^{*}\right){\psi }_{\mathrm{BN}}}}{C_i}$

[0022] where V_FBis the flat-band voltage, ψ_BNis the band-bending at the surface of the n-channel transistor, e is the electronic charge, ε_sis the dielectric constant of silicon, N_A1* is the doping concentration of a first acceptor, N_A2* is the estimated doping concentration of a second acceptor, and C_iis the gate oxide capacitance per unit area.

[0023] The change in threshold voltage in the double p-doped n-channel transistor can be described by: $\Delta V_{{\mathrm{TH}}_N}\approx \frac{2\sqrt{e{\epsilon }_s{\psi }_{\mathrm{BN}}}}{C_i}\left(\sqrt{N_{\mathrm{A1}}^{*}+N_{\mathrm{A2}}^{*}}-\sqrt{N_{\mathrm{A1}}^{*}}\right)$

[0024] Referring now to FIG. 1b, there is illustrated an energy band diagram of a double n-doped material of a p-channel transistor, in accordance with a preferred embodiment of the present invention. As shown, E_vrepresents the energy level of the valence band, E_crepresents the energy level of the conduction band, E_Frepresents the Fermi energy level, E_D1represents the energy level of a first donor, and E_D2represents the energy level of a second donor-the partially ionized dopant. Thus, at room temperature, the energy level of the first donor is closer to the conduction band, and the energy level of the second donor is closer to the valence band.

[0025] In a preferred embodiment, the first donor (or first dopant) and the second donor (or second dopant) for the double n-doped p-channel transistor are Phosphorous and Carbon, respectively. But Phosphorous and Carbon are also merely illustrative and many other elements, such as Platinum or Gold, could also be utilized without departing from the scope of the present invention.

[0026] The desired ionized impurity concentration for the double n-doped p-channel transistor can be estimated by: $N_{\mathrm{D1}}^{*}=\frac{N_{\mathrm{D1}}}{1+2\exp \left(\frac{E_F-E_{\mathrm{D1}}}{\mathrm{kT}}\right)}$ $N_{\mathrm{D2}}^{*}=\frac{N_{\mathrm{D2}}}{1+2\exp \left(\frac{E_F-E_{\mathrm{D2}}}{\mathrm{kT}}\right)}$

[0027] where N_D1is the impurity concentration of the fully ionized donor dopants and N_D2is the impurity concentration of the partially ionized donor dopants. At low temperatures, such as room temperature, the impurity concentration of the fully ionized donor dopants is about the same as the impurity concentration of the partially ionized donor dopants (i.e., N_D*≈N_D1). However, at higher temperatures, such as 140° C., the total ionized impurity concentration for the double n-doped p-channel transistor is the sum of the impurity concentration of the fully ionized donor dopants and the impurity concentration of the partially ionized donor dopants (i.e., N_D*=N_D1+N_D2).

[0028] The equation for threshold voltage of the double n-doped p-channel transistor is given by: $V_{{\mathrm{TH}}_P}=V_{\mathrm{FB}}+2{\psi }_{\mathrm{BP}}+\frac{2\sqrt{e{\epsilon }_s\left(N_{\mathrm{D1}}^{*}+N_{\mathrm{D2}}^{*}\right){\psi }_{\mathrm{BP}}}}{C_i}$

[0029] where V_FBis the flat-band voltage, ψ_BPis the band-bending at the surface of the p-channel transistor, e is the electronic charge, ε_sis the dielectric constant of silicon, N_D1* is the doping concentration of a first donor, N_D2* is the estimated doping concentration of a second donor, and C_iis the gate oxide capacitance per unit area.

[0030] The change in threshold voltage in the double n-doped p-channel transistor can be described by the equation below: $\Delta V_{{\mathrm{TH}}_P}\approx \frac{2\sqrt{e{\epsilon }_s\psi B_P}}{C_i}\left(\sqrt{N_{\mathrm{D1}}^{*}+N_{\mathrm{D2}}^{*}}-\sqrt{N_{\mathrm{D1}}^{*}}\right)$

[0031] With reference now to FIG. 2, there is illustrated a chart of ionization energies of different dopants in silicon. If an element has an ionization energy in silicon that is below the band gap center and has a “D” associated with its stated ionization energy, then the element is a good candidate for use as an electron donor. Alternatively, if an element has an ionization energy in silicon that is above the band gap energy and has an “A” associated with its stated ionization energy, then the element is a good candidate for use as an electron acceptor.

[0032] B. Infra-red Radiation

[0033] Even with the double-doped process, the threshold voltage of the transistors remains low at high temperatures because some dopants within the body and channels of transistors are not fully ionized. Thus, an infra-red (IR) source is utilized to increase the threshold voltage of these transistors. With the radiation from the IR source, photons are absorbed by the partially ionized dopants and electrons are excited to a higher state. When the electrons are in a higher state, the threshold voltage of the transistors increases.

[0034] Specifically, discrete wavelengths of light from the IR source are absorbed by an atom as an atom makes a transition from a state of lower energy to an excited state. The characteristics of the composition of an atom dictate what frequency of photon energy will be absorbed by the atom. In a preferred embodiment, hυ_N=E_A2−E_vfor the p-doped n-channel transistors and hυ_P=E_c−E_D2for the n-doped p-channel transistors, where h is the Planks constant and υ is the frequency of the IR light. The dopants are ionized only if E_F>E_A+2 kT for the p-doped n-channel transistors and E_F<E_D+2 kT for the n-doped p-channel transistors.

[0035] The efficiency of photon absorption depends on the radiation by the proper wavelength of IR source. Further, the intensity level of the IR source is very low such that there will be no detectable heating of the IC by the radiation from the IR source.

[0036] Referring now to FIG. 3, there is illustrated a pictorial diagram of a physical arrangement for performing a high-temperature burn-in test on ICs, in accordance with a preferred embodiment of the present invention. As shown, an IC 30 is affixed on a chip carrier 32 via solder bumps 31. In order to provide a high-temperature burn-in test on IC 30, a layer of thin-film 33, an IR filter 34, and a thermoelectric cooler 35 along with a heat spreader 36 is placed on top of IC 30 as shown in FIG. 3.

[0037] Thin-film 33 is utilized to conduct heat from IC 30 to thermoelectric cooler 35. Thin-film 33 is preferably made of diamond because of its high thermal conductivity (2000 W/m-K). In addition, diamond is also transparent to IR.

[0038] IR filter 34 can be adjusted to increase the Rayleigh resolution beyond the 0.5 μm limit imposed by an IR source. Many different types of IR filters can be utilized to selectively photoionize IC 30. Selective filtering would be useful to accommodate the differing ionization requirements of different functional areas of IC 30. For example, a cache memory may require a lower intensity of IR radiation than an input and/or output of IC 30.

[0039] IR radiation can be provided by many sources. Light Emitting Diodes (LEDs) that are based on direct band gap materials can be utilized to supply photons locally. Gallium Arsenide (GaAs) or Gallium Indigo Arsenide (GaInAs) devices can be tailored to produce high quantum efficiency IR wavelengths that closely match the absorption profile of the dopants in the silicon. The incident IR radiation is preferably collimated such that the IR radiation pattern is uniform. Thermoelectric cooler 356 and heat exchanger 36 are provided to lower the operating temperature of IC circuit 30.

[0040] With reference now to FIG. 4, there is illustrated a pictorial diagram of a physical arrangement for performing a high-temperature burn-in test on ICs, in accordance with an alternative embodiment of the present invention. This arrangement provides greater heat transfer capacity because the cooling apparatus (i.e., thermoelectric cooler 45 and heat spreader 46), can dissipate more heat into the ambient environment. Forced convection could also be utilized to enhance heat transfer. In addition, LEDs 42 are placed in close proximity to IC 40. These LEDs are preferably GaAs LEDs or GaInAs LEDs. Thin-film 43 is placed between IC 40 and LEDs 42. As described above, thin-film 43 is utilized to conduct heat from IC 40 to thermoelectric cooler 45.

[0041] As has been described, the present invention provides an improved method for performing a high-temperature burn-in test on integrated circuits.

[0042] While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.