Method of forming an inter-poly oxide layer

[0002] 1. Field of the Invention

[0003] The invention relates in general to a method of forming semiconductor integrated circuits (ICs), and more particularly to a method of forming an inter-poly oxide layer.

[0004] 2. Description of the Related Art

[0005] A conventional fabrication process of mixed mode devices comprises forming a pad oxide layer and a silicon nitride layer on a provided substrate. Active regions for forming transistors are defined on the substrate. A part of the silicon nitride layer and a part of the pad oxide layer are removed to form a field oxide layer to isolate the active regions from each other. A first polysilicon layer is formed on the active regions and the field oxide layer. A part of the first polysilicon layer is removed to form a lower electrode positioned over the field oxide layer using a photoresist layer. The silicon nitride layer and the pad oxide layer positioned on the active regions are removed. A gate oxide layer is formed on the active regions by thermal oxidation. At the same time, an oxide layer is formed on the profile of the lower electrode. A conformal second polysilicon layer is formed on the substrate. A silicide layer is formed on the second polysilicon layer. A part of the silicide layer and a part of the second polysilicon layer are removed to form a gate of a transistor and an upper electrode. The gate is formed on the gate oxide layer. The lower electrode, the oxide layer and the upper electrode constitute a capacitor on the field oxide layer.

[0006] FIG. 1 is a schematic. cross-sectional view showing a conventional, mixed mode device comprising a capacitor and a transistor. A gate 111 is formed on a gate oxide layer 105. A capacitor 101 is formed on a field oxide layer 103. The capacitor 101 consists of a polysilicon layer as a bottom electrode 107, another polysilicon layer as a top electrode 109 and a dielectric layer 113, such as a silicon oxide layer, between the top electrode 109 and the bottom electrode 107. The dielectric layer 113 is called inter-poly oxide layer 113.

[0007] FIGS. 2A to 2E are schematic, cross-sectional views showing a conventional process for forming a mixed mode device. In FIG. 2A, a substrate 201 is provided. A field oxide layer 203 is formed on the substrate 201 to isolate an active region 201a.A gate oxide layer 205 is formed on the active region 201a,for example, by thermal oxidation.

[0008] In FIG. 2B, a polysilicon layer 207 is formed over the substrate 201 to cover the gate oxide layer 205 and the field oxide layer 203.

[0009] In FIG. 2C, the polysilicon layer 207 is defined to form a gate 207bon the gate oxide layer 205 and to form a bottom electrode 207aof a capacitor on the field oxide layer 203.

[0010] In FIG. 2D, an inter-poly oxide layer 209ais formed on the bottom electrode 207a.At the same time, an oxide layer 209bis formed on the gate 207bso that the oxide layer 209band the inter-poly oxide layer 209ahave the same thick. Since the inter-poly oxide layer 209ais used as a dielectric layer of the capacitor, the thickness and the uniformity of the inter-poly oxide layer 209ado affect the capacitor quality.

[0011] In FIG. 2E, a top electrode 211, such as a polysilicon layer, is formed on the inter-poly oxide layer 209ato complete the capacitor of the mixed mode device.

[0012] According to the description the conventional method performs two oxidation steps to form the gate oxide layer 205 and to form the inter-poly oxide layer 209a.These steps require a long reacting time (silicon oxide with 1000 Å requires about 2-8 hours to react). Furthermore a silicon oxide layer formed on a polysilicon layer is too non-uniform to be the dielectric layer of a capacitor so that capacitance of the capacitor is increased only with difficulty.

[0013] It is therefore an object of the invention to provide a method of forming an inter-poly oxide layer to obtain a better uniformity of the inter-poly oxide layer than a conventional inter-poly oxide layer. The inter-poly oxide layer is applied to form a capacitor of a DRAM, an EPROM, an E²PROM or a mixed mode device.

[0014] It is another object of the invention to provide a method to decrease oxidation rate by doping an impurity into an epitaxial silicon layer to form a thin oxide layer. According the invention, a oxidation step is skipped to save the reaction time for forming the oxide layer.

[0015] The invention achieves the above-identified objects by providing a method of forming an inter-poly oxide layer. A substrate having a field oxide layer thereon is provided. A first polysilicon layer is formed on the field oxide layer. The surface of the first polysilicon layer is destroyed by heavy ions to form an amorphous silicon surface. The amorphous silicon surface converts to an epitaxial silicon film by annealing. The epitaxial silicon film and the remaining first polysilicon layer are defined to form a bottom electrode of a capacitor. An oxide layer as a dielectric layer of the capacitor is formed by oxidizing the epitaxial silicon layer. At the same time, a gate oxide layer is formed on the exposed substrate.

[0016] Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings in which:

[0017] FIG. 1 is a schematic, cross-sectional view showing a conventional mixed mode device comprising a capacitor and transistor;

[0018] FIGS. 2A to 2E are schematic, cross-sectional views showing a conventional process for forming a mixed mode device; and

[0019] FIGS. 3A to 3F are schematic, cross-sectional views showing steps of one preferred embodiment of the method of forming an inter-poly oxide layer.

[0020] In FIG. 3A, a substrate 301 is provided. A field oxide layer 303 is formed on the substrate 301 to isolate an active region 301aof the substrate 301. A first polysilicon layer 307 is formed on the substrate 301 and the field oxide layer 303. The preferred method to form the first polysilicon layer comprises low-pressure chemical vapor deposition (LPCVD) using SiH₄as a source. The surface of the first polysilicon layer 307 is treated to form an epitaixial film 308. A preferred method to form the epitaxial film 308 comprises the following, steps. Plasma 309 with heavy ions is applied at the surface of the first polysilicon layer 307 about 5-100 seconds to form an amorphous layer thereon. For example, the plasma comprises argon ion with a flowing rate of about 100-2000 sccm and with a power of about 50-1000 Watts. The amorphous layer is converted to the epitaxial film 308 by annealing. The annealing is performed, for example, by furnace or rapid thermal oxidation under about 800-1000° C.

[0021] In FIG. 3B, impurity, such as nitrogen, is doped into the epitaxial film 308 to form a doped epitaxial film 308a.A preferred method of doping the impurity is ion implantation. The oxidizing rate of silicon is reduced for doping the impurity.

[0022] In FIG. 3C, the first polysilicon layer 307 and the doped epitaxial film 308aare defined, for example, using a photolithography and etching process. A part of the first polysilicon layer 307aused as a bottom electrode and a part of the epitaxial film 308bremain on the field oxide layer 303.

[0023] In FIG. 3D, the remaining epitaxial film 308bis oxidized, for example, by thermal oxidation to form an inter-poly oxide layer 315bas a dielectric layer of a capacitor on the bottom electrode 307a.In the same oxidation step, a gate oxide layer 315ais formed on the substrate positioned on the active region 301a.Since the doping epitaxial film 308band the substrate 301 are different, the oxidation rates of the doping epitaxial film 308band of the substrate 301 are different. The inter-poly oxide layer 315bis thus thinner than the gate oxide layer 315a.Furthermore, the inter-poly oxide layer 315bis formed from the doping epitaxial film 308bso that the inter-poly oxide layer is uniform.

[0024] In FIG. 3E, a second polysilicon layer 317 is formed, for example, by chemical vapor deposition (CVD) on the structure shown in FIG. 3D to cover the gate oxide layer 315aand the inter-poly oxide layer 315b.

[0025] In FIG. 3F, the second polysilicon layer 317 is defined to form a gate 317aon the gate oxide layer 315aand to form a top electrode 317bon the inter-poly oxide layer 315b.A transistor gate and a capacitor are thus formed. The transistor and the capacitor together make a mixed mode device.

[0026] A gate structure of a flash memory, an EPROM or an EP²ROM comprises a floating gate a control gate and a dielectric layer between the floating gate and the control gate. The gate structure is similar in structure to the capacitor of the mixed mode devices. A capacitor in a memory cell of a DRAM is similar in structure to the capacitor of the mixed mode device, too. The invention thus provides a method which applies to forming DRAMs, flash memories, EPROMs and E²PROMs.

[0027] A feature of the invention is the performance of an ion implantation step and an annealing step on the surface of a polysilicon layer to form an epitaxial film. The epitaxial film is oxidized to form a thin and uniform oxide layer. The oxide layer is used as a dielectric layer of a capacitor to enhance the capacitance of the capacitor.

[0028] Another feature of the invention is that the oxide layer is thinner than the gate oxide layer from doping impurity into the epitaxial film. The thickness of the oxide layer is controlled by a concentration of the impurity in the epitaxial film.

[0029] Yet another feature of the invention is that the gate oxide layer and the oxide layer are formed at the same time so that an oxidation step is saved. Process time is thus reduced to enhance the performance of forming a mixed mode device.

[0030] Yet another feature of the invention is that the method applies to form oxide layers with high quality of DRAMs, of flash memories, of EPROMs or of E²PROMs.

[0031] While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.