Dual damascene manufacturing process

[0002] This application claims the priority benefit of Taiwan application Ser. No. 87108191, filed May 26, 1998, the full disclosure of which is incorporated herein by reference.

[0003] 1. Field of Invention

[0004] The present invention relates to a method of manufacturing multi-level interconnects in semiconductor manufacture. More particularly, the present invention relates to a method of manufacturing multi-level interconnects using a dual damascene process.

[0005] 2. Description of Related Art

[0006] A typical integrated circuit comprises various devices and components. These devices or components are typically insulated by an isolation structure. To electrically connect certain parts of the devices or component, an interconnect is commonly used. In the conventional method of manufacturing interconnects, a metallic layer is deposited over a substrate. A portion of the metallic layer is etched away to form a desired metallic wiring pattern. The metallic wiring pattern is then covered by an insulation layer to is to avoid any unwanted connection to other conductive part of layer. A vertical via hole is formed through the insulation layer to electrically connect the metallic wiring layer. In general, an inter-metal dielectric (IMD) layer is used as an insulation layer to isolate the metallic layer other metallic layer or metallic wiring. The connection between the metallic layer and other metallic layer or metallic wiring is achieved through a vertical via.

[0007] At present, two methods of fabricating interconnects such as plugs or vias are used in the semiconductor industry. The first method uses two separate stages for forming the interconnects. A dielectric layer is formed over a first metallic layer, and then a photoresist layer is deposited over the dielectric layer. Etching techniques are used to form a via hole, and then a conductive material is deposited into the via holes to form a via for electrical connection. A second metallic layer is deposited over the dielectric layer followed by the patterning of the second metallic layer.

[0008] This second method is a dual damascene process. In the conventional dual damascene process, an insulation layer is first formed over a substrate structure, and then the insulation layer is planarized. According to the required metallic wiring pattern and positions of vias, the insulating layer is etched to form horizontal trenches and vertical via holes. In other words, the lower portion of the insulating layer is etched to expose some of the device regions or portions of the metallic lines below, thereby to form a vertical via hole. The upper portion of the insulating layer is also etched to form a horizontal trench. A metallic material is then deposited over the substrate structure to fill the horizontal trench and the via hole at the same. Chemical-mechanical polishing (CMP) method is used to planarize the surfaces of the devices, and then another dual damascene process can be carried out again. Since two metal-filling operations for forming the respective horizontal trenches and vertical via holes are combined into a single operation, the operation is referred to as a dual damascene process.

[0009] FIGS. 1A through 1I are cross-sectional views showing the progression of manufacturing steps in producing interconnects using a conventional dual damascene process.

[0010] As shown in FIG. 1A, a substrate structure 100 having a planar surface is provided. For clarity, devices within the substrate structure 100 are not sketched. A metallic layer 101 is formed over the substrate structure 100. A patterned photoresist layer 104 is formed over the metallic layer 101. The patterned photoresist layer 104 covers regions above the metallic layer 101 where metallic lines are desired.

[0011] As shown in FIG. 1B, using the photoresist layer 104 as a mask, the metallic layer 101 is etched. For example, a reactive ion etching (RIE) method is used to etch away a portion of the metallic layer 101 forming metallic lines 101a, 101band 101cand exposing the substrate structure 100 below. Subsequently, the photoresist layer 104 is removed.

[0012] In FIG. 1C, an insulation layer 105, for example, a silicon oxide layer is deposited over the substrate structure 100. Excess insulation layer 105 above the metal lines 101a, 101band 101care removed using, for example, a chemical-mechanical polishing (CMP). Hence, the top surface of the metal lines 101a, 101band 101care exposed.

[0013] In FIG. 1D, another insulation layer 106, for example, a silicon oxide layer are deposited over the substrate structure 100 and covering the metal lines 101a, 101band 101cand the insulation layer 105. The insulation layer 106 has a thickness roughly equals to the vertical height of subsequently formed metal plugs. After that, the insulation layer 106 is planarized, and then an etching stop layer 108, for example, a silicon nitride layer is deposited over the insulation layer 106. Subsequently, another patterned photoresist layer 114 is formed over the etching stop layer 108. The patterned photoresist layer 114 exposes regions on the etching stop layer where vias for extending to the respective metal lines 101aand 101care desired.

[0014] In FIG. 1E, using the photoresist layer 114 as a mask, the silicon nitride layer 108 is etched. For example, using a reactive ion etching (RIE) method, openings 113 and 123 are formed in the etching stop layer 108a. The openings 113 and 123 exposes a portion of the insulation layer 106 in regions that correspond to the locations where vias leading to the metal lines 101aand 101care desired. Subsequently, the photoresist layer 114 is removed.

[0015] In FIG. 1F, a third insulation layer 116, for example, a silicon oxide layer is deposited over the etching stop layer 108a. The third insulation layer 116 has a thickness roughly equal to the thickness of the horizontal trenches after the dual damascene structure is formed. Thereafter, a third patterned photoresist layer 124 is formed over the insulation layer 116. The third patterned photoresist layer 124 exposes a portion of the insulation layer 116 in regions that correspond to the locations where the final horizontal trenches that have connections with the metal lines 101aand 101care desired.

[0016] In FIG. 1G, using the third photoresist layer 124 as a mask, the third insulation layer 116 is etched. For example, a reactive ion etching (RIE) is used to etch out horizontal trenches 115aand 125ain the insulation layer 116 where metal lines will be formed. A portion of the horizontal trenches 115aand 125aare aligned over the subsequently formed via holes 115band 125brespectively. Thereafter, the insulation layer 106ais etched to form via holes 115band 125bthat exposes the respective metal lines 101aand 101c. Due to the presence of the etching stop layer 108a, a top-wide/bottom-narrow type of openings such as 115 and 125 can be formed by using an etchant having a high etching selectivity for silicon oxide in the etching operation. Subsequently, the photoresist layer 124 is removed.

[0017] In FIG. 1H, a conformal glue/barrier layer 122 is deposited over the horizontal trenches 115aand 125aas well as the vertical via holes 115band 125b. The conformal glue/barrier layer 122 serves to increase adhesion of subsequently deposited metal or other materials. Thereafter, a metallic layer 121 is deposited over the insulation layer 116aand filling the horizontal trenches 115aand 125aas well as the vertical via holes 115band 125b.

[0018] In FIG. 1I, a chemical-mechanical polishing method is used to remove redundant portions of the metallic layer 121 above the insulation layer 116aexposing the insulation layer 116a. Hence, dual damascene structures 121aand 121bare formed.

[0019] In the above dual damascene process of forming metal interconnects such as contact vias or plugs, complicated steps are needed to form the tapering vias. In fact, major defects of the above method includes:

[0020] 1. At least two insulation layers (that is, inter-metal dielectric layer) are reguired.

[0021] 2. At least an additional etch stop layer is required, and consequently, at least a photolithography and etching process is required for forming the etch stop layer.

[0022] 3. The vias are not formed self-aligned. A misalignment is easily to occur during photolithography and etching process.

[0023] Accordingly, the present invention is to provide an improved dual damascene process for forming interconnects and vias. The dual damascene process not only is capable of preventing the defects produced by a conventional dual damascene process, but is also capable of simplifying operational procedure.

[0024] To achieve these and other advantages and in accordance with the purpose of the invention, a process of dual damascene process is provided. A metallic layer and a first insulation layer are formed over a substrate structure in sequence. The first insulation layer and the metallic layer are patterned, so that a metallic line with a conformal insulation layer thereon is formed. The first insulation layer on the metal line is patterned, so that a part of the metallic line is covered by the first insulation layer, and the other part of the metal line is exposed. The part of the metallic line covered by the first insulation layer is called the first metal line, and the exposed part of the metallic line is the second metal line. A second insulation layer is formed over the substrate structure. The second insulation layer is patterned to form a horizontal trench that exposes the first insulation layer on the second metal line. The first insulation layer is then removed to form a vertical via which exposes the second metal line. A second metallic layer is formed over the second insulation layer to fill the trenches and the vertical vias and thus, to electrically connect the second metal line. The second metallic layer is then planarized until the insulation layer is exposed.

[0025] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0026] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, FIGS. 1A through 1I are cross-sectional views showing the progression of manufacturing steps in producing vias and interconnects using a conventional dual damascene process; and

[0027] FIGS. 2A through 2K are cross-sectional views showing the progression of manufacturing steps in producing vias and interconnects using a dual damascene process according to one preferred embodiment of this invention.

[0028] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0029] FIGS. 2A through 2K are cross-sectional views showing the progression of manufacturing steps in producing vias and interconnects using a dual damascene process according to one preferred embodiment of this invention

[0030] As shown in FIG. 2A, a substrate structure 200 is provided. Preferably, the substrate structure 200 is planarized to advantage the subsequent process. A conductive layer 201 is formed over the substrate structure 200. The conductive layer 201 is typically copper, aluminum, or aluminum-copper alloy, though other conductive materials may also be used. Thereafter, an insulation layer 208 is formed over the metallic layer 201 using, for example, a chemical vapor deposition method or other deposition methods. A patterned photoresist layer 204 is formed on regions of the insulation layer 208. The regions covered by the photo-resist layer 204 are the regions for forming metal lines.

[0031] As shown in FIG. 2B, using the photoresist layer 204 as a mask, the exposed regions of the insulation layer 208 and the metallic layer 201 under the exposed regions are etched to form metal lines 210a, 201band 201c. At the same time, patterned insulation layers 208a, 208band 208cconformal to the metal lines 210a, 210b, and 210care formed on the metal lines 201a, 201band 201c, respectively. A top view of the patterned insulation layers 208a, 208b, and 208care shown as FIG. 2C. The insulation layer 208 may be defined into different patterns according to the specific requirements or the configuration of the metal lines. A column shape is used as an example for the metal lines 201a, 201a, and 201cin this embodiment.

[0032] As shown in FIG. 2D, vertical vias are defined by using dual damascene process. That is, a patterned photoresist layer (not shown in the figure) is formed to cover predetermined regions of the insulation layers 208a, 208band 208cabove the metal lines 201a, 201band 201c. In this example, the insulation layers 208bis completely covered by the patterned photoresist layer. However, only a part of each of the insulation layers 208aand 208care covered by the photoresist layer. The insulation layers 208a, 208band 208care then etched by, preferably, a reactive ion etching (RIE) method, though other etching processes may be used. The upper surfaces of the metal lines 201a, 201band 201care used as etch stop in the etching operation. Consequently, a pattern of pillars of insulation layers 208dand 208eare formed. A part of the top surface of the metal lines 201aand 201cand the whole top surface 212 of the metal line 201bare exposed. The pillars of insulation layers 208dand 208eact as studs in the subsequent fabrication process for forming vertical vias. Moreover, the pillars of insulation layers 208dand 208ecan be completely conformal or only partially conformal to the metal lines 201aand 201c, depending on the design and specific requirements for forming vertical vias. Subsequently, when the horizontal trenches of the dual damascene structure are formed, the stud-like insulation layers 208dand 208ecan be removed to obtain vias that self-align with the respective metal lines. The top view of the stud-like insulation layers 208dand 208eis shown as FIG. 2E.

[0033] As shown in FIG. 2F, an insulation layer 206, for example, a silicon oxide layer deposited by a chemical vapor deposition method is formed over the substrate structure 200. The insulation layer 206 covers the columnar insulation layers 208dand 208eas well as the metal lines 201a, 201band 201c. The insulation layer 206 is planarized, preferably, by chemical-mechanical polishing (CMP), though other planarization technique may be applied. Advantageously, after being planarized, the insulation layer 206 remained on the pillars of insulation layers 208dand 208ehas approximately a same thickness of a horizontal trenches formed by a subsequently dual damascene process. That is, the thickness between the top surface of the insulation layer 206 and a level of the top surfaces 218dand 218eis approximately the same as the depth of the horizontal trenches formed by a subsequently dual damascene process.

[0034] In FIG. 2G, a patterned photoresist layer 214 is formed over the insulation layer 206 with openings aligned over the pillars of the insulation layers 208dand 208e. Regions of the insulation layer 206 determined for forming metal lines subsequently are exposed within the openings. That is, in this example, the insulation layer 206 covering the pillars 208dand 208eis exposed.

[0035] In FIG. 2H, using the photoresist layer 214 as a mask, the exposed insulation layer 206 is etched using, for example, a reactive ion etching (RIE) method with the pillars of insulation layers 208dand 208eas an etch stop. As a consequence, horizontal trenches 215aand 225aare formed in the insulation layer 206ato expose the upper surfaces 218 and 219 of the pillars of insulation layers 208dand 208e. Since the positions for forming the vertical vias are pre-arranged at the locations occupied by the pillars of insulation layers 208dand 208e, self-aligned vias are easy to obtain. The self-aligned vias can be formed easily by using an etchant having a higher etching selectivity for material of the pillars of insulation layers 208dand 208eto than insulation layer 206a.

[0036] In FIG. 21, the pillars of insulation layers 208dand 208eare etched to form self-aligned vias 215band 225bin the insulation layer 206a. As mentioned above, the pillars of the insulation layers 208dand 208eare removed by etching with a higher selectivity than the insulation layer 206a, so that substantially, the pillars of the insulation layers 208dand 208eare removed without removing the insulation layer 206a. Also, the thickness between top surface of the insulation layer 206aand the bottom level of the openings 215aand 215bare approximately the same. Even if a portion of the insulation layer 206ais removed while etching the pillars 208dand 208e, with a much lower selectivity, the thickness of the removed portion of the insulation layer 206ais much less than the depth of the horizontal trenches 215aand 225a. The dual damascene structure, that is, the topography of the horizontal trenches 215a, 225aand the openings 215b, 225bis still well defined.

[0037] Preferably, the studs 208dand 208eare removed by immersing the wafer in an etchant having a high etching selectivity for the material of the studs to the insulation layer 206a, though the studs 208dand 208ecan also be removed by other etching processes. After the etching operation, the openings 215band 225bare aligned precisely over the metal lines 201aand 201c. The horizontal trenches 215aand 225bare combined with the openings 215band 215bas contact windows 215 and 225, respectively. Hence, the dual damascene process of this invention is capable of producing vias or contact windows self-aligned over the metal lines.

[0038] In FIG. 2J, a conformal glue/barrier layer 222 is deposited on the surface of the contact windows 215 and 225. The glue/barrier layer 222 can be selected from a composite conductive layer, for example, a titanium/titanium nitride (Ti/TiN) layer or a tantalum/tantalum nitride (Ta/TaN) layer, though other material may also be used. The glue/barrier layer 222 mainly serves to increase adhesion between subsequently deposited metallic material and the metal lines 201a, 201b, and 201c, or avoid mutual diffusion between the metal lines 201a, 201b, 201cand the subsequently deposited metallic material.

[0039] A metallic layer 221 selected from at least one of the materials such as, for example, copper, aluminum, or aluminum-copper alloy or other conductive materials is deposited to cover the insulation layer 206aand fill the windows 215 and 225. Hence, electrical connection for the metal lines 201aand 201cis established.

[0040] In FIG. 2K, a planarization process, for example, a chemical-mechanical polishing (CMP) opera, is performed to planarize and to remove the excessive metallic layer 221 above the insulation layer 206a. The upper surface of the insulation layer 206ais exposed and dual damascene structures, vertical vias, 221aand 221bare formed.

[0041] In the invention, the predetermined positions for forming vertical vias above the metal lines are occupied by pillars of insulation layers (studs). The horizontal trenches are formed to expose the pillars. The vertical vias are formed precisely aligned with the metal lines without additional operations. Therefore, the vias are consider self-aligned.

[0042] In a conventional dual damascene process, generally, deposition of two or more etching stop layers and two insulation layers are required. Furthermore more than one photolithograph and etching process is required. The multiple photolithograph and etching process cause a great possibility of misalignment, especially for process of sub-micron line width. The dual damascene process of this invention reduces the steps of the manufacturing process, especially, the photolithography and etching process, and hence, capable of increasing precision of process and reducing processing time and production cost.

[0043] The processing steps and equipment used in this invention are compatible with most manufacturing facilities, and hence can be easily arranged for production.

[0044] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.