Method of forming shallow trench isolation by HDPCVD oxide

[0002] (1) Field of the Invention

[0003] The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming planarized shallow trench isolation in the fabrication of integrated circuits.

[0004] (2) Description of the Prior Art

[0005] Shallow trench isolation (STI) is gaining substantial interest for deep sub-micron processes. To achieve good planarity after STI, chemical mechanical polishing (CMP) is a more promising solution than is etchback. However, due to pad deformation, the trench open area is susceptible to dishing which causes oxide thinning in the wide trench. In addition, the pattern dependency of CMP leads to non-uniform oxide removal on the silicon nitride underlayer of different dimensions. In order to remove all the oxide on the silicon nitride before nitride stripping, overpolishing is generally carried out at the cost of severe oxide dishing and silicon nitride erosion.

[0006] FIG. 1 illustrates a partially completed integrated circuit device of the prior art. A pad oxide layer 12 and a silicon nitride layer 14 have been deposited over the surface of a semiconductor substrate 10. Trenches in the substrate have been filled with an oxide 17 which has been polished using CMP. Oxide dishing and silicon nitride erosion can both be seen in area 19.

[0007] In order to reduce these problems, the use of a reverse tone mask at the device pattern layer has been proposed. But, due to the great difficulties in overlaying the device pattern mask and reverse-tone device pattern mask on a non-planarized oxide surface, this approach becomes very challenging for deep sub-micron processes.

[0008] U.S. Pat. No. 5,275,965 to Manning shows a method of forming trench isolation using gated sidewalls. U.S. Pat. No. 5,494,857 to Cooperman et al teaches CMP shallow trenches using a reverse-tone mask and a silicon nitride polish stop layer. U.S. Pat. No. 5,518,950 to Ibok et al shows a method in which spin-on-glass in trenches is covered with a resist mask to increase the spin-on-glass thickness over the trenches.

[0009] Accordingly, the primary object of the invention is to provide a process for forming planarized shallow trench isolation in the fabrication of integrated circuits.

[0010] A further object of the invention is to provide a process for forming planarized shallow trench isolation in which oxide dishing is eliminated.

[0011] Still another object is to provide a process for forming planarized shallow trench isolation in which silicon nitride erosion is reduced.

[0012] Yet another object of the invention is to provide a process for forming planarized shallow trench isolation in which CMP uniformity is improved.

[0013] In accordance with the objects of the invention, a method for forming planarized shallow trench isolation is achieved. A pad oxide layer is grown over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate wherein there are at least one first wide nitride region between two of the trenches and at least one second narrow nitride region between another two of the trenches. A high density plasma oxide layer is deposited over the nitride layer and within the isolation trenches wherein the high density plasma oxide layer fills the isolation trenches and wherein the high density plasma oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer. A photoresist mask is formed over the high density plasma oxide layer. The substrate is exposed to actinic light wherein a central portion of the first region is exposed. The high density plasma oxide layer is etched away where it has been exposed. The high density plasma oxide layer remaining is polished away whereby the substrate is planarized and fabrication of said integrated circuit device is completed.

[0014] In the accompanying drawings forming a material part of this description, there is shown:

[0015] FIG. 1 is a cross-sectional representation of an embodiment of the prior art.

[0016] FIGS. 2 through 7 are cross-sectional representations of a preferred embodiment of the present invention.

[0017] FIG. 8 is a cross-sectional representation of a completed integrated circuit device fabricated by the process of the present invention.

[0018] Referring now more particularly to FIG. 2, there is shown a semiconductor substrate 10. A layer of pad silicon oxide 12 is grown on the surface of the semiconductor substrate to a thickness of between about 100 and 150 Angstroms. A layer of silicon nitride 14 is deposited over the pad oxide layer 12 to a thickness of between about 1500 and 2000 Angstroms.

[0019] Referring now to FIG. 3, shallow trenches are etched into the silicon substrate using conventional photolithography and etching techniques. The shallow trenches 16 are etched to a depth of between about 3000 and 5000 Angstroms into the semiconductor substrate.

[0020] A lining oxide layer 18 is grown on the exposed silicon surface on the bottom and sidewalls of the trenches to a thickness of between about 300 and 400 Angstroms. The lining oxide ensures a good-quality sidewall between the silicon substrate and the trench oxide.

[0021] Next, as illustrated in FIG. 4, a layer of high density plasma oxide 20 is deposited by chemical vapor deposition (HDPCVD) to a thickness of about 7000 Angstroms over the surface of the substrate and filling the trenches. The HDPCVD oxide is deposited by flowing silane, oxygen, and argon gases.

[0022] Because of the characteristics of the HDPCVD deposition, the oxide overlying the narrow silicon nitride areas 21 is thin while the oxide overlying the wide silicon nitride areas 22 is thick. For example, for a silicon nitride width of about 0.3 micron, the HDPCVD oxide would have a thickness of about 0.15 micron. A silicon nitride width of about 1.0 micron would have a HDPCVD oxide thickness of about 0.55 micron. This thickness difference causes problems. In the thinner areas 21, silicon nitride erosion and silicon polishing may occur which would damage the device areas. In the thicker areas 22, some of the oxide may remain making the nitride stripping difficult.

[0023] The process of the invention resolves these problems with HDPCVD oxide. Referring to FIG. 5, the HDPCVD oxide 20 is patterned by exposing the wide silicon nitride areas on which the oxide 20 is thick; that is, those areas wider than 1 micron. A bias 25 is imposed so that the exposure area is smaller than the dimension of the silicon nitride. Since the exposed area is large, the bias is not critical. For example, for a 1 micron wide silicon nitride area, a 0.8 micron window might be used.

[0024] The photoresist mask 24 is shown in FIG. 5. The HDPCVD oxide 20 that is exposed is etched away to the silicon nitride layer 14 using either a wet or a dry etch, as illustrated in FIG. 6. The thickest HDPCVD oxide has now been removed. The photoresist mask is stripped.

[0025] Referring now to FIG. 7, the residual oxide 20 on the narrow silicon nitride areas is polished, stopping at the silicon nitride layer. The amount of residual oxide to be polished is greatly reduced; therefore, chemical mechanical polishing (CMP) throughput and uniformity are improved significantly. The short polish time and the good uniformity also prevent silicon nitride erosion. Also, dishing over the wide trench is eliminated since the trench oxide becomes extruded before polishing. Oxide remaining on the silicon nitride is eliminated since the thick oxide over the wide silicon nitride areas is etched away before polishing. Through the process of the present invention, the oxide thickness can be reduced to only about 1000 to 2000 Angstroms above the trench. The CMP process can easily polish away that thickness of oxide above the trenches.

[0026] The silicon nitride is etched away and the pad oxide is removed completing the formation of the shallow trench isolation. Semiconductor device structures, including gate electrodes 32 and source and drain regions 34 may be formed as is conventional in the art. Electrical contacts 38 may be made through dielectric isolation layer 36, as shown in FIG. 8.

[0027] The process of the present invention results in the formation of planarized shallow trench isolation using HDPCVD oxide wherein oxide dishing is eliminated, silicon nitride erosion is reduced, CMP uniformity is improved, and CVD and CMP throughputs are improved.

[0028] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.