Offset-compensated switched-opamp integrator and filter

[0002] 1. Field of the Invention

[0003] The present invention generally relates to an integrator and filter constituted of one or more offset-compensated switched-capacitor circuits. More specifically, it relates to an integrator and filter capable of working under a low operation voltage.

[0004] 2. Description of Related Art

[0005] To achieve faster operation, integrated circuits require an increase in integration, thereby increasing power consumption. Hence, a low operation voltage is desired for various integrated circuits and systems processing analog or digital signals. Many technicians try to improve fabrication arts, circuit and logic design, structure, or algorithms to meet the requirements of low operation voltage to drive communication, electronic, and computer products. One of the most direct improvements is to modify the circuit design to operate the integrated circuit under a low supply voltage and then reduce the power consumption. In the such circuit design, many MOS transistors within integrators and filters are used to implement the integrated circuit. But the threshold voltage of MOS transistors (about 0.7 to 1 voltage) actually limits their practical utility.

[0006] Conventional switched-capacitor circuits are mainly applied to implement the analog and digital signal process circuits, including analog-to-digital converters, digital-to-analog converters, and sampling-hold circuits. However, the offset voltages of amplifiers in the integrators and filters effect the operation precision. Solutions for the above problem include (1)MOS switches with low threshold voltages disclosed in “A 1.4V switched capacitor filter”, in IEEE Proceeding of CICC, pp. 8.2.1-8.3.4, May 1900, by K. Takasuka, etc., (2)a method to raise the clock boosting disclosed in “1.2V CMOS switched-capacitor circuits”, in IEEE Int. Solid-State Circuit Conference, pp. 388-389, February 1996, by J. T. Wu., etc., and (3)a switched-opamp technique disclosed in “Switched-opamp: an approach to realize full CMOS switched-capacitor circuit at very low power supply voltage”, IEEE J. Solid-State Circuit, SC-29, pp. 936-942, August 1994 by J. Crols, etc. A specific fabricating process is necessary to realize method (1), so the cost is higher than common methods. While the mentioned specific fabricating process is not needed in method (2), the trend of semiconductor devices is to low operation voltage. And while it is not necessary to execute the specific fabricating process or raise the clock boosting in method (3), the offset voltage problem from MOS transistors still exists.

[0007] It is therefore an object of the present invention to provide an offset-compensated switched-capacitor integrator and filter, which can be operated under a low supply voltage and compensate the offset voltage of the opamp with switched-capacitor circuits, thereby improving the operation precision.

[0008] The present invention provides one integrator having offset-compensated switched-capacitor circuits, which can be operated under a low power voltage, comprising a first amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal, and an output terminal; a first capacitor, which has a terminal receiving said input signal and another terminal coupled to said inverting input terminal of said first amplifier; a first switch coupled between said first capacitor and said ground; a second switch and a third switch coupled to said inverting input terminal of said first amplifier, wherein said third switch is also coupled to said output terminal of said first amplifier; a second capacitor, which has a terminal coupled to said second switch and another terminal coupled to said output terminal of said first amplifier; a third capacitor coupled to said output terminal of said first amplifier; a second amplifier comprising a non-inverting input terminal coupled to said ground, an inverting input terminal coupled to said three capacitors, and an output terminal; and a fourth capacitor and a fourth switch coupled in parallel between said inverting input terminal and said output terminal of said second amplifier; wherein a first timing waveform operates said first switch and second switch and a second timing waveform operates said third switch and fourth switch, said first and second timing waveforms having a same period and showing different logic levels at the same time.

[0009] The present invention provides another integrator having offset-compensated switched-capacitor circuits, which is able to be operated under a low power voltage, comprising a first amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal, and an output terminal; a fifth capacitor coupled to said inverting input terminal of said first amplifier; a first capacitor, which has a first terminal coupled to said fifth capacitor and a second terminal receiving an input signal; a first switch coupled between said second terminal of said first capacitor and said ground; a second switch coupled between said ground and a terminal coupling said first capacitor and said fifth capacitor; a third switch coupled to said terminal coupling and said first capacitor said fifth capacitor; a second capacitor coupled between said third switch and said output terminal of said first amplifier; a fourth switch coupled between said inverting input terminal and said output terminal of said first amplifier; a third capacitor coupled to said output terminal of said first amplifier; a second amplifier comprising a non-inverting input terminal coupled to said ground, an inverting input terminal coupled to said three capacitors, and an output terminal; and a fourth capacitor and a fifth switch coupled in parallel between said inverting input terminal and said output terminal of said second amplifier; wherein a first timing waveform operates said first, second and fourth switches and a second timing waveform operates said third switch and fifth switch, said first and second timing waveforms having a same period and showing different logic levels at the same time.

[0010] The present invention provides one filter having offset-compensated switched-capacitor circuits, which can be operated under a low supply voltage, comprising a first amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal, and an output terminal; a first capacitor coupled to said inverting input terminal of said first amplifier; a first switch coupled between said first capacitor and a signal input terminal; a second switch coupled between said ground and a terminal coupling said first capacitor and said first switch; a second capacitor coupled to said output terminal of said first amplifier; a third switch coupled between said inverting input terminal of said first amplifier and said second capacitor; a fourth switch coupled between said output terminal and said inverting input terminal of said first amplifier; a third capacitor coupled to said output terminal of said first amplifier; a second amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal coupled to said third capacitor, and an output terminal; a fourth capacitor and a fifth switch coupled in parallel between said inverting input terminal and said output terminal of said second amplifier; a fifth capacitor coupled to said output terminal of said second amplifier; a seventh switch coupled to said fifth capacitor; a sixth switch coupled between said inverting terminal of said second amplifier and a terminal coupling said fifth capacitor and said seventh switch; a ninth capacitor coupled to said seventh switch; an eighth switch coupled between said ground and a terminal coupling said seventh switch and said ninth capacitor; a third amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal coupled to said ninth capacitor, and an output terminal; a ninth switch coupled between said inverting input terminal and said output terminal of said third amplifier; a tenth switch and an eleventh switch coupled in parallel to a terminal coupling said ninth capacitor and said seventh switch; a six capacitor coupled between said tenth switch and said output terminal of said third amplifier; a seventh capacitor coupled between said eleventh switch and said output terminal of said third amplifier; a twelfth switch coupled between said inverting input terminal of said third amplifier and a terminal coupling said eleventh switch and said seventh capacitor; an eighth capacitor coupled to said output terminal of said third amplifier; a thirteenth switch coupled between said eighth capacitor and said ground; and a fourteenth switch coupled to said inverting input terminal of said first amplifier and a terminal coupling said eighth capacitor and said thirteenth switch; wherein a first timing waveform operates said second, third, fifth, sixth, eighth, ninth, eleventh, twelfth, and fourteenth switches and a second timing waveform operates said first, fourth, seventh, tenth, and thirteenth switch, said first and second timing waveforms having a same period and showing different logic levels at the same time.

[0011] The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:

[0012] FIG. 1 is a circuit diagram illustrating a low-pass filter of the prior art.

[0013] FIG. 2 is a circuit diagram illustrating a non-inverting integrator of a preferred embodiment of the present invention;

[0014] FIG. 3 is a timing diagram applied in all embodiments of this application;

[0015] FIG. 4 is a circuit diagram illustrating an inverting integrator of another preferred embodiment of the present invention; and

[0016] FIG. 5 is a circuit diagram illustrating a low-pass filter of another preferred embodiment of the present invention.

[0017] Referring to FIG. 2, a preferred embodiment in accordance with the present invention is shown as a non-inverting integrator circuit, including two amplifiers A1 and A2 coupled in series, four capacitors C1, C2, C3, and C4, and four MOS switches 10, 20, 30, and 40.

[0018] FIG. 3 is a timing diagram illustrating two timing waveforms 01 and 02 related to the FIG. 2, wherein the switches 10, 20, and 40 are in response to the timing waveform 01 and the switch 30 is in respond to the timing wave form 02. Note that timing waveforms 01 and 02 having the same period show different logic levels at the same time, that is, switches 10, 20, and 40 are on/off while switch 30 is off/on while the non-inverting integrator is operated.

[0019] When 01 rises to a high logic level, the input capacitor C1 whose initial voltage is Vin(nT−T/2)−Voff1 is discharged to −Voff1, where the voltage Vin is an input voltage and the voltage Voff1 is an offset voltage of the amplifier A1. On the other hand, the capacitor C2 whose initial voltage is V1(nT−3T/2)−Voff1 is charged to V1(nT−T/2)−Voff1. Thus, the charge conservation at node A gives:

[0020] C1[−Voff1−Vin(nT−T/2)+Voff1]+C2[V1(nT)−Voff1−(V1(nT−T)−Voff1)]=0   (1)

[0021] Therefore,

[0022] V1(nT−T/2)−V1(nT−3T/2)=(C1/C2)Vin(nT−T)   (2)

[0023] It is obvious that the offset voltage Voff1 in the non-inverting integrator circuit of this preferred embodiment is compensated based on the present invention.

[0024] Furthermore, when 01 rises to a high logic level, the capacitor C3 whose initial voltage is V1(nT−T/2)−Voff2 is discharged to Voff1−Voff2, where the voltage Voff2 is an offset voltage of the amplifier A2. On the other hand, the capacitor C4 is charged from zero voltage to V2(nT)−Voff2. Similarly, the charge conservation at node B gives:

[0025] C3[Voff1−Voff2−V1(nT−T/2)+voff2]+C4[V2(nT)−Voff2]=0   (3)

[0026] If the capacitance of the capacitor C3 is equal or similar to the capacitance of the capacitor C4, equation (3) can be simplified to

[0027] V2(nT)=V1(nT−T/2)+Voff2−Voff1   (4)

[0028] And if the offset voltage Voff1 of the amplifier A1 is close to the voltage Voff2 of the amplifier A2, the purpose of offset compensation can be also achieved. In addition, because all MOS switches are coupled to a ground terminal or a virtual ground terminal of the amplifiers, the non-inverting integrator circuit can be operated under a low supply voltage.

[0029] FIG. 4 is a circuit diagram illustrating an inverting integrator of another preferred embodiment of the present invention. As shown in the figure, the inverting integrator comprises two amplifiers A1 and A2 coupled in series, four capacitors C1, C2, C3, and C4, and four MOS switches 10, 20, 30, and 40 which have same symbols and function as in FIG. 2. In addition, there is a capacitor Ch to store the offset voltage Voff1 of the amplifier A1 and a switch 50 in the inverting integrator.

[0030] Similar to the non-inverting integrator shown in FIG. 2, the timing diagram having two timing waveforms 01 and 02 shown in FIG. 3 is applied to the inverting integrator shown in FIG. 4, wherein the switches 10, 30, and 50 are in response to the timing waveform 01 and the switches 20 and 40 are in response to the timing waveform 02. Note that timing waveforms 01 and 02 having the same period show different logic levels at the same time, that is, switches 10, 30, and 50 are on/off while switch 20 and 40 are off/on while the inverting integrator is operated.

[0031] By similar analysis as made in the non-inverting integrator, when 02 rises to a high logic level in the inverting integrator in FIG. 3, the charge conservation at node A′ gives :

[0032] C1Vin(nT)+C2[v1(nT)−V1(nT−T)]=0   (5)

[0033] Therefore,

[0034] V1(nT)−V1(nT−T)=−(C1/C2)Vin(nT)   (6)

[0035] On the other hand, when 01 rises to a high logic level and the capacitance of the capacitor C3 is equal to the capacitance of the capacitor C4, the charge conservation at node B′ gives:

[0036] V2(nT−T/2)=V1(nT−T)+Voff2−Voff1   (7)

[0037] If the two offset voltages Voff1 and Voff2 of the relative amplifiers A1 and A2 are close, the purpose of offset compensation can be also achieved. In addition, because all MOS switches are coupled to a ground terminal or a virtual ground terminal of the amplifiers, the inverting integrator circuit can be operated under a low supply voltage.

[0038] FIG. 5 is a circuit diagram illustrating a low-pass filter of another preferred embodiment of the present invention, which is constituted of portions of the non-inverting and inverting integrator circuits respectively shown in FIG. 2 and FIG. 4. As shown in FIG. 5., the filter circuit can also be operated under a low power voltage.

[0039] The filter circuit shown in FIG. 5 comprises three amplifiers A1, A2 and A3 coupled in series, capacitors C1-C8 and Ch, and MOS switches 311-318 and 321-326, wherein the capacitors C7 and C8 function equally as feedback resistors. Similar to the circuits shown in FIG. 2 and FIG. 3, the timing diagram shown in FIG. 3 is applied to operate the filter circuit in FIG. 5, wherein the switches 311-318 are in response to the timing waveform 01 and the switches 321-326 are in response to the timing waveform 02. Note that timing waveforms 01 and 02 having the same period show different logic levels at the same time, that is, switches 311-318 are on/off while switch 321-326 are off/on while the filter is operated.

[0040] When 01 rises to a high logic level in the filter in FIG. 5, the charge conservation gives:

[0041] V1(nT−T/2)−V1(nT−3T/2)=(C1/C2)Vin(nT−T)+{C8/C2[(Voff1−Voff2)+Vo(nT−T))]}=0   (8)

[0042] If the offset voltages Voff1 and Voff2 are close and compensate each other, a z-transformed result of the equation (8) is:

[0043] (z^−1/2−z^−3/2)V1(z)=(C1/C2)z⁻¹Vin(z)+(C8/C2)z⁻¹Vo(z)   (9)

[0044] When 02 rises to a high logic level in the filter in FIG. 5, the charge conservation gives:

[0045] V2(z)=(C3/C4)z^−1/2V1(z)+Voff3−(C3/C4)Voff1   (10)

[0046] If the offset voltages Voff1 and Voff3 are close and the capacitance of the capacitors are equal, then the offset voltages Voff1 and Voff3 are compensated and the equation (10) becomes:

[0047] V2(z)=z^−1/2V1(z)   (11)

[0048] , wherein the relation between voltages V2 and Vo is:

[0049] Vo(z)(1−z⁻¹)=−(C5/C6)V2(z)−(C7/C6)Vo(z)   (12)

[0050] By the equations (9), (11), and (12), the z-transform equation of the low-pass filter shown in FIG. 5 can be represented as:

[0051] Vo(z)/Vin(z)=−[(C5C1)/(C6C2)]z⁻¹/[1+C7/C6−(C5C8)Z⁻¹/(C6C2)+Z^−2]  (13)

[0052] In fact, according to the equation (13), the circuit shown in FIG. 5 can function as a low-pass filter while the proper ratios between the capacitance of the capacitors are determined.

[0053] FIG. 1 is a low-pass filter circuit of the prior art, which comprises three amplifiers coupled in series A11, A12, and A13, capacitors C1-C8, and switches 110-116 and 120-124, wherein there are two timing waveforms having the same period show different logic levels at the same time to operate the capacitors. To compare the low-pass filter in FIG. 5 disclosed in the present invention, both low-pass filter both have the same z-transform equation (13), but two drawbacks exist in the low-pass filter in FIG. 1 of the prior art. First, each amplifier needs to be switched. As shown in FIG. 1, the amplifiers A1, A2, and A3 are respectively switched by switches 112, 123, and 124. Moreover, the offset voltages from the amplifiers can not be compensated so as to reduce the operation precision of the low-pass filter.

[0054] Consequently, the disclosed non-inverting and inverting integrator and the low-pass filter of the present invention can not only be operated under a low power voltage, but also compensate the offset voltages created from the amplifiers, so as to increase the operation precision of the circuits.

[0055] While the present invention has been particularly shown and described with reference to a preferred embodiment, it will be readily appreciated by those of ordinary skill in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. It is intended that the claims be interpreted to cover the disclosed embodiment, those alternatives which have been discussed above and all equivalents thereto.