Method to increase contact area

[0002] 1. Field of the Invention

[0003] The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a metal-oxide-semiconductor (MOS) with an increased gate contact area.

[0004] 2. Description of the Related Art

[0005] In deep sub-micron integrated circuit technology, the line width, the contact area and the contact depth are continuously being reduced. To effectively raise the quality of a device, to decrease the resistance and to reduce the RC delay time due to a high resistance and capacitance, the fabrication of the MOS transistor tends to employ a silicide layer to reduce the contact resistance at the gate and the source/drain region. Since the fabrication of a silicide layer does not require the photolithography process, it is thus known as the self-aligned silicide process. A commonly known silicide includes titanium silicide (TiSi_x). Since titanium silicide has a low resistance and is more easily controlled during the fabrication process, titanium silicide becomes popular in the fabrication of a semiconductor device.

[0006] The conventional self-aligned silicide fabrication process includes providing a semiconductor substrate having a shallow trench structure. A polysilicon gate is formed on the substrate, wherein the gate comprises a spacer. A source/drain region is also formed in the substrate on both sides of the gate.

[0007] Thereafter, a layer of titanium is deposited on the semiconductor substrate, covering the gate and the surface of the source/drain region. A two staged rapid thermal process (RTP) is conducted for titanium to react with the silicon on the surface of the source/drain region and the gate to form a titanium silicide layer on the surface of the gate and the source/drain region. The unreacted titanium layer is then removed by wet etching to complete the self-aligned silicide manufacturing process.

[0008] The titanium silicide comprises the high resistance metastable C49 phase titanium silicide (C49-TiSi₂) and the low resistance, thermodynamically stable C54 phase titanium silicide (C54-TiSi₂). The first stage of the rapid thermal process results in the titanium silicide layer (TiSi₂) comprising a major component of the C49 phase and a minor component of the C54 phase. Thereafter, the unreacted titanium is removed. In the second stage of the rapid thermal process, the temperature is further increased to rapidly anneal in-situ, transforming the titanium silicide layer from the high resistance C49 phase titanium silicide to the low resistance C54 phase titanium silicide.

[0009] The resistance of the C49 phase titanium silicide is higher and its formation temperature is lower. On the other hand, the resistance of the C54 titanium silicide is lower and its formation temperature is higher. In general, the titanium silicide is transformed from the high resistance C49 phase to the low resistance C54 phase via a rapid thermal process. In order for the metal layer and silicon to react to form a silicide layer with a substantial thickness and a more uniform quality, it is necessary to increase the temperature and the duration for the thermal process

[0010] Along with the size reduction of the polysilicon gate, the formation temperature for the C54 phase titanium silicide is increased due to the narrow line effect. The narrow line effect refers to the relationship between the linewidth and the phase transformation temperature. As the linewidth decreases, the phase transformation temperature for the titanium silicide to transform from the high resistance C49 phase to the low resistance C54 phase increases. As the temperature for the RTP process is increased to form the C54 titanium silicide, the quality of the titanium silicide becomes unstable and is not suitable for use in a small-dimension device. In addition, the higher reaction temperature is difficult to control, and lateral growth of silicon from the source/drain region to the spacer is likely to occur. As a result, as the device integration increases and the device dimension decreases, bridging is likely to occur on the side of the gate. To avoid the occurrence of bridging, the reaction temperature cannot be raised. Consequently, a higher resistance results at the polysilicon gate due to the narrow line effect and the difficulty of phase transformation.

[0011] Based on the foregoing, the present invention provides a method to increase the gate contact area, wherein a side-wing layer is formed on both sides of the gate to increase the area for a silicide formation and to lower the gate contact resistance. The narrow line effect is thus prevented. An air spacer is further formed under the side-wing layer to reduce the parasitic capacitance between the gate and the source/drain region

[0012] The current invention provides a fabrication method for a semiconductor device in which the gate contact area is increased. The method is applicable on a substrate comprising isolation structures. The method includes forming a gate structure on the silicon substrate. A conformal sacrificial layer is formed on the silicon substrate and on the gate structure. A light doping is conducted to form a lightly doped source/drain region at both sides of the gate in the silicon substrate. A first spacer is then formed on the sidewall of the gate structure. A heavy doping is further performed on both sides of the gate structure in the substrate, using the spacer as mask, to form the heavily doped source/drain region. Thereafter, a second sacrificial layer is formed covering the silicon substrate, followed by partially removing the second sacrificial layer, the first spacer and the first sacrificial layer until the surface of the second sacrificial layer is lower than the top of the gate by a certain thickness. A conformal polysilicon layer is then formed, covering the silicon substrate. After this, a second spacer is formed on the sidewall of the gate on the conformal polysilicon layer. The portion of the polysilicon layer that is not covered by the second spacer is removed to from a sidewing polysilicon layer at both sides of the gate. The second spacer, the second sacrificial layer, the first spacer and the first sacrificial layer are removed. Subsequently, a metal salicidation process is conducted on the gate, the side-wing polysilicon layer and the surface of the source/drain region to form a silicide layer. An insulation layer is then formed on the silicon substrate covering the side-wing polysilicon layer. An air spacer is thus formed under the polysilicon side-wing layer.

[0013] The present invention provides a fabrication method for a semiconductor device, in which a side-wing layer is formed on both sides of the gate to increase the gate area for silicidation and to avoid the narrow line effect. In addition, an air spacer is formed under the side-wing layer to reduce the parasitic capacitance between the gate and the source/drain region.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0015] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0016] FIGS. 1A to 1I are schematic, cross-sectional views showing the manufacturing of a metal-oxide-semiconductor device according to the preferred embodiment of the present invention.

[0017] The present invention provides a fabrication method to increase the gate contact area. The present invention also provides a fabrication method for a MOS device in which the method to increase the gate contact is incorporated. In the preferred embodiment, the fabrication of a MOS device is disclosed to illustrate in detail the fabrication method for increasing the gate contact area according to the present invention.

[0018] Referring to FIG. 1A, a silicon substrate 100 comprising isolation structures 102, for example, shallow trench isolation structures, is provided. A gate 108, comprising a gate oxide layer 104 and a polysilicon layer 106, is formed on the substrate 100, wherein the gate structure 108 is about 3000 Å high. The technique for forming the gate 108 is familiar to persons skilled in the art and will not be re-iterated in the preferred embodiment of the present invention.

[0019] A conformal sacrificial layer 110 is formed on the silicon substrate 100 and covering the gate structure 108. The sacrificial layer 110, such as silicon nitride, is formed by, for example, low pressure chemical vapor deposition, to a thickness of about 200 angstroms. The sacrificial layer 110 on the isolation structures 102 protects the device isolation structures 102 from being damaged during the subsequent etching process.

[0020] Continuing to FIG. 1B, an ion implantation is conducted to form a lightly doped source/drain region 112 at both sides of the gate structure 108 in the substrate 100. After this, a spacer 114, about 500 angstroms wide, is formed on the sidewall of the gate structure 108. The spacer 114, such as silicon oxide, is formed by conventional deposition and etching methods. Another ion implantation is conducted at both sides of the gate structure 108 to form a heavily doped source/drain region 116 in the substrate 100 using the spacer 114 as a mask. The lightly doped source/drain region 112 and the heavily doped source/drain region 116 together form the source/drain region 118.

[0021] As shown in FIG. 1C, another sacrificial layer 120 is formed by, for example chemical vapor deposition, on the silicon substrate 100, covering the spacer 114 and the sacrificial layer 110. The sacrificial layer 120, such as silicon oxide is planarized by chemical mechanical polishing (CMP) until the sacrificial layer 110 on the top surface of the gate structure 108 is exposed.

[0022] Referring to FIG. 1D, portions of the sacrificial layer 120, the spacer 114, the sacrificial layer 110 are removed until the surface 152 of the sacrificial layer 120 (FIG. 1C) is lower than the top surface 108 of the polysilicon gate 154 by a thickness of “d”, which is about 1500 angstroms, to form the sacrificial layer 120a, the spacer 114aand the sacrificial layer 110a. If the sacrificial layer 120 (FIG. 1C) and the spacer 114 (FIG. 1C) are silicon oxide and the sacrificial layer 110 (FIG. 1C) is silicon nitride, a buffer oxide etchant (BOE) and phosphoric acid (H₃PO₄) are used to etch the sacrificial layer 120, the spacer 114, and the sacrificial layer 110, respectively, to the desired heights.

[0023] Referring to FIG. 1E, a conformal polysilicon layer 122 is then formed, covering the substrate 100, the spacer 114a, the sacrificial layer 120 and the gate 108. It is preferable that the polysilicon layer 122 is a doped polysilicon layer, and the polysilicon layer 122 is formed by, for example, chemical vapor deposition, and is about 300 to 500 angstroms thick. Another spacer 124 is then formed by the sidewall of the gate structure 108 on the polysilicon layer 122 above the spacer 114a. The spacer 124 such as silicon oxide, is formed by, for example, forming a silicon oxide layer on the silicon substrate, followed by back etching the spacer 124. The spacer 124 is about 300 angstroms to about 800 angstroms wide.

[0024] Referring to FIG. 1F, using the spacer 124 as a mask, the exposed polysilicon layer 122 is removed by, for example dry etching, to form a side-wing polysilicon layer 122aon both sides of the gate structure 108. With the formation of the side-wing polysilicon layer 122aon both sides of the gate structure 108, the gate contact area is increased. During the subsequent formation of a silicide, as a result, the narrow line effect is mitigated to effectively lower the gate contact resistance.

[0025] Continuing to FIG. 1G, the spacer 124 (FIG. 1F), the sacrificial layer 120a(FIG. 1F), the spacer 114aare removed using, for example, a buffer oxide etchant (BOE), followed by removing the sacrificial layer 110awith phosphoric acid (H₃PO₄).

[0026] As shown in FIG. 1H, a silicidation process is conducted to form a silicide layer 132 on the top surface of the gate 108 and the side-wing polysilicon layer 122a, and to form a silicide layer 130 on the surface of the heavily doped source/drain region 116. The silicide layers 130 and 132 are, for example, titanium silicide or cobalt silicide. Using the titanium silicide as an example, the titanium silicide layers 130, 132 are formed by depositing silicon on the silicon substrate 100, covering the gate 108 and the surface of the heavily doped source/drain region 116. A rapid thermal process is conducted to form a titanium silicide layer only, in principle, where the titanium is in contact with silicon. A wet etching is further conducted to remove the unreacted metal. Another rapid thermal process is conducted to form the low resistance C54 phase titanium silicide.

[0027] Referring to FIG. 11, an insulation layer 134 is formed on the silicon substrate 100, covering the silicide layers 130 and 132. The insulation layer 134, such as sputtered oxide, is formed by reactive sputtering deposition. By using the anisotropic deposition characteristic of sputtering, an air spacer 136 is formed under the side-wing polysilicon layer 122a. Since the dielectric constant of air is very low, about 1, the formation of the air spacer 136 can lower the parasitic capacitance between the gate 108 and source/drain region to prevent the RC time delay.

[0028] Based on the preferred embodiment of the present invention, the present invention comprises at least the following advantages. The formation of the side-wing layer on both sides of the gate 108 increases the area of the gate 108 for silicidation. The narrow line effect is, therefore, prevented. Furthermore, an air spacer 136 is formed under the side-wing layer to lower the parasitic capacitance between the gate 108 and source/drain region 118.

[0029] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.