Clock Reproduction Circuit That Can Reproduce Internal Clock Signal Correctly in Synchronization With External Clock Signal

1. A synchronous semiconductor integrated circuit device comprising: a clock generation circuit receiving a base clock signal and generating an internal clock signal in synchronization with the base clock signal; a clock power supply circuit coupled to said clock generation circuit, for supplying an operating power supply voltage to said clock generation circuit; an internal power supply, separate from said clock power supply circuit, for generating a power supply voltage; and internal circuitry for carrying out a function, said internal circuitry including a peripheral circuit, receiving the power supply voltage from said internal power supply circuit as an operating power supply voltages for operating in synchronization with the internal clock signal.

2. The synchronous semiconductor integrated circuit device according to claim 1, further comprising: an initialization signal generation circuit for rendering an initialization signal active in response to activation of a clock enable signal activating said clock generation circuit; and a delay circuit for delaying said initialization signal, wherein said clock power supply circuit includes a circuit rendered active in response to activation of the clock enable signal for generating the operating power supply voltage for said clock generation circuit, and said clock generation circuit is initialized in response to the initialization signal and rendered active in response to activation of the clock enable signal and to activation of an output signal from said delay circuit to generate the internal clock signal.

3. The synchronous semiconductor integrated circuit device according to claim 1, wherein said clock generation circuit comprises a synchronization circuit for establishing synchronization between the base clock signal and the internal clock signal, and a buffer circuit group including a buffer circuit for applying a signal to said synchronization circuit and a buffer circuit for transferring a signal from said synchronization circuit, wherein said synchronization circuit receives the power supply voltage from said clock power supply circuit as an operating power supply voltage, and said buffer circuit group receives the power supply voltage from said internal power supply circuit as an operating power supply voltage.

4. The synchronous semiconductor integrated circuit device according to claim 1, further comprising an initialization signal generation circuit generating an initialization signal in response to rise of the operating power supply voltage from said clock power supply circuit, wherein said clock generation circuit is reset to an initial state in response to the initialization signal.

5. The synchronous semiconductor integrated circuit device according to claim 4 further comprising a delay circuit for delaying the initialization signal, wherein said clock generation circuit is rendered active in response to activation of an output signal of said delay circuit and activation of a clock enable signal to generate the internal clock signal.

6. The synchronous semiconductor integrated circuit device according to claim 1, wherein said clock generation circuit comprises: a frequency determination circuit receiving the power supply voltage from said clock power supply circuit as an operating power supply voltage to generate a coarse adjust clock signal approximating in at least one of frequency and phase the base clock signal, and a fine adjust circuit receiving the power supply voltage from said clock power supply circuit as an operating power supply voltage, and receiving the coarse adjust clock signal from said frequency determination circuit to adjust phase of the coarse adjust clock signal according to comparison between the base clock signal and the internal clock signal, for generating a fine adjust clock signal synchronized with the base clock signal for output as the internal clock signal.

7. The synchronous semiconductor integrated circuit device according to claim 6, wherein said fine adjust circuit is located at a midpoint between a circuit that operates in synchronization with said internal clock signal and said frequency determination circuit, so that a signal propagation delay time between said fine adjust circuit and said internal circuit is substantially equal to a signal propagation delay time between said frequency determination circuit and said fine adjust circuit.

8. The synchronous semiconductor integrated circuit device according to claim 6, further comprising a circuit for making a determination of completion of phase adjustment by phase comparison between the base clock signal and the internal clock signal to render said fine adjust circuit active according to the determination.

9. The synchronous semiconductor integrated circuit device according to claim 1, wherein said clock generation circuit is rendered active in response to activation of a clock enable signal to generate the internal clock signal, and the clock power supply circuit generates the operating power supply voltage for said clock generation circuit in response to activation of said clock enable signal.

10. The synchronous semiconductor integrated circuit device according to claim 9, further comprising a circuit responsive to inactivation of the clock enable signal for setting a substrate bias of an insulated gate field effect transistor of said clock generation circuit a reversed bias state.

11. The synchronous semiconductor integrated circuit device according to claim 9, wherein said clock generation circuit comprises: a phase difference retain circuit for detecting a phase difference between the base clock signal and the internal clock signal to retain the phase difference as a multi-bit binary value, a current decoder for generating a current flow according to the multi-bit binary value of said phase difference retain circuit, and an oscillator having an operating power supply current determined by the current flow from said current decoder for oscillation to generate a signal corresponding to the internal clock signal, wherein said synchronous integrated circuit device further comprises an auxiliary store circuit for receiving and storing the multi-bit binary value retained in said phase difference retain circuit in response to inactivation of the clock enable signal, and for transferring to said phase difference retain circuit the stored multi-bit binary value in response to activation of the clock enable signal, said auxiliary store circuit receiving the power supply voltage from said internal power supply circuit as an operating power supply voltage.

12. The synchronous semiconductor integrated circuit device according to claim 11, wherein said auxiliary store circuit includes as a component a first insulated gate field effect transistor having a threshold voltage, and said clock generation circuit includes as a component a second insulated gate field effect transistor having a threshold voltage smaller in absolute value than the threshold voltage of said first insulated gate field effect transistor.

13. The synchronous semiconductor integrated circuit device according to claim 1, wherein said clock generation circuit comprises: a clock input buffer buffering an external clock signal, the base clock signal, and generating a reference clock signal, a first dummy delay buffer for delaying the reference clock signal from said clock input buffer, a first delay circuit including a plurality of cascaded delay stages, for delaying an output signal of said first dummy delay buffer, a gate circuit responsive to a sampling signal for passing the reference clock signal to generate a sample clock signal, a tap circuit for selecting a clock signal output from a particular delay stage of said first delay circuit according to a comparison between the sample clock signal from said gate circuit and a clock signal output from each delay stage of said first delay circuit, a second delay circuit for delaying an output signal of said tap circuit, a second dummy delay buffer for receiving and buffering a clock signal output from said second delay circuit, a third delay circuit for delaying an output signal from said second dummy delay buffer, said third delay circuit including a plurality of cascaded delay stages, a maximum delay time of said third delay circuit corresponding to a delay time of one delay stage of said first delay circuit, a clock tree receiving an output signal from said third delay circuit to distribute the output signal as the internal clock signal to said internal circuitry, a phase difference detection circuit for detecting a difference in phase between the internal clock signal output from said clock tree and the reference clock signal, a fine tap set circuit for setting a delay time of said third delay circuit according to an output signal of said phase difference detection circuit, and a tap determination circuit for generating a tap adjust signal when the delay time set by said fine tap set circuit provides a transition between the maximum delay time and a minimum delay time of said third delay circuit, wherein said tap circuit comprises a circuit for shifting a selected delay stage in said first delay circuit by one stage in response to the tap adjust signal.

14. The synchronous semiconductor integrated circuit device according to claim 13, wherein the second and third delay circuits and said clock tree are arranged so that a signal propagation delay time from an output portion of said second delay circuit to an input portion of said third delay circuit is equal to a signal propagation delay time from an output portion of said third delay circuit to an output portion of said clock tree.

15. The synchronous semiconductor integrated circuit device according to claim 13, further comprising a third dummy delay buffer having a gate delay time identical to a gate delay time of said first dummy delay buffer, and provided at an output portion of said third delay circuit to buffer an output signal from said third delay circuit for application to said clock tree.

16. The synchronous semiconductor integrated circuit device according to claim 13, wherein said fine tap set circuit comprises a bi-directional shift register including stages identical in number with said delay stages of said third delay circuit, and a shift operation of said bi-directional shift register is controlled by an output signal from said phase difference detection circuit, and a delay stage of said third delay circuit is selected by an output signal of each stage of said bi-directional shift register.

17. The synchronous semiconductor integrated circuit device according to claim 13, further comprising: a circuit for making a determination of completion of phase adjustment by phase comparison between the reference clock signal and the internal clock signal to render said fine adjust circuit active according to the determination; and a circuit responsive to activation of a signal indicating the phase adjustment completion determination for maintaining the sampling signal in an inactive state.

18. The synchronous semiconductor integrated circuit device according to claim 13, wherein said first, second, third delay circuits, said tap circuit, said phase difference detection circuit and said tap determination circuit operate receiving the power supply voltage from said clock power supply circuit as an operating power supply voltage, and said clock input buffer, said first and second dummy delay circuits and said clock tree receive the power supply voltage from said internal power supply circuit as an operating power supply voltage.

19. The synchronous semiconductor integrated circuit device according to claim 18, wherein the first and second dummy delay buffers and said clock tree are rendered inactive when a clock enable signal designating generation of the internal clock signal is inactive, and said clock power supply circuit is rendered inactive when the clock enable signal is inactive, to stop generation of said power supply voltage.

20. The synchronous semiconductor integrated circuit device according to claim 13, further comprising a replica buffer having a gate delay time identical to a gate delay time of said first dummy delay buffer, for buffering the internal clock signal from said clock tree for transmission to said phase difference detection circuit, wherein a signal propagation delay time from an output portion of said clock tree up to an input portion of said phase difference detection circuit via said replica buffer is equal to a signal propagation delay time from an output portion of said clock input buffer up to an input portion of said phase difference detection circuit.

21. The synchronous semiconductor integrated circuit device according to claim 20, wherein said replica buffer receives the power supply voltage from said internal power supply circuit as an operating power supply voltage.

22. The synchronous semiconductor integrated circuit device according to claim 21, wherein said replica buffer, said first and second dummy delay buffers, and said clock tree are rendered inactive in response to inactivation of a clock enable signal designating generation of the internal clock signal, and said clock power supply circuit is rendered inactive in response to inactivation of the clock enable signal.

23. A synchronous semiconductor integrated circuit device comprising: a clock generation circuit for generating an internal clock signal in synchronization with a base clock signal, said clock generation circuit comprising: (i) a coarse adjust circuit including a plurality of cascaded first delay elements for delaying the base clock signal, for comparison of output signals of said plurality of first delay elements with a reference clock signal corresponding to the base clock signal to generate a coarse clock signal at a first precision according to the comparison, and (ii) a fine adjust circuit including a plurality of cascaded second delay elements, for comparison of the reference clock signal with the internal clock signal to adjust phase of the coarse adjust clock signal at a second precision, finer than the first precision, according to the comparison, a maximum variable delay time of said plurality of second delay elements corresponding to a delay time of one stage of said first delay elements, said fine adjust circuit including a circuit for shifting phase of the coarse adjust clock signal of said coarse adjust circuit by one stage of said first delay elements when a phase adjust exceeds a processing range of said plurality of second delay elements; and an internal circuit carrying out a predetermined operation in synchronization with the internal clock signal.

24. The synchronous semiconductor integrated circuit device according to claim 23, wherein said coarse adjust circuit comprises: a first clock input buffer responsive to activation of a clock enable signal for transmitting a first reference clock signal to a train of said plurality of first delay elements, and rendered inactive from a next cycle onward, and a second clock input buffer responsive to activation of the clock enable signal for receiving the first reference clock signal and a second reference clock signal for the phase comparison, and rendered inactive thereafter, wherein said fine adjust circuit comprises a circuit rendered active at a clock cycle of the reference clock signal after an output signal of said coarse adjust circuit is stabilized to receive the reference clock signal and the internal clock signal for phase comparison.

25. The synchronous semiconductor integrated circuit device according to claim 23, wherein said coarse adjust circuit comprises: a circuit for detecting completion of coarse adjustment of said coarse adjust circuit, and a circuit for stopping the coarse adjustment to generation a clock signal in synchronization with the reference clock signal in the coarse adjustment when completion of coarse adjustment is detected, a fine adjust operation of said fine adjust circuit being rendered active in response to a signal indicating detection of completion of the coarse adjustment.

26. The synchronous semiconductor integrated circuit device according to claim 23, wherein said fine adjust circuit is located at an intermediate position between an output portion of said coarse adjust circuit and said internal circuit.

27. The synchronous semiconductor integrated circuit device according to claim 23, wherein said coarse adjust circuit includes a delay monitor for compensating for a difference in signal propagation delay between the internal clock signal and the base clock signal.

28. The synchronous semiconductor integrated circuit device according to claim 27, wherein said delay monitor comprises a delay stage providing a delay time equal to an initialized delay time of said coarse adjust circuit and said fine adjust circuit.

29. The synchronous semiconductor integrated circuit device according to claim 23, further comprising: an internal circuit power supply circuit for supplying an operating power supply voltage to said internal circuit; and a clock power supply circuit separate from said internal circuit power supply circuit for supplying an operating power supply voltage to said clock generation circuit.

30. The synchronous semiconductor integrated circuit device according to claim 29, wherein said clock generation circuit is rendered active when a clock enable signal is active, to generate the internal clock signal, and said clock power supply circuit is rendered active, in response to activation of the clock enable signal to generate the operating power supply voltage to said clock generation circuit.

31. The synchronous semiconductor integrated circuit device according to claim 23, wherein said fine adjust circuit comprises: a fine adjust circuit including said plurality of second delay elements, for receiving the coarse adjust clock signal to generate the internal clock signal, a phase comparison circuit for comparison of phases of the reference clock signal and the internal clock signal, and a delay set circuit for adjusting a delay time of said fine adjust delay circuit according to the comparison of said phase comparison circuit, said delay set circuit including a circuit for shifting by one stage the delay of said first delay elements of said coarse adjust circuit when a phase difference detected by said phase comparison circuit exceeds an adjustable range of said fine adjust delay circuit.

32. The synchronous semiconductor integrated circuit device according to claim 31, wherein said delay set circuit comprises a fine adjust bi-directional shift register responsive to a phase lead/lag designating signal from said phase comparison circuit for shifting an output signal thereof bi-directionally, and a coarse adjust bi-directional shift register responsive to transition of an active output signal of said fine adjust bi-directional shift register between a last stage register and a first stage register in said fine adjust bi-directional shift register for shifting an output signal thereof, wherein a delay time of said fine adjust circuit is set according to an output signal of said fine adjust bi-directional shift register, and a delay time of said coarse adjust delay circuit is adjusted according to an output signal of said coarse adjust bi-directional shift register.

33. The synchronous semiconductor integrated circuit device according to claim 31, wherein said fine adjust delay circuit comprises an inverter having an operating current adjusted stepwise according to an output signal of said delay set circuit.

34. The synchronous semiconductor integrated circuit device according to claim 31, wherein said fine adjust delay circuit comprises a first inverter having an operating current varied stepwise over m stages, and a second inverter coupled in series to said first inverter, and having an operating current varied stepwise over m stages.

35. The synchronous semiconductor integrated circuit device according to claim 31, wherein a phase comparison between the internal clock signal and the reference clock signal and a delay time setting by said delay set circuit are carried out at alternate cycles of the reference clock signal.

36. The synchronous semiconductor integrated circuit device according to claim 31, wherein said phase comparison circuit comprises: a first delay circuit for delaying the reference clock signal, second and third delay circuits, each of said second and third delay circuits for delaying the internal clock signal, a first flip-flop receiving output signals of said first and second delay circuits, a second flip-flop receiving output signals of the first and third delay circuits, and latch circuits for latching respective output signals of said first and second flip-flops, wherein each of said first, second, and third delay circuits includes a delay stage having a delay time equal to the delay time of one stage of said first delay element of said coarse adjust circuit.

37. The synchronous semiconductor integrated circuit device according to claim 36, wherein each of said latch circuits includes a first gate, a first latch delay element receiving an output signal of said first gate, a second gate, and a second latch delay element receiving an output signal of said second gate, said first gate receiving an output signal of said second latch delay element and a first output signal of a corresponding one of said flip flops, said second gate receiving an output signal of said first latch delay element and a second output signal of said corresponding one of said flip flops.