Linearization Technique for Analog to Digital Converters

The present invention is related to a linearization technique for analog to digital converters (ADC).

The limited ability to implement an amplifier with gain exactly equal to 2.sup.M, where M is an integer number, limits the achievable linearity of algorithmic and pipelined analog-to-digital converters. Such amplifiers with accurate gain are typically implemented as switched capacitor amplifiers. A switched capacitor amplifier with gain equal to two (X2 amplifier) is shown in FIG. 5. The circuit operates in two phases (FIGS. 1 and 2). In the first phase (sampling phase) the switches labelled .phi..sub.1 are closed connecting the input signal to C.sub.F (feedback capacitor) and C.sub.S (sampling capacitor) as shown schematically in FIG. 1. At the end of the phase the capacitors are disconnected leaving the input voltage stored on each capacitor. In the second phase (amplification phase) the switches labelled .phi..sub.2 are closed as shown schematically in FIG. 2. All charge stored on C.sub.S will be transferred to C.sub.F resulting in the transfer function shown in equation (1) if an infinite operational amplifier open-loop gain is assumed.

The gain becomes exactly equal to 2 if C.sub.S and C.sub.F are exactly equal. The accuracy of the gain is limited by the capacitor matching that can be obtained with current technology. During one clock cycle, the sampling phase is performed before an amplification phase. For normal operation in a high-speed ADC, the X2 amplifier therefor will alternate between the sampling phase and the hold phase.

Several principles have been proposed to enhance the performance of the X2 amplifier. The mismatch problem is known to be solved by using the same capacitor both for sampling and feedback. This is accomplished by sampling the input twice and transferring the charge back and forth from an extra capacitor. Four operational amplifier (op amp) settling-time periods are required in this solution, and the obtainable conversion rate would therefore be reduced by at least a factor of two.

In FIG. 6 the same configuration as in FIG. 5 is used, except that the circuit is connected so that both C.sub.S and C.sub.F can be used as feedback capacitor. If the capacitances of C.sub.S and C.sub.F are different by a certain percentage, the gain will become higher than two or lower than 2 depending on which of the capacitors is selected as feedback capacitor, cf. equation 1. It is known from prior art to use the value of the input signal V.sub.in, to determine if C.sub.S or C.sub.F should be used as feedback capacitor. When this configuration is used in a so-called pipeline ADC, having several amplifiers, their gain is dependent on the input voltage, hence harmonic distortion in the system results. Therefore this approach cannot improve the distortion of the ADC, measured by the parameters SFDR (spurious free dynamic range), THD (total harmonic distortion) for full scale input signals. The DNL (differential nonlinearity) of the converter is improved.

Substantial improvements are achieved with the linearization technique according to the present invention as defined by the features of the claims.

FIG. 1 discloses schematically gain-of-2 amplifiers with C.sub.F =C.sub.S in the sampling phase, FIG. 2 corresponds with FIG. 1, however in the amplification phase, FIG. 1 again discloses schematically gain-of-2 amplifiers with C.sub.F =C.sub.S and linearization technique in the sampling phase, FIG. 3 corresponds with FIG. 1, however in the amplification phase, FIG. 4 discloses gain-of-2 amplifiers and C.sub.F =C.sub.S where C.sub.F and C.sub.S is divided into N=2 unity capacitors in the sampling phase, FIG. 5 discloses a switched capacitor implementation of gain-of-2 amplifier and FIG. 6 discloses a gain-of-2 amplifier with feedback capacitor selected by D.sub.S.

FIG. 1 depicts an amplifier with C.sub.F =C.sub.S in the sampling phase;

FIG. 2 depicts an amplifier in the amplification phase;

FIG. 3 depicts an amplifier in the amplification phase;

FIG. 4 depicts an amplifier with C.sub.F =C.sub.S and where C.sub.F and C.sub.S are divided into N=2 unity capacitors in the sampling phase;

FIG. 5 depicts a switch capacitor amplifier; and

FIG. 6 depicts an amplifier with feedback capacitor selected by D.sub.S.

The ADC linearization technique according to the present invention can be employed in the X2 amplifier as shown schematically in FIGS. 1, 3 and 6. A in FIG. 3 corresponds with C.sub.F with a digital signal, D.sub.S equal to zero and with C.sub.S if D.sub.S is equal to one. Correspondingly B in FIG. 3 corresponds with C.sub.S if D.sub.S is equal to zero and with C.sub.F if D.sub.S is equal to one. Appropriate control means 10 uses the state of the digital signal D.sub.S, generated by a pseudo random binary number generator (PRNG) 12, to determine if C.sub.S or C.sub.F is used as feedback capacitor, so that the choice between C.sub.S and C.sub.F is determined for each clock cycle 14. During normal operation the circuit will alternate between the sampling phase and the amplification phase. Before each amplification phase, the PRNG 12 selects a random value (O or 1) for D.sub.S, which determines if C.sub.S or C.sub.F is used as feedback capacitor. FIG. 6 shows a possible implementation of a circuit with control means 10 selecting feedback capacitor determined by a D.sub.S input signal. The PRNG output signal must have no correlation to the input signal, V.sub.in, and it must be symmetrical. In this context symmetrical means that during a certain number of clock cycles 14, the number of times C.sub.S and C.sub.F are used as feedback capacitor must be equal. The output of the PRNG 12 may be "white" (fully random) or it may have given spectral properties depending on the application. If C.sub.F and C.sub.S are different by a given percentage, the gain will be higher than 2 and lower than 2 for the same number of clock cycles 14 (see equation 1). The linearization technique therefore significantly reduces the average gain error. Since the PRNG output is uncorrelated to the input signal, the systematic gain error caused by capacitor mismatch is eliminated and replaced by noise having a frequency characteristic independent of the input signal.

The invention is used in systems where the distortion performance is limited by component matching limitations. Examples of such systems are analog-to-digital and digital-to-analog converters. The operation of such circuits is based on the following principle. Several sets of components where the sum of the component values in each set are a multiple of (or equal to) the sum of the values in the other sets are used to implement a given transfer function. The accuracy of the transfer function is limited by the matching of the component values. Examples of such systems are found in prior art.

The invention is based upon this linearization technique and gives practical solutions to linearity problems by improving the performance of such systems in the following way. The components in the matched sets are interchanged between the sets as a function of time and in a manner that is uncorrelated with the input signal and the state of the system clock (eg. random component interchange). The component interchange must be performed so that the time average of the sum of the component values in each set are matched exactly to each other. The linearization technique then eliminates signal dependent errors and replaces these errors with a noise with no correlation to the input signal.

The scheme can be extended by splitting C.sub.S into N equal size capacitors and C.sub.F into N equal size capacitors, resulting in a capacitor array with 2N capacitors (see FIGS. 4 and 3). In the sampling phase the input signal is sampled onto all 2N capacitors in parallel. In the amplification phase, N capacitors selected by the digital signal Ds are connected in the feedback path of the operational amplifier.

The linearity averaged over many A/D-conversions of a pipelined ADC based on the known circuit in FIG. 1 can be improved by the linearization technique. Capacitor mismatch in a pipeline ADC increases the linearity error of the converter due to gain errors. This results in harmonic distortion. The linearization technique therefore randomizes the error and distributes the energy of the harmonic components over the entire sampled frequency spectrum if the digital signal Ds is random and uncorrelated with the input signal. In this way harmonic errors are eliminated and converted to signal independent white noise. This results in a significant improvement in SFDR and THD at the expense of a slight reduction in SNR.

The linearization technique can also be adapted to other circuit topologies whose function is based on matching of any electronic component.