Digital-to-Analog Converter in Which an Analog Output of Low Order Bits Is Attenuated, and Added to an Analog Output of High Order Bits

The present invention relates to a digital-to-analog converter.

FIG. 6 is a view showing the structure of a conventional digital-to-analog converter. The converter divides input digital data of N bits into M high order bits and (N-M) low order bits. The M high order bits are input to a digital-to-analog converter 12 for high order bits, and the (N-M) low order bits are input to a digital-to-analog converter 20 for low order bits. The digital-to-analog converter 12 for high order bits comprises: a string of 2.sup.M resistors 3 to 8 (resistor string) for high order bits, which are unit resistors Rm series-connected to each other between a first reference voltage VR1 (10) and a second reference voltage VR2 (11); 2.sup.M switch circuits 2 each of which is designed to select one of divided voltages which are obtained by dividing the voltage between the first reference voltage VR1 (10) and the second reference voltage VR2 (11) by means of a respective one of the 2.sup.M resistors 3 to 8; and a decoder 1 for outputting a selection signal for selecting one of the 2.sup.M switches 2 which corresponds to the input M-bit digital data. A resistor element Rc 9 is a resistor element for adjustment.

The digital-to-analog converter 20 for low order bits comprises: a string of 2.sup.(N-M) resistors 15 to 19 for low order bits which are unit resistors Rs connected in parallel with both the ends of the unit resistor Rm (8), and which are series-connected to each other; 2.sup.(N-M) switch circuits 14 each of which is designed to select one of divided voltages which are obtained by dividing the voltage between the first reference voltage VR1 (10) and the second reference voltage VR2 (11) by means of a respective one of the 2.sup.(N-M) resistors 15 to 19; and a decoder 13 for outputting a selection signal for selecting one of the 2.sup.(N-M) switches 14 which corresponds to the input (N-M)-bit digital data.

In the conventional digital-to-analog converter having the above structure, the digital-to-analog converter 12 outputs an analog output having an M-bit resolution, and the digital-to-analog converter 20 outputs an analog output having an (N-M)-bit resolution.

Those analog outputs are added by an analog adder 21, thereby obtaining an analog output having an N-bit resolution between the first reference voltage VR1 (10) and the second reference voltage VR2 (11).

By virtue of the above structure, in order to obtain an analog output having an N-bit resolution, the number of unit resistors and that of switch circuits can be reduced greatly, as compared with the case where an analog output having an N-bit resolution is obtained with one digital-to-analog converter. Accordingly, the above conventional digital-to-analog converter can be easily incorporated into a chip and manufactured at a low cost.

More specifically, in order to obtain an analog output having a 12-bit resolution, for example, the above conventional digital-to-analog converter differs from a circuit using only one digital-to-analog converter as follows:

The circuit using only one digital-to-analog converter needs 4096 (2.sup.12) unit resistors and 4096 switch circuits respectively associated with the unit resistors. On the other hand, the aforementioned conventional digital-to-analog converter has only 128 (2.sup.6 .times.2) unit resistors (64 units resistors for high order bits plus 64 units resistors for low order bit) plus 128 switch circuits respectively associated with the unit resistors, if the input data is divided into 6 high order bits and 6 low order bits.

In such a manner, when the input data is divided into two, i.e., high order bits and low order bits, or three, the number of structural elements provided in the circuit is far smaller than that of structural elements of the circuit having one digital-to-analog converter. However, the above conventional digital-to-analog converter has the following disadvantages:

First, the analog output of the conventional digital-to-analog converter has bad linearity.

The linearity of the analog output is important for a resistor string type of digital-to-analog converter (which uses a string of resistors). It is influenced by the variance in resistance value among the unit resistors if the circuit has only digital-to-analog converter. In contrast, the conventional digital-to-analog converter which divides the input data into two further error factors worsening the linearity function, in addition to the variance in resistance value among the unit resistors. To be more specific, one of the unit resistors Rm for high order bits, which is connected in parallel with the resistor string for low order bits, is lower in resistance value than each of the other unit resistors Rm for high order bits. Due to this, the resistor Rc for adjustment is connected in series to said one of the unit resistors Rm. Its resistance needs to be adjusted such that the total resistance of said one of the unit resistors Rm, the resistor Rc for adjustment and the resistor string for low order bits is equal to the resistance of each of the other unit resistors Rm for high order bits.

Furthermore, in the conventional digital-to-analog converter, the linearity is greatly influenced by the resistances of the resistor Rc for adjustment and the resistor Rm connected in parallel with the resistor string for low order bits. This will be explained in detail as follows:

FIGS. 5A and 5B show conversion characteristics of the conventional digital-to-analog converter.

As shown in FIG. 5A, ideal digital-to-analog conversion characteristics represented by a line 62 in FIG. 5A cannot be obtained, and an error voltage Verror is generated at the turn from conversion of high order bits to conversion of low order bits, as shown in a two-dot chain line 63, when the total resistance of the resistor Rc and the unit resistor Rm for high order bits connected in parallel with the resistor string for low order bits is smaller than each of the other resistors Rm for high order bits.

Also, when the above total resistance is greater than each of the other resistors Rm for high order bits, ideal digital-to-analog conversion characteristics represented by a line 65 cannot be obtained, and an error voltage Verror represented by a two-dot chain line 64 is generated, thus losing the linearity.

Such a disadvantage gives rise to a problem in the case where the digital-to-analog converter is incorporated into an LSI chip or the like. In the case of doing so, in order resistors be formed to have the same resistance, they are formed to have the same shape, although they are formed in different manufacturing processes. As a result, their relative resistance values do not vary, even if their absolute resistance values vary. However, in the conventional digital-to-analog converter, it is difficult to reduce the variance in relative resistance values among the unit resistors Rm, since the resistor Rc for adjustment is needed for the unit resistor Rm for high order bits connected in parallel with the resistor string for low order bits.

In such a manner, in the conventional digital-to-analog converter, the variance in relative resistance value is hard to reduce. Thus, the converter cannot maintain the linearity of the analog output, although the number of the unit resistors and that of the switch circuits can be reduced greatly.

Furthermore, in order for digital-to-analog conversion to be performed with a high precision, the conventional digital-to-analog converter requires adjustment by trimming or the like after it is manufactured, which is troublesome.

In addition, the operating speed of a resistor string type of digital to analog converter depends on the output impedance of the resistor string. Thus, the operating speed of the conventional digital to analog converter of a resistor string type is limited due to the output impedance of the resistor string for low order bits, since the output impedance of the resistor string for low order bits is higher than that of the resistor string for high order bits. The output impedance of the resistor string for low order bits cannot be easily decreased from the standpoint of structure. In this point, the conventional digital-to-analog converter cannot be designed to operate at a higher speed.

In view of the forgoing, the first object of the present invention is to provide a digital-to-analog converter which outputs an analog output having a good linearity, by attenuating an analog output obtained from low order bits, and then adding the analog output to an analog output obtained from high order bits.

The second object of the present invention is to provide a digital-to-analog converter having a resistor string used commonly by digital-to-analog converters for high order bits and for low order bits, and thus is formed to have a small size and manufactured at a low cost.

The third object of the present invention is to provide a digital-to-analog converter in which a resistor string is used in common by digital-to-analog converters for high order bits and low order bits, and the output impedance of the resistor string can be easily decreased, thus increasing the operating speed of the digital-to-analog converter.

In order to attain the above objects, a digital-to-analog converter of the first aspect comprises:

a first digital-to-analog converter for M bits, for receiving M high order bits of input data of N bits, and then outputting an analog output;

a second digital-to-analog converter for (N-M) bits, for receiving (N-M) low order bits of the input data of N bits, and then outputting an analog output; and

an analog operating circuit for adding the analog outputs of the first and second digital-to-analog converters, with the ratio of the former to the latter being substantially 2.sup.M :1, and outputting an analog signal representing a result of addition of the analog outputs.

In the digital-to-analog converter of the second aspect, according to the first aspect, at least one of the first and second digital-to-analog converters comprises:

a decoder for decoding input digital data;

a voltage dividing circuit comprising unit resistors, which are series-connected to each other between a first reference voltage and a second reference voltage, for outputting divided voltages having a resolution determined in accordance with the number of the N bits of the input data; and

switch circuits connected to voltage dividing output terminals of the voltage dividing circuits, respectively, each of the switch circuits being designed to select one of the divided voltages output from the voltage dividing circuit in accordance with output data of the decoder.

In the digital-to-analog converter of the third aspect, according to the first aspect, the voltage dividing circuit is used in common by the first and second digital-to-analog converters.

In the digital-to-analog converter of the fourth aspect, according to the fourth aspect, the analog operating circuit comprises a plurality of resistor elements for determining the ratio of 2.sup.M to 1 and an operational amplifier for addition of analog outputs.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments give below, serve to explain the principles of the invention.

FIG. 1 is a view showing the structure of a digital-to-analog converter according to an embodiment of the present invention;

FIG. 2 is a view showing the first example of integral construction of an attenuator and an analog adder;

FIG. 3 is a view showing the second example of integral construction of an attenuator and an analog adder;

FIG. 4 is a view showing the third example of integral construction of an attenuator and an analog adder;

FIGS. 5A and 5B are views each showing conversion characteristics of a conventional digital-to-analog converter, and generation of an error voltage at the turn from conversion of high order bits to conversion of low order bits; and

FIG. 6 is a view showing the structure of the conventional digital-to-analog converter.

An embodiment of the present invention will be explained in detail with reference to the accompanying drawings as follows:

FIG. 1 is a circuit diagram showing the structure of a digital-to-analog converter according to the embodiment of the present invention. In the digital-to-analog converter, input digital data of an n-number of bits is divided into M high order bits and (N-M) low order bits, and the M high order bits are input to a digital-to-analog converter 32 for high order bits, and the (N-M) low order bits are input to a digital-to-analog converter 35 for low order bits.

The digital-to-analog converter 32 for high order bits comprises: a string of 2.sup.M resistors 24 to 29 (resistor string) for high order bits, which are unit resistors Rm series-connected to each other between a first reference voltage VR1 (30) and a second reference voltage VR2 (31), constituting a voltage divider; 2.sup.M switch circuits 23 each of which is designed to select one of divided voltages which are obtained by dividing the voltage between the first reference voltage VR1 (30) and the second reference voltage VR2 (31) by means of a respective one of the 2.sup.M resistors 24 to 29; and a decoder 22 for outputting a selection signal for selecting one of the 2.sup.M switch circuits 23 which corresponds to the number of the input M bits.

The digital-to-analog converter 35 for the low order bits comprises: a string of 2.sup.(N-M) of resistors 24 to 29 (resistor string) for low order bits, which are unit resistors Rs series-connected to each other between the first reference voltage VR1 (30) and the second reference voltage VR2 (31), constituting a voltage divider; 2.sup.(N-M) switch circuits 34 each of which is designed to select one of divided voltages which are obtained by dividing the voltage between the first reference voltage VR1 (30) and the second reference voltage VR2 (31) by means of a respective one of the 2.sup.(N-M) resistors 24 to 29; and a decoder 33 for outputting a selection signal for selecting one of the 2.sup.(N-M) switch circuits 34 which corresponds to the number of the input (N-M) bits.

The digital-to-analog converter 32 outputs an analog output having a M-bit resolution as an analog output for high order bits, and the digital-to-analog converter 35 outputs an analog output having an (M-N)-bit resolution as an analog output for low order bits. An analog adder 37 adds the analog output for high order bit and an analog output which is substantially 1/2.sup.M of the analog output for high order bits and which is obtained by attenuating the analog output for low order bits by means of an attenuator 36, thereby obtaining an analog output having an N-bit resolution.

In the embodiment, the resistors 24 to 29 (resistor string) are used in common for high order bits and low order bits, and divided between the reference voltages VR1 (30) and VR2 (31) in accordance with the number of bits of input data. In other words, the resistor string doubles as the resistor string for high order bits and the resistor string for low order bits, since the difference between the resistor string used for high order bits and for low order bits resides only in the number of resistors for dividing a voltage, in the case where the number of high order bits differs from the number of low order bits.

By virtue of the above feature, the number of resistors can be decreased by either the resistor string for high order bits (the M high order bits) or the resistor string for low order bits (the (N-M) low order bits) can be deleted, whichever is smaller than the other in the number of resistors. As a result, the size of the digital-to-analog converter is small, and the cost thereof is low.

For example, the difference between the digital-to-analog converter according to the embodiment and the conventional digital-to-analog converter will be explained by referring to the case of obtaining an analog output having a 12-bit resolution.

If input digital data is divided into 6 high order bits and 6 low order bits, the conventional digital-to-analog converter comprises 128 (2.sup.6 =64.times.2) unit resistors (64 unit resistors for high order bits and 64 unit resistors for low order bits) and 128 switch circuits, whereas the digital-to-analog converter according to the embodiment comprises 64 switch circuits and 64 (2.sup.6) unit resistors the number of which is half that of the unit resistors of the conventional digital-to-analog converter. If the input digital data is divided into 7 high order bits and 5 low order bits, the digital-to-analog converter according to the embodiment has unit resistors the number of which is less than that of the unit resistors of the conventional digital-to-analog converter by 2.sup.5 (32).

In this case, for high order bits, all the switch circuits for high order bits which are respectively associated with the unit resistors Rm are connected to each other, whereas for low order bits, those of the switch circuits for low order bits which are respectively associated with every four unit resistors Rm are connected to each other. In other words, the number of the unit resistors Rs for low order bits is 1/4 of the number of the unit resistors Rm for high order bits (Rs=Rm.times.4).

Furthermore, in the embodiment, the resistors 24 to 29 double as the resistors for high order bits and the resistors for low order bits. Thus, the operating speed of the digital-to-analog converter is limited due to the output impedance of the resistors 24 to 29 doubling as the resistors for high order bits and low order bits.

However, the output impedance can be easily decreased, and thus the operating speed can be easily increased.

FIG. 2 is a view of the first example of the integral construction of the analog adder 37 and the attenuator 36 as an analog operating circuit. The attenuator 36 is used for attenuating the analog output of the digital-to-analog converter 35 for low order bits to 1/2.sup.M. This circuit, as shown in FIG. 2, comprises: first and second voltage follower amplifiers 38 and 39 for receiving the analog outputs of the digital-to-analog converter 32 for high order bits and digital-to-analog converter 35 for low order bits; an operational amplifier 40 for addition of analog outputs; a first resistor element 41 for feedback, which connects the output terminal and negative input terminal of the operational amplifier 40; second and third resistor elements 42 and 43 connected in parallel with each other between the second reference voltage VR2 (31) and the negative input terminal of the operational amplifier 40; a fourth resistor element 44 connected between the positive input terminal of the operational amplifier 40 and the output terminal of the first voltage follower amplifier 38; a fifth resistor element 45 connected between the positive input terminal of the operational amplifier 40 and the output terminal of the second voltage follower amplifier 39; and a sixth resistor element 46 connected between the positive input terminal of the operational amplifier 40 and the second reference voltage VR2 (31). The second, fourth and sixth resistor elements 42, 44 and 46 have the same resistance value, and the third and fifth resistor elements 43 and 45 have the same resistance value. The resistance value of the second, fourth and sixth resistor elements 42, 44 and 46 and the resistance value of the third and fifth resistor elements are determined to satisfy a resistance ratio in accordance with the number of the M high order bits. In addition, "K" in FIG. 2 denotes an attenuating ratio, and the attenuating ratio K is 2.sup.M.

The above circuit of the integral construction is an analog operating circuit for adding the analog output of the digital-to-analog converter 32 and the analog output of the digital-to-analog converter 35, with the ratio of the former to the latter being 2.sup.M :1, and then outputting an analog signal representing a result of addition of the above analog outputs.

The analog output VOUT of the digital-to-analog converter is expressed by the following equation: ##EQU1## where VAM is an analog output voltage of the digital-to-analog converter 32 for high order bits, and VAS is an analog output voltage of the digital-to-analog converter 35 for low order bits.

The analog operating circuit which receives the analog outputs VAM and VAS has voltage follower amplifiers 38 and 39 as a buffer, since its input impedance is low. In addition, it needs a voltage follower amplifier as an output buffer if a load having a low impedance is connected to the analog output VOUT. The analog output VOUT having an N-bit resolution is obtained in accordance with the above equation.

In the embodiment, the attenuating ratio of high order bits to low order bits is determined in accordance with the resistance ratio of a resistance R to a resistance R.times.K. Therefore, a digital-to-analog converter can be achieved which outputs an analog output having a good linearity, since the relative ratio of the resistance R to the resistance R.times.K is kept at a high precision.

Therefore, the digital-to-analog converter according to the embodiment can output an analog output having an excellent linearity, without the need to provide a resistor Rc for adjustment or to carry out a considerably complicated processing such as trimming after the converter is manufactured, unlike the conventional digital-to-analog converter.

FIG. 3 is the second example of the integral construction of the analog adder 37 and the attenuator 36 for attenuating the analog output of the digital-to-analog converter 35 for low order bits to 1/2.sup.M of the analog output. This circuit, as shown in FIG. 3, comprises: first and second voltage follower amplifiers 47 and 48 for receiving the analog outputs of the digital-to-analog converter 32 for high order bits and the digital-to-analog converter 35 for low order bits; a third voltage follower amplifier 49 for receiving the second reference voltage VR2 (31); an operational amplifier 50 for addition of analog outputs; a first resistor element 51 for feedback, which connects an output terminal of the operational amplifier 50 to a negative input terminal thereof; a second resistor element 52 connected between the negative input terminal of the operating terminal 50 and ground potential VSS; a third resistor element 53 connected between the negative input terminal of the operational amplifier 50 and the output terminal of the third voltage follower amplifier 49; a fourth resistor element 54 connected between a positive input terminal of the operational amplifier 50 and an output terminal of the first voltage follower amplifier 47; a fifth resistor element 55 connected between the positive input terminal of the operational amplifier 50 and the output terminal of the second voltage follower amplifier 48; and a sixth resistor element 56 connected between the positive input terminal of the operational amplifier 50 and an output terminal of the third voltage follower amplifier 49. The second, fourth and sixth resistor elements 52, 54 and 56 have the same resistance, and the third and fifth resistor elements 53 and 55 have the same resistance. The resistance of the second, fourth and sixth resistor elements 52, 54 and 56 and the resistance of the third and fifth resistor elements 53 and 55 are determined to satisfy a resistance ratio in accordance with the number of the M high order bits.

The second resistor element 52 may be connected between the negative input terminal of the operational amplifier 50 and the second reference voltage VR2 (31), instead of between the negative input terminal of the operational amplifier 50 and the ground potential VSS.

The "K" in FIG. 4 denotes an attenuating ratio, and the attenuating ratio K is 2.sup.M as in the first example.

The analog output VOUT of the digital-to-analog converter having the above construction is expressed by the following equation:

In the second example, the voltage follower amplifier 49 as a buffer is provided for the second reference voltage VR2 (31), and the resistor R (the resistor element 52) for inputting, connected to the negative input terminal of the operational amplifier 50 for addition of analog outputs, is connected to the ground potential VSS. In this regard, the second example differs from the first example.

More specifically, the input impedance of the operational amplifier 50 is low when the second reference voltage VR2 (31) is set at an intermediate potential of the resistors between power source VDD and the ground potential VSS. Therefore, the voltage follower amplifier 49 is provided for the second reference voltage VR2 (31).

Furthermore, with respect to the term "(VAS-VR2)/K" of the above equation, if an output offset occurs at the voltage follower amplifier as a buffer, the offset voltages of the VAS and VR2 cancel each other, thus further improving the linearity of the analog output, as compared with the first example.

Next, the following is the reason that the resistor R (the resistor element 52) for inputting, connected to the negative input terminal of the operational amplifier 50, is connected to the ground potential VSS:

Due to this connection, an offset voltage corresponding to the voltage VR2 can be added to the analog output VOUT. This is based on the above equation. To be more specific, the above connection enables the range of the analog output of the digital-to-analog converter to differ from the range of the analog output of the resistor string. For example, when the analog output of the resistor string falls within 0.75V to 2.75V (2Vp-p:1.75 center), VR2 is 0.75V, and it is determined from the equation that the analog output of the digital-to-analog converter falls within 1.5V to 3.5V (2Vp-p:2.5V center).

By virtue of this feature, if the voltage follower amplifiers as a buffer and the switch circuits have optimal operating ranges with respect to analog characteristics, the analog output of the resistor string can be determined in accordance with the above optimal operating ranges, and the analog output of the digital-to-analog converter can be determined to fall within the range specified in the specification of the digital-to-analog converter. As a result, the linearity of the analog output of the digital-to-analog converter can be improved since the voltage follower amplifiers as a buffer and the switch circuits can be used within the optimal operating ranges with respect to the analog characteristics.

Furthermore, if the resistor R for feedback, which connects the output terminal and negative input terminal of the amplifier for addition of analog outputs, is set at a value G times greater than the resistor R for inputting, the digital-to-analog converter can have a gain G times greater than that in the case where the resistor R for feedback is set at the same value as the resistor R for inputting. For example, when the resistor R for feedback is set a value 1.5 times greater than the resistor R for inputting, and the analog output amplitude of the resistor string is 2Vp-p, the analog output amplitude of the digital-to-analog converter is 3Vp-p.

FIG. 4 shows the third example of the integral construction of the analog adder 37 and the attenuator 36 for attenuating the analog output of the digital-to-analog converter 35 for low order bits to 1/2.sup.M of the analog output. This circuit, as shown in FIG. 4, comprises (i) an operational amplifier 57 for addition of analog outputs, (ii) a first capacitor element 58 for feedback, which connects an output terminal of the operational amplifier 57 and a negative input terminal thereof, (iii) a switch element 61 connected in parallel with the first capacitor element 58, (iv) a second capacitor element 59 connected between the negative input terminal of the operational amplifier 57 and an analog output terminal of the digital-to-analog converter 32 for high order bits, and (v) a third capacitor element 60 connected between the negative input terminal of the operational amplifier 57 and the analog output terminal of the digital-to-analog converter 35 for low order bits. A positive input terminal of the operational amplifier 57 is connected to the ground potential VSS, the capacitance of the second capacitor element 59 and the capacitance of the third capacitor element 60 are determined such that a capacitance ratio of the former capacitance to the latter capacitance varies in accordance with the number of the M bits.

The circuit of the third example adds the capacitances of the capacitor elements, whereas each of the circuits of the first and second examples adds the resistances of the resistor elements. The "K" in FIG. 4 denotes an attenuating ratio, and the attenuating ratio K is 2.sup.M.

In the circuit of the third example having the above feature, the analog output VOUT of the digital-to-analog converter is expressed by the following equation:

In this case, the input impedance of the operational amplifier 57 is high, and thus the circuit of the third example does not use the voltage follower amplifiers as a buffer which are necessary for the circuits of the first and second examples which add the resistances of the resistor elements. Furthermore, if the capacitance C.times.(1+K) of the first capacitor element 58 for feedback, which connects the output terminal and negative input terminal of the operational amplifier 57, is set at a value G times greater than the capacitance C.times.K of the second capacitor element 59, the operational amplifier 57 can have a gain 1/G times greater than that in the case where the capacitance C.times.(1+K) of the first capacitor element 58 is set at the same value as the capacitance C.times.K of the second capacitor element 59.

As explained above, in the embodiment, a weighting value is added to one of the analog outputs of the digital-to-analog converters which divide an applied voltage to obtain voltages each having a low resolution (a small number of bits), and then the analog outputs are added, thereby to obtain and output analog data. In such a manner, the digital-to-analog converter according to the embodiment is constituted by the digital-to-analog converters which divide a voltage to obtain voltages each having a low resolution (a small number of bits), and thus obtain a voltage having a high resolution (a large number of bits). In addition, it may be used as a digital-to-analog converter of serial comparison type.

In the above embodiment of the present invention, the analog output of the digital-to-analog converter for low order bits is attenuated by the attenuator, and then added to the analog output of the digital-to-analog converter for high order bits. However, the analog output of the digital-to-analog converter for high order bits may be increased by a booster, and then added to the analog output of the digital-to-analog converter for low order bits.

To summarize, in the embodiment, the analog output of the digital-to-analog converter for low order bits is attenuated by the attenuator, and then added to the analog output of the digital-to-analog converter for high order bits, as mentioned above. In addition, the attenuating ratio can be controlled by adjusting the resistance ratio or the capacitance ratio. Thus, the linearity of the analog output of the digital-to-analog converter can be improved even in the case where the converter is incorporated into an LSI or the like.

Moreover, the resistor string is used in common by the digital-to-analog converters for high order bits and for low order bits, thus reducing the number of resistors by the number of resistors doubling as ones for high order bits and ones for low order bits. As a result, the digital-to-analog converter can be formed to have a small size, and thus can be manufactured at a low cost.

In addition, the operating speed of the digital-to-analog converter can be increased since it is possible to easily decrease the output impedance of the resistor string doubling as the resistor strings of the digital-to-analog converters for high order bits and low order bits.

Additional advantages and modifications will readily occurs to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.