Unlanded via Process

1. Field of the Invention

The present invention relates to an unlanded via process, and more particularly, to a method for forming an unlanded via hole.

2. Description of the Prior Art

The technology of semiconductors is improving daily. To increase the scale of integrated circuits, the technology of multilevel interconnects has been developed. In such an integrated circuit, the patterned conductive material on one interconnect level is electrically insulated from the patterned conductive material on another level by a dielectric layer (e.g., a silicon dioxide layer). This dielectric layer is called inter-metal dielectrics (IMD). For the specific-point contact of two levels, via holes are opened in the dielectrics and filled by an electrical conductor. These structures are often referred to as vias.

In some cases, it is necessary to increase the width of the underlying conductive material to provide the landing of the conductor formed in the via hole. Therefore, the increase in minimum width increases the pitch, and correspondingly decreases the packing density. The pitch described above is the width of an interconnect line and the space required between those lines.

For submicron technology, in order to reduce the pitch and save the area, the unlanded via process was developed. Its use has been suggested to form an unlanded via hole, which could contain the conductor unlanded on the underlying conductive material, instead of the original landing via hole. That is, when the conductor in the via hole connects with the underlying conductive material, it is not necessary that the underlying conductive material contains completely the bottom area of the conductor which is in the via hole. In the conventional process, unlanded via etching is the critical step. It should be optimized between high resistance and via profile loss. Therein, the high resistance is due to insufficient etching shown in FIG. 1. Referring to FIG. 2, the via profile loss is due to too much overetching. This also makes via resistance high and the following process, such as barrier forming, to be out of control.

For the foregoing reasons, there is a need for a method of forming an unlanded via hole which can substantially improve the high resistance and the via profile loss problem which occurrs in an unlanded via etching processes.

In accordance with the present invention, a method is provided for forming an unlanded via hole that substantially solves both the problems of high resistance and via profile loss due to etching. In one embodiment, a metal layer on a first dielectric layer is provided firstly. A silicon-rich oxide layer is then formed on the first dielectric layer and the metal layer by plasma enhanced chemical vapor deposition (PECVD). A spin-on glass (SOG) layer is formed on the silicon-rich oxide layer and subsequently etched back until the metal layer is exposed. The following procedure is to deposite a silicon nitride layer on the SOG layer and the metal layer. An oxide layer is deposited on the silicon nitride layer and planarized by chemical mechanical polishing (CMP). Thereafter, a patterned photoresist layer is formed on the oxide layer. Then the etching process is used to etch the oxide layer and the silicon nitride layer to form an unlanded via hole. Finally, the photoresist layer is removed. The unlanded via hole provided by the invention would give the unlanded via a good profile.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a cross-sectional view illustrative of an insufficiently-etched unlanded via hole.

FIG. 2 shows a cross-sectional view illustrative of an overetched unlanded via hole.

FIGS. 3-7 show the cross-sectional views illustrative of various stages of fabrication of an unlanded via hole according to the present invention.

Referring to FIG. 3, firstly a structure is provided, in which a conductor layer 11 is formed and patterned on a first dielectric layer 10. The component of the conductor 11 is usually metal, such as aluminum (Al) or copper (Cu). The structure exhibits a conductive level of multilevel interconnects.

Referring to FIG. 4, a silicon-rich oxide (SRO) layer 12 which has a thickness in the range of approximately 100 nm to approximately 200 nm is formed on the first dielectric layer 10 and the metal layer 11 by CMP. A spin-on glass (SOG) 13 is then formed on the silicon-rich oxide layer 12. Therein, the SRO 12 having a dense structure is used to insulate the metal layer 11 from vapor contained in SOG. In sub-micron dimensions, the SOG can fill a narrower space without causing voids than can CVD intermetal dielectric layer. SOG materials are siloxanes or silicates mixed in alcohol-based solvents, the primary difference between them being that a small percentage of Si--C bonds remain in the siloxane-based SOGs following the final cure cycle. Upon baking, the solvents are driven off and the remaining solid layer exhibits properties similar to those of SiO.sub.2. Silicate SOGs can also be doped with such compounds as P.sub.2 O.sub.5 to improve their dielectric layer properties. Other advantages of SOG include simpler processing, lower defect density, higher throughput, relatively low cost and no the elimination of handing of hazardous gases.

Referring to FIG. 5, the SOG layer 13 is etched back until the metal 11 is exposed. Subsequently, a silicon nitride (SiN) layer 14 is formed on the metal 11 and the etched SOG 13. Plasma-enhanced chemical vapor deposition (PECVD) is used in its formation. The silicon nitride 14, approximately 30 to 100 nm thick, is used as the stop layer of following etching process.

Referring to FIG. 6, an oxide layer 15, approximately 700 to 1100 nm thick, is deposited on the silicon nitride layer 14 by a PECVD process. The oxide layer 15, used as an inter-metal dielectric (IMD), is subsequently provided with a chemical-mechanical polishing (CMP) to eliminate the height non-uniformities at the surface. The CMP, used to achieve a planar surface over the entire chip and wafer, is a common planarizing technique. Then, a patterned photoresist layer 16, in which an unlanded via hole is defined, is formed on the oxide layer 15.

Referring to FIG. 7, an etching process with a proper range of selectivity (10-15 etches) tis used to etch he oxide 15 and silicon nitride 14 until the metal 11 is exposed. An unlanded via hole 17 is formed. Finally, the photoresist layer is removed. When the oxide etching is finished, the SiN layer will reduce the etching rate because of the selectivity 10-15 and be etched completely in a fixed time. Owing to the SiN stop layer, the problem of overetching would be solved. Moreover, enough etching time would result in the good profile of an unlanded via hole. The disadvantage of high resistance of an unlanded via would be avoided.

Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.