Low Voltage Dual-Modulus Prescaler Circuit Using Merged Pseudo-Differential Logic

The present invention relates generally to frequency synthesizers for communications devices, and more particularly to a novel prescaler circuit for use in a frequency synthesizer which significantly reduces the amount of current consumed by the synthesizer.

Wireless communication devices such as handsets typically include low power frequency synthesizers that monitor a plurality of frequency channels to determine whether any transmissions are present on those channels. If a transmission is found to be present on a particular channel, the synthesizer tunes to the frequency of that channel to permit the user to receive the incoming transmission. Since the frequency synthesizer is usually the first circuit in the communications device that is actuated, and since it is actuated at frequent intervals (as often as once per millisecond) to continually monitor for incoming transmissions, optimization of its performance and minimization of the current consumed is desirable.

There have been several approaches to improving the performance of synthesizers. The "technology improvement" approach is concerned primarily with developing devices that have a lower output capacitance and/or a lower substrate capacitance. Lower capacitances permit the device to switch faster. In particular, emitter-coupled logic (ECL) utilizes this approach to achieve significantly faster operational speeds. ECL has a significant drawback, however, in that current is continually consumed, even when devices employing this technology are not switching (changing the states of the inputs and outputs).

Another approach is reduction of current consumption through improvement of circuit topology. That is, the amount of current consumed can be reduced if the size of the circuit and/or the number of circuit components can be reduced. Synthesizers typically include a prescaler circuit, which divides the input frequency by a desired factor. As the prescaler is one of the most current-hungry components in the synthesizer, this is where optimization and current consumption reduction efforts have been focused.

The present invention provides a prescaler circuit for a frequency synthesizer that is of reduced size and utilizes a reduced number of components relative to the prior art, and hence, that consumes less current than prior art circuits.

In one embodiment of this invention, a prescaler circuit includes two blocks of merged OR/flip-flop logic. An input clock signal having a frequency FN is supplied to the flip-flop of each block, and an output clock signal having a frequency of either FN/2 or FN/3 is generated. A control signal input to the OR gate of the second block determines whether the output frequency is divided by two or by three.

According to one aspect of the invention, the prescaler circuit utilizes primarily differential signals in order to deal with the problem of common-mode noise. Single-ended common-mode signals, however, are also provided at OR gate inputs in order to ensure proper functioning of the OR gates. In order to extract the common-mode signal, the actual and inverted components of a differential signal are summed and divided with high value resistors, yielding a common-mode signal that is supplied to the OR gates.

The present invention also provides a method for prescaling a frequency by a factor of 2 or 3. First and second circuit blocks are provided, wherein each block is an OR gate coupled with a master-slave flip-flop. A clock signal having a frequency FN is input to each block, and a control signal is input to one of the blocks. Depending on the value of the control signal, a signal having a frequency FN/n is output from one of the blocks.

Further features and advantages of the invention, as well as the structure and operation of particular embodiments of the invention, are described in detail below with reference to the accompanying drawings.

The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements, and

FIG. 1 is a block diagram illustrating a 2/3 prescaler circuit;

FIG. 2 is a schematic diagram illustrating the prescaler circuit of FIG. 1 in greater detail;

FIG. 3 is a block diagram illustrating a prescaler circuit according to the present invention;

FIG. 4 is a schematic diagram illustrating the prescaler circuit of FIG. 3 in greater detail; and

FIG. 5 is a schematic diagram illustrating the sub-circuitry of one of the merged OR/flip-flop logic blocks of the circuit of FIGS. 3 and 4.

A 2/3 prescaler circuit 10 is illustrated in FIGS. 1 and 2. Although it incorporates some aspects and features of the present invention, circuit 10 is illustrated primarily for purposes of establishing a context for, and contrasting with, the present invention Applicant neither intends nor makes any admission regarding the prior art effect of circuits 10.

Circuit 10 is known as a 2/3 prescaler since, contingent on the setting of a control signal, the frequency of an input signal is divided by either a factor of two or of three (i.e., circuit 10 is a "dual modulus" circuit). Other division factors may be realized by combining the base prescaler circuit with additional logic. Prescaler circuit 10 includes two AND gates 12 and 14, two master-slave flip-flops 16 and 18, and two level shifters 20 and 22 (level shifter 22 is illustrated in FIG. 2 only). With reference to FIG. 1, a clock pulse generator feeds a clock signal clk.sub.in having a pulse frequency FN into circuit 10 and, contingent on the setting of control signal f.sub.ctrl, circuit 10 generates an output clock signal clk.sub.out having a pulse frequency of either FN/2 or FN/3.

Prescaler circuit 10 is illustrated in greater detail in FIG. 2. Each of the components of circuit 10 is connected to a bias voltage v.sub.cs a ground signal at the ports designated n.sub.sup and a supply voltage V.sub.cc at the ports designated P.sub.sup. The connections between the components of circuit 10 are differential or "double-ended" connections, that is, both the actual logical or "positive" value of a signal as well as its inverted value are utilized. Differential signals are utilized to address the problem of common-mode noise. Common-mode noise arises when capacitances existing between circuit components and lines become coupled to a signal line, resulting in an offset or inaccurate signal level. Dual lines carrying differential signals, however, are so proximate that any amount of capacitance or noise coupled to one line will be coupled to its companion differential line in nearly exactly the same amount. Hence, the undesired common-mode noise is coupled by exactly the same amount to each differential line, with the result that it is cancelled out when the difference is taken. This is known as common-mode rejection; any commonmode noise coupled to the differential logic is rejected.

Differential input clock signals cki.sub.p and cki.sub.n, having a frequency FN, are applied to master-slave flip-flops 16 and 18 at the ports designated samp and latch. AND gate 12 receives differential input signals at ports l.sub.p1, and l.sub.nl from the output of flip-flop 16, and differential input signals at ports i.sub.p2 and i.sub.n2 from the output of level shifter 20. The differential output of AND gate 12 is fed from ports o.sub.p and o.sub.n to, respectively, ports l.sub.n and l.sub.p of flip-flop 16.

Flip-flop 16 outputs a differential signal from ports o.sub.p and o.sub.n which is fed to, respectively, inputs l.sub.n1 and l.sub.p1 of second AND gate 14. Additionally, this signal is fed back to the inputs of first AND gate 12, as well as forwarded to ports samp and latch of flip-flop 18. AND gate 14 is also supplied with a differential input control signal designated by ct3.sub.p and ct3.sub.n. The setting of this control signal determines whether circuit 10 will divide the frequency of the input clock signal by a factor of two or by a factor of three. The differential output of AND gate 14 is fed from ports o.sub.p and o.sub.n to, respectively, ports l.sub.n and l.sub.p of flip-flop 18. The differential output of flip-flop 18 is fed back to level shifter 20 which, in turn, supplies the differential input to AND gate 12.

The differential output of flip-flop 16 is also passed through level shifter 22, which outputs clock signals ck23.sub.p and ck23.sub.n. This signal is the end output signal of circuit 10; it has a frequency FN/2 if control signal ct3.sub.p has a logical value of zero, and a frequency FN/3 if the control signal has a logical value of one. Looking at circuit 10 in FIG. 2, the reason for this result is apparent. So long as a logical zero (control signal ct3.sub.p) is fed to AND gate 14, the output of AND gate 14 will remain a constant zero, irrespective of the value of the other input signal received by AND gate 14 from flip-flop 16. Hence, flip-flop 18, which receives the NAND'ed output of AND gate 14, will not change states and will generate a constant output of a logical one. The stage represented by AND gate 14 and flip-flop 18 is essentially taken out of the circuit and has no effect on the frequency of the output signal. Since AND gate 12 receives a logical one through level shifter 20, however, its output will change depending on the feedback input received from flip-flop 16. And, since the NAND'ed output of AND gate 12 is supplied to flip-flop 16, the output of flip-flop 16 will change with each rising clock pulse. The result is an output clock signal ck23.sub.p having a frequency FN/2.

Conversely, when control signal ct3.sub.p is set to a logical one, the output of AND gate 14 will vary depending on the value of the input signal received from flip-flop 16. In this scenario, both stages of the circuit are involved and both flip-flops regularly change states, thereby producing an output signal having a pulse frequency FN/3.

The power consumed by circuit 10 is essentially equal to V.sub.cc *I.sub.Q (the sum of the currents in the circuit). In order to reduce the power consumed, one may reduce V.sub.cc or one may reduce I.sub.Q. In bipolar logic devices employing base-emitter junctions, however, the voltage cannot be scaled. Hence, reduction of V.sub.cc to effect a reduction in circuit power consumption is not a viable option. I.sub.Q, however, is directly related to the size of and number of components in the circuit. Accordingly, if the size of the circuit can be reduced, for example, by removing or merging some of the circuitry components and designing a smaller loop, the current and power consumed by the circuit can also be reduced. This is the objective of the present invention, which is embodied in circuit 50 (FIGS. 3-5).

Circuit 50 performs the same function as circuit 10 described above, that is, it takes an input clock signal having a pulse frequency FN and generates an output signal having a divided pulse frequency of FN/2 or FN/3. Instead of utilizing AND gates serially connected with flip-flops, however, it merges or couples the OR and flip-flop logic to eliminate a level of logic. Circuit 10 has three levels of logic: the AND logic, the flip-flop logic and the level-shifting logic. The use by circuit 50 of OR gates rather than AND gates, and their merger (connection in parallel on the same IC chip) with the flip-flops, reduces the number of logic levels required. By implementing all logic on one level, the need for level shifters is also eliminated, and the amount of current consumed by the circuit is further reduced.

Prescaler circuit 50 is illustrated in simplified block form in FIG. 3. It includes blocks 52 and 54, each of which is essentially a merger or coupling of an OR gate (56, 60) with a master-slave flip-flop (58,62). Circuit 50 produces the same results as circuit 10 described above: a clock pulse generator feeds a clock signal clk.sub.in having a pulse frequency FN into circuit 10 and, contingent on the setting of control signal f.sub.ctrl, circuit 10 generates an output clock signal clk.sub.out having a pulse frequency of either FN/2 or FN/3.

The problem of common-mode noise still exists in circuit 50 and hence, differential signals are utilized as they were in circuit 10. In order to provide a stable, accurate output from the merged OR/flip-flop logic, however, single-ended or common-mode signals are needed at some of the inputs to the OR logic. To address this issue, circuit 50 utilizes primarily differential signals and, where a single-ended signal is needed, a common-mode signal is extracted from the two differential signals. In order to extract the common-mode signal, the two differential signals are summed and divided by two with a pair of high and equal value resistors, yielding the common-mode or average signal. Hence, circuit 50 is pseudo-differential in that it utilizes both single-ended (common mode) and double-ended (differential) signals.

Circuit 50 is illustrated in greater detail in FIG. 4. Each of blocks 52 and 54 is essentially OR logic merged with a master-slave flip-flop. The sub-circuitry of the merged OR/flip-flop blocks is illustrated in FIG. 5 and will be discussed in more detail herein. For purposes of the following discussion, however, it can simply be considered a block consisting of an OR gate (56, 60) whose output is coupled to the input of a master-slave flip-flop (58, 62).

Each of blocks 52 and 54 is connected to a supply voltage V.sub.cc, a ground and a system bias voltage v.sub.cs (not shown). Differential clock signals cki.sub.p and cki.sub.n having a pulse frequency FN are supplied to the clock inputs of each of blocks 52 and 54. Second merged block 54 receives inputs as follows: at port i.sub.p1, the positive component of the differential signal output from block 52; at port i.sub.cm1, the common-mode signal generated from the differential outputs of block 52 by high value summing and dividing resistors R.sub.1 and R.sub.2 ; at port i.sub.p2, the positive component ctrl.sub.p of the differential control signal; and at port i.sub.cm2, the common-mode control signal generated by summing and dividing the differential components of the control signal through resistors R.sub.3 and R.sub.4.

The differential output of second block 54 is fed back to first block 52: the inverted component (from port o.sub.n) of the differential output signal is coupled to input port i.sub.p2 of block 52, and the common-mode signal generated by summing and dividing the differential outputs of block 54 through resistors R.sub.5 and R.sub.6 is coupled to input port i.sub.cm2. Block 52 also receives feedback of its own output signals: the inverted component (from port o.sub.n) of the differential output of block 52 is coupled to input port i.sub.p1 of block 52; and the common-mode output signal generated by summing and dividing the differential outputs of block 52 through resistors R.sub.7 and R.sub.8 is connected to port i.sub.cm1.

The differential output signals cko.sub.p and cko.sub.n of first block 52 have a pulse frequency of either FN/2 or FN/3, depending on the setting of the control signal supplied to second block 54. The operation of circuit 50 is similar to that of circuit 10, however, the effects of the control signal are reversed. A control signal of zero will yield an output signal having a pulse frequency FN/3, whereas a control signal of one will yield an output signal having a pulse frequency FN/2.

Operation of circuit 50 is as follows. A logical one input to OR gate 60 of block 54 will yield a constant output of one from OR gate 60 to flip-flop 62, irrespective of the value of the input signal received from block 52. Hence, flip-flop 62 will not change states or affect the pulse frequency as long as the control signal is a logical one. The inverted output of flip-flop 62 (zero, when the control signal is one) is fed to OR gate 56 of block 52. Accordingly, the output of OR gate 56 is contingent on the value of the feedback input signal received from flip-flop 58. Since it is the inverted value of the output signal of flip-flop 58 that is fed back, the output of flip-flop 58 will also change with each rising clock pulse, thereby generating an output clock signal cko.sub.p having a frequency FN/2.

Conversely, when control signal ctrl.sub.p is set to a logical zero, the output of OR gate 60 will vary depending on the value of the input signal received from block 52. In this case, both stages of the circuit are involved and both flip-flops regularly change states, thereby producing an output signal having a pulse frequency FN/3.

The sub-circuitry of merged or coupled OR/flip-flop block 52 is illustrated in FIG. 5. Block 54 utilizes identical circuitry. The right half 72 of the circuit is the slave latch portion of the flip-flop, the schematic of which is well known to those skilled in the art and will not be described in further detail herein. The left half 70 of the circuit is the master latch portion of the flip-flop. The master latch has been slightly altered to incorporate OR logic: a first transistor T1 has been placed in parallel with the conventionally configured transistor T3; and a second transistor T2 has been placed in parallel with the conventionally configured transistor T4. It is this placement of the transistors in parallel that effects the "merger" or coupling of the OR and the flip-flop logic. Hence, references in this specification to a merger or coupling of OR and flip-flop logic, or a merged OR/flip-flop block, refer to this placement of two transistors in parallel with the existing transistors of a master latch portion of a conventional master-slave flip-flop.

The emitters of each of transistors T1, T2, T3 and T4 are coupled to the input clock signal cki.sub.p via the collector of transistor T5. The base of transistor T1 is connected to the positive component i.sub.p2 of a first differential signal; and the base of transistor T2 is connected to the common-mode signal i.sub.cm2 derived from the first differential signal. The base of transistor T3 is connected to the positive component i.sub.p1 of a second differential signal; and the base of transistor T4 is connected to the common-mode signal i.sub.cm1 derived from the second differential signal. The collectors of transistors T1 and T3 are coupled together, as are the collectors of transistors T2 and T4.

The desired outputs of this modified OR portion of the circuit are designated C and C in FIG. 5. If either i.sub.p1 or i.sub.p2 has a logical value of one, C should have a value of one (logical high) andC should have a value of zero (logical low). Analyzing circuit 52, it is seen that this is the result. If the base voltage of either of transistors T1 or T3 is high (meaning either or both of i.sub.p1 and i.sub.p2 are logically high), a current will flow through the collectors of one or both of transistors T1 and T3, and current will be pulled away from transistors T4 and T2, whose bases are charged to the lesser common-mode voltage. Hence, little or no current will flow through resistor R10, requiring C to be approximately equal to V.sub.cc, or logically high. Since current is flowing through the collectors of transistors T1 and/or T3 and through resistor R9, C will be less than V.sub.cc, or logically low.

Conversely, when both i.sub.p1 and i.sub.p2 have a logical value of zero, current is pulled away from transistors T1 and T3 and towards transistors T2 and T4, whose bases are charged to the higher common-mode voltage. Hence, C will be logically low (due to current flowing through resistor R10, and C will be logically high (since no current flows through resistor R9, C must be approximately equal to V.sub.cc). This is the correct result.

Notably, the correct result would not be obtained if, rather than applying the common-mode signals to transistors T2 and T4, one simply applied the inverted components of the differential signals to the transistors. Consider a case where the input to the base of transistor T1 is logically high and the input to the base of transistor T3 is logically low (or vice-versa). If the inverted components of these signals were simply applied to transistors T2 and T4, the base of transistor T2 would be logically high and the base of transistor T4 would be logically low. Both transistor pairs T1/T3 and T2/T4 would attempt to pull current, and a logically translatable result would not be obtained. Hence, it is necessary to utilize common-mode signals in order to obtain the desired outputs C and C. The common-mode signals act as a middle ground, having a voltage low enough to pull little or no current when logically high signals are applied to one or both of transistors T1 and T3, but a voltage high enough to pull current when logical zeros are applied to both of transistors T1 and T3.

Comparing circuit 50 (FIG. 3) with circuit 10 (FIG. 1), it is notable that the five "blocks" required by circuit 10 have been reduced to two blocks in circuit 50. There is no need for a level shifter in circuit 50 since the extra level necessitated by the use of AND logic has been eliminated. With respect to the merger or coupling of the OR and flip-flop logic in circuit 50, even though two components are being merged into one, the resulting merged component does not consume twice the current of the individual components. In the merged logic, common collectors are present from two devices that must be charged at the same time, resulting in a doubled capacitance. However, due to the relationship of the charging time with the input capacitance and a time constant related to output capacitance, the current does need not be doubled in order to charge the two devices. A current savings of nearly fifty percent is realized.

While particular embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not as limitations. The breadth and scope of the present invention is defined by the following claims and their equivalents, and is not limited by the particular embodiments described herein.