Current Limiter Responsive to Changing Parallel Power Supply Capacity

1. Technical Field

The present invention relates in general to regulating power supplies, and in particular to a system and method for regulating the total power delivered from a parallel power supply. Still more particularly, the system and method of the present invention relate to dynamically adjusting the maximum current limit for each of a plurality of parallel power supplies in accordance with variations in available power supply capacity, such that the total available output power never exceeds a maximum allowable limit.

2. Description of the Related Art

Conventional power supply systems often utilize multiple, parallel power supply circuits for improved adaptability to load variations and also for increased reliability. Representative parallel power supply systems (referred to alternatively in the art as "N+1 power systems") are described in U.S. Pat. No. 5,319,536 (issued Jun. 7, 1994, to R. Malik), U.S. Pat. No. 5,266,838 (issued Nov. 30, 1993 to Gerner), and U.S. Pat. No. 5,745,670 (issued Apr. 28, 1998 to Linde).

FIG. 1 illustrates a conventional parallel power supply system 101 comprising three power supplies, PS1 102, PS2 103, and PS3 104 that together provide a source of power to electrical system 106. For safety reasons, a maximum allowable power output limit is imposed on each of PS1 102, PS2 103, and PS3 104, and also on the total power delivered from power supply system 101 to electrical system 106.

As seen in FIG. 1, each of the three power supplies in system 101 employs an individual current sense resistor (R.sub.CS 1 108, R.sub.CS 2 110, and R.sub.CS 3 112 for PS1 102, PS2 104, and PS3 106, respectively). R.sub.CS 1 108, R.sub.CS 2, and 110 R.sub.CS 3 112 are utilized to detect the level of current on each parallel supply line (I.sub.1 122, I.sub.2 124, and I.sub.3 126). An additional current sense resistor, R.sub.CS 114, is inserted within a power backplane 118 where the outputs of all three power supplies converge.

R.sub.CS 114 is utilized to sense the total supply current, I.sub.T 120, which is equal to the sum of I.sub.1 122, I.sub.2 124, and I.sub.3 126. Assuming that the Volt-Amp (VA) limit for electrical system 106 is the same as that for each power supply, the maximum allowable current level for I.sub.T 120 is three times the maximum level permitted for each individual power supply circuit (I.sub.1 122, I.sub.2 124, and I.sub.3 126). To ensure compliance with the maximum allowable VA limit, R.sub.CS 114 monitors the magnitude of I.sub.T 120, and if an excessive level of current (relative to V.sub.o 116) is detected, power supply system 101 is forced to shutdown. Current sense resistor R.sub.CS 114 must be a carefully selected resistor having a minimum voltage drop to avoid reducing rail-to-rail voltage. This low voltage drop requirement necessitates a precise, low resistance value for R.sub.CS 114. Such precision and low resistance characteristics dramatically increase the cost of R.sub.CS 114 and also require a low offset comparator. The utilization of an additional current sense resistor such as R.sub.CS 114 thus results in reduced power supply efficiency as well as increased cost of power supply system 101.

Modern circuits have much lower operating voltages than previous generations of integrated circuits. A current standard for state-of-the-art integrated circuits is 1.8 volts. Thus an additional voltage drop caused by the a conventional current sense resistor may result in an unacceptable decrease in the rail-to-rail voltage.

It would therefore be desirable to provide an indirect (non-resistive) method for determining total available parallel power supply capacity and dynamically adjusting the output current level of each parallel power supply in response thereto, such that the VA levels for all circuits within an N+1 power supply are maintained below the maximum allowable limit.

It is therefore one object of the present invention to provide an improved system and method for regulating the total power delivered from a plurality of parallel power supplies.

It is another object of the present invention to provide a system and method for dynamically adjusting the output current limit for each of a plurality of parallel power supplies in accordance with variations in total available power supply capacity, such that the level of output power from the power supply never exceeds a maximum allowable limit.

The foregoing objects are achieved as is now described. An improved power regulation system and method are disclosed for adjusting the maximum allowable current limit for each of a plurality of parallel power supplies within an N+1 power supply system in response to dynamic variations in the total supply current capacity of the N+1 power supply system. A plurality of parallel power supplies comprise the N+1 power supply which provides power to a load. A sensor within each of the parallel power supplies determines an operating status of each of the parallel power supplies. A detector circuit in communicative contact with the sensors translates the operating status determination into a supply current capacity signal. Finally, a current limit adjustment circuit generates a current limit signal in response to the supply current capacity signal, such that the maximum allowable current limit for each parallel power supply is adjusted while maintaining the overall power supply VA limit for the N+1 power supply.

The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 depicts a schematic representation of a conventional power limit circuit for a parallel power supply system;

FIG. 2 is a block diagram illustrating a preferred embodiment of the dynamic power limit system of the present invention;

FIG. 3A depicts a schematic representation of one embodiment of the dynamic current limit adjustment circuit of the present invention accounting for variations in N+1 power supply capacity; and

FIG. 3B illustrates a current limit adjustment circuit in accordance with the system and method of the present invention.

Parallel power supply systems (often referred to as N+1 power supplies) are well-known in the art. The total Volt-Amp (VA) power output from an N+1 power supply is supplied utilizing multiple AC/DC converters connected in parallel. The total VA supplied to the load from an N+1 power supply, as well as the power output from each individual converter, must be maintained below a specified safety limit. For many systems this limit is specified as 240 VA. As explained with reference to FIG. 1, current sense resistors are often utilized within each converter to ensure compliance with the maximum allowable VA limit. As further illustrated in FIG. 1, an additional current sense element, such as R.sub.CS 114, has been conventionally required to monitor the cumulative power supplied by the parallel converters to ensure compliance with the maximum power limit.

The present invention provides an improved power regulator which utilizes real-time variations in the available supply current capacity as a means for indirectly maintaining the maximum power output limit. The present invention provides an efficient and economical means for dynamically adjusting the current limit from each parallel converter, thus eliminating the need for an additional current sense element. The value of available supply current (referred to hereinafter as "supply current capacity") is monitored and translated into a current limit feedback signal within a conversion and amplification feedback unit. By accounting for real-time changes in total power supply capacity, the system and method of the present invention ensure VA limit compliance while providing the maximum available source current to accommodate fluctuations in power supply load. In one embodiment of the present invention, the total output current capacity for an N+1 power supply is specified in proportion to the number of currently operating parallel power supplies.

FIG. 2 is a block diagram illustrating a power supply system 200 in accordance with the system and method of the present invention. As seen in FIG. 2, power supply system 200 comprises an N+1 power supply 203 which provides a supply voltage, V.sub.o 234, and a supply current, I.sub.o 232, for a system load 236. As illustrated in FIG. 2, N+1 power supply 203 comprises n parallel AC/DC converters, C.sub.1 202 through C.sub.n 206, each contributing a partial current, I.sub.p (not depicted), to I.sub.o 232 in accordance with the following relation:

wherein p is equal to the subset of n converters that are currently operating. As further depicted in FIG. 2, C.sub.1 202, C.sub.2 204, and C.sub.n 206 include sensors 210, 212, and 214, respectively, which provide a means for monitoring the I.sub.p supplied from each converter. If any such individual current level causes the corresponding VA output from any converter to exceed a pre-determined limit, the corresponding current sensor will deliver a shut down signal for that converter.

Power supply system 200 further comprises a current regulator 205 which is constructed and which operates in accordance with the system and method of the present invention. Current regulator 205 includes a supply capacity sensor 208 and a feedback amplifier 224. As illustrated in FIG. 2, supply capacity sensor 208 receives a current sense signal from each of sensors 210 through 214. In the depicted embodiment, these current sense signals provide a real-time indication of the operating status of each power converter. The operating status of each of C.sub.1 202 through C.sub.n 206 is in turn utilized as the supply capacity metric for N+1 power supply 203. Analog-to-digital converters (ADCS) 216, 218 and 220 provide suitable binary translations for a detector circuit 222. Detector circuit 222 comprises a binary combinatorial logic circuit which translates the current sense inputs from sensors 210 through 214 into a corresponding supply capacity signal 228.

The maximum permissible value for I.sub.o 232 may be determined in accordance with the following relation:

wherein Maximum VA is a pre-determined value equal to the maximum allowable power limit. V.sub.o 234 is maintained as close as possible to pre-determined rail-to-rail voltage level requirements of electrical system 236, and is therefore a relative constant. Maximum VA is therefore observed as a function of variations in I.sub.o 232 which fluctuates in response to shifting electrical loads of system 236.

If all n power converters are currently operating, and assuming each converter contributes equally to I.sub.o 232, then each converter has an output current, I.sub.p, (not depicted) having a magnitude that may be determined in accordance with the following relation:

Rather than monitoring and reacting to actual current levels I.sub.p and I.sub.o 232, the present invention anticipates the maximum allowable level for I.sub.p, referred to hereinafter as I.sub.max, in accordance with the current supply capacity of N+1 power supply system 230. The power regulator of the present invention monitors the total output current capacity (not to be confused with actual output current, I.sub.o 232) of N+1 power supply system 230 utilizing sensor circuit 208.

As depicted in FIG. 2, supply capacity signal 228 is delivered from supply capacity sensor 208 to feedback amplifier 224. Feedback amplifier 224 includes a current limit adjustment circuit (not depicted) which as explained in further detail with reference to FIGS. 3A and 3B, generates a current limit signal 226 in response to changes in supply capacity signal 228. In this manner, current regulator 205 dynamically maintains the VA limit for N+1 power supply 203 utilizing changes in current supply capacity of C.sub.1 202 through C.sub.n 206.

Turning now to FIG. 3A, there is depicted a schematic representation of a dynamic current limit adjustment circuit accounting for variations in N+1 power supply capacity in accordance with the system and method of the present invention. As illustrated in FIG. 3A, regulator circuit 300 includes an N+1 power supply 306 which is regulated through a power backplane circuit 304 while providing power to a system load 302. As illustrated in FIG. 3A, N+1 power supply 306 comprises three parallel power supplies (analogous to the power converter of FIG. 2) PS1 308, PS2 310, and PS3 312. Although not depicted in FIG. 3, each of these power supplies is connected to an AC input and provides power to load 302 via decoupling diodes. Within PS1 308, PS2 310, and PS3 312, reside VA limit circuits 352, 354, and 356 that include current sensing resistors RCS1 314, RCS2 316, and RCS3 318, respectively. In the depicted embodiment, RCS1 314, RCS2 316, and RCS3 318 serve as individual current regulation devices for each of PS1 308, PS2 310, and PS3 312.

FIG. 3B further illustrates the construction and operating characteristics of VA limit circuit 352 as may be utilized as any or all of VA limit circuits 352, 354, and 356. VA limit circuit 352 is comprised of sensing resistor RCS1 314 across which a current sense voltage, Vcs, is monitored such that the output current, I.sub.L, can be monitored and regulated in accordance with the teachings of the present invention. A threshold voltage signal, V.sub.T 350, is applied to an input impedance network comprising Rl1 364, Rl2 362, Rl3 366, and RCS1 314. V.sub.T 350 serves as the reference against which Vcs is compared in order to dynamically adjust the maximum allowable value for I.sub.L (I.sub.max) as necessary. With reference to FIGS. 3A and 3B, I.sub.max is defined as the value of I.sub.L at which the voltage levels at the inverting and non-inverting terminals of comparator 355 will be sufficiently offset, such that a shutdown signal 357 terminates operation of PS1 308. I.sub.max varies as a function of V.sub.T 350 in accordance with the following relation:

wherein k is a constant equal to [.vertline.Rl2.vertline./(.vertline.Rcs.vertline..times..vertline.Rl1.vert line.)]. It should be noted that relation (4) expresses the dependence of the maximum allowable value, I.sub.max, not the actual value of I.sub.L. As illustrated by FIG. 3B and relation (4), V.sub.T 350 provides a means by which I.sub.max may be adjusted in real-time. If I.sub.L exceeds I.sub.max, the VA output from the host power supply (i.e. the product of I.sub.L and the output voltage level from the supply) will exceed the pre-determined maximum allowable VA level, and a shutdown signal 357 from a comparator 355 will result.

Returning to FIG. 3A, and in an important feature of the present invention, each of PS1 308, PS2 310, and PS3 312 also provide a "power status" signal to power backplane circuit 304. PG1 320, PG2 322, and PG3 324 illustrate such power status signals which are generated within PS1 308, PS2 310, and PS3 312, utilizing devices depicted as sensors 210, 212, and 214 in FIG. 2. In one possible embodiment of the present invention, a current sense voltage signal such as Vcs (FIG. 3B) may be converted into a digital signal and utilized as a power status signal. As bimodal binary signals, power status signals 320, 322, and 324 indicate whether their respective power supplies are operating (i.e. power good) or not.

In the illustrated embodiment, while each of the parallel power supplies is operating normally, its corresponding power status signal remains high (logic 1). If power from one or more of the power supplies is interrupted, due to failure or removal, its power status signal drops from high to low (logic 0). PG1 320, PG2 322, and PG3 324 are fed through inverters into a detector circuit 328 comprising an equivalent resistance network 326 and a feedback amplifier 343. Detector circuit 328 senses and reacts to changes in the supply current capacity of N+1 power supply 306 as characterized by power status signals 320, 322, and 324. Having three binary inputs, detector circuit 328 operates as a multiple input logic switch driven in accordance with the states of PG1 320, PG2 322, and PG3 324. Resistance network 326 comprises switch transistors Q1 330, Q2 331, and Q3 333 which incrementally increase or decrease the equivalent resistance of the network in discrete units as determined by the resistance values of resistors R3 332, R2 334, R1 335 and RO 337. PG1 320, PG2 322, and PG3 drive Q1 330, Q2 331, and Q3 333, respectively. While PG1 320, PG2 322, and PG3 324 are set to a logic 1, the inverted inputs into Q1 330, Q2 331, and Q3 333 remain at a logic 0, thus maintaining Q1 330, Q2 331, and Q3 333 in a disabled or "off" state. If any of power status signals PG1 320, PG2 322, or PG3 324 go low, the corresponding input goes from logic 0 to a logic 1, resulting in one or more of the switches being switched on.

For example, shifting PG2 322 from a logic 1 (indicating PS2 310 currently operating) to a logic 0 (indicating PS2 310 no longer operating), will cause Q2 331 to switch on thus changing the equivalent resistance, R.sub.eq, of detector circuit 328 from R.sub.eq =RO to R.sub.eq =RO.vertline..vertline.R2 (RO 337 and R2 334 in parallel). Any additional failures (or removals) of parallel power supplies within N+1 power supply 306 would similarly reduce R.sub.eq in accordance with the number of resistors added in parallel. By detecting the number of operating power supplies within N+1 power supply 306, detector circuit 328 modulates R.sub.eq in accordance with a fault condition or power supply removal. As explained with reference to relation (5) below, the modulation of R.sub.eq serves as a supply capacity signal translation of the operating status provided by PG1 320, PG2 322, and PG3 324.

As further illustrated in FIG. 3A, the R.sub.eq of detector circuit 328 is applied to the inverting terminal of an operational amplifier (op-amp) M2 340 within feedback amplifier 343. M2 340 is biased by feedback resistor R.sub.f 344, and R.sub.eq, and V.sub.REF 342. The input/output amplification characteristics of a non-inverting amplifier such as M2 340 are well-known in the art. One such characteristic is the voltage gain, A.sub.v of a non-inverting amplifier as measured by the ratio of V.sub.T 350, to the input reference voltage, V.sub.REF 342. The threshold voltage level V.sub.T 350 will increase as R.sub.eq decreases in accordance with the following op-amp gain formula:

V.sub.T 350 is then fed back to VA limit circuits 352, 354, and 356 as depicted in FIG. 3B.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.