US 6,156,601 AGrant
Method of Forming DRAM Matrix of Basic Organizational Units Each With Pair of Capacitors With Hexagon Shaped Planar Portion
Issue Date:2000-12-05
•16 Claims
•5 Drawing Sheets
Abstract
A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.
Metadata
Assignee
- Hyundai Electronics Industries Co., Ltd.
Inventors
- Chang Jae Lee
- Won Suck Yang
- Kong Hee Park
Application Information
Application Number:US 3339610
Filing Date:1999-06-16
Priority Date:1996-07-31
Art Unit:282
Classifications
IPC:
H01L 2170H01L 218242
Field of Search:
438238;239;250;253;381;393;396
Patent Drawings (5 sheets)
Description
Background of the Invention
The present invention relates to a DRAM (Dynamic Random Access Memory), and more particularly, to a cell array of the DRAM.
Generally, with the integration of a semiconductor DRAM device, layouts and structures of cell arrays suitable for high integration thereof have been proposed.
A capacitor under bit line (CUB) structure applies to 16 Mb DRAM sizes or smaller, while a capacitor over bit line (COB) structure applies to 64 Mb DRAM sizes or greater.
FIGS. 1a and 1b depict a layout and a sectional view, respectively, showing a cell array of a conventional CUB structure.
As shown in FIGS. 1a and 1b, the CUB structure includes gate lines 2 arranged in rows on a substrate 1, gate insulator layers 2a, a node electrode 3 over and between the gate lines 2 and in contact with the substrate 1, a plate electrode 4 on the node electrode 3 (a capacitor dielectric between the plate electrode 4 and the node electrode 3 is not shown), an insulator layer 5a on the plate electrode 4, the gate insulator 2a, and the substrate 1, and a bit line 5 over and perpendicular to the gate lines 2. The active region is denoted by X.
That is, the CUB structure includes the bit line 5 formed on a capacitor having the node electrode 3 and the plate electrode 4.
In the CUB structure as aforementioned, in order to obtain a capacitor having a sufficient capacitance required for highly integrated DRAMs, the height of the capacitor must be high. However, this causes a problem in that an aspect ratio of a contact hole 6 of the bit line gets higher. This, in turn, causes difficulties in the technology relating to forming a conductive layer into of the contact hole 6 and patterning the bit line 5.
For this reason, a new layout for the cell array has been required for 64 M DRAMs.
FIGS. 2a and 2b show a layout and a sectional view, respectively, showing a cell array of a conventional COB structure.
As shown in FIGS. 2a and 2b, the COB structure includes gate lines 11 arranged in a row on a substrate 10, a bit line 12 perpendicular to the gate lines 11 and in contact with the gate insulating layers 11a and the substrate 10, a node electrode 13 in a rectangular form over and between the gate lines 11 and in contact with the substrate 10 and the gate insulating layers 11a, and a plate electrode 14 over the node electrode 13. A dielectric layer 15 is formed between the plate electrode 14 and the node electrode 13.
In the COB structure as aforementioned, since the bit line 12 is formed sooner than the capacitor, the capacitor region may include the bit line 12. As a result, the aspect ratio of the bit line contact hole 16 does not increase even if the height of the capacitor becomes high for high capacitance.
The cell array of the COB structure allows the effective area of the bit line to be incorporated into the capacitor region. It also allows the effective area of the capacitor to increase by increasing the height of the capacitor so that it can be used in a 64 M DRAM or a 256 M DRAM.
However, the cell array of the COB structure has several problems.
First, it is hard to mass produce DRAM devices using a technology which increases the effective area of the capacitor, because this goes against the prevailing trend of reducing the effective area of the cell in order to achieve a 1 G DRAM size or greater.
Second, shrinkage of the node electrode of the capacitor due to the use of a rectangular-shape pattern makes the electrode region of the capacitor smaller than its actual design.
Third, a narrow interval between the bit lines makes parasitic capacitance of the bit lines higher.
Thus, high capacitance of the cell capacitor is required to maintain the capacitance C.sub.S of the cell capacitor and the parasitic capacitance C.sub.B of the bit line, which have certain levels required for the design of the memory cell. However, it is not suitable for highly integrated devices.
Summary of the Invention
Accordingly, the present invention is directed to a DRAM device having a high dielectric ratio and high reliability that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a DRAM device which has improved speed.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the DRAM according to the present invention includes: a semiconductor substrate; an active region in the substrate including a first region having a first impurity region, a second region having a third impurity region, and a bent region between the first impurity region and the second impurity region, the bent region having a second impurity region; a first word line provided over and between the first impurity region and the second impurity region; a second word line provided over and between the second impurity region and the third impurity region; insulating layers on the substrate and on the word lines, having a first contact hole on the first impurity region, a second contact hole on the second impurity region, and a third contact hole on the third impurity region, respectively; a bit line electrically connected to the second impurity region through the second contact hole, extending across the word lines at the bent region; a first capacitor with a hexagon-shaped planar portion above the first region, electrically connected to the first impurity region through the first contact hole; and a second capacitor with a hexagon-shaped planar portion above the second region, electrically connected to the third impurity region through the third contact hole, wherein one side of the hexagon-shaped planar portion of the second capacitor is parallel to one side of the hexagon-shaped planar portion of the first capacitor, and the second contact hole is disposed between the first and second capacitors.
The objects of the present invention are also achieved by providing a method of forming a cell array of a DRAM which includes the steps of: arranging the contact holes such that a respective first contact hole, second contact hole, and third contact hole are connectable by an imaginary straight line; arranging the first word line between the first contact hole and the second contact hole; arranging the second word line between the second contact hole and the third contact hole so as to be symmetric with the first word line relative to the central point of the second contact hole; disposing the central point of the second contact hole to be on the central line of the bit line; arranging the bit line to be a straight line forming an angle .theta..sub.21 of 0.degree.<.theta..sub.21 <90.degree. counterclockwise and an angle .theta..sub.22 of 90.degree.<.theta..sub.22 <180.degree. clockwise against the respective center lines of the first and second word lines; and arranging the first and second capacitors such that the respective central points of the first and third contact holes are aligned with the central points of the first and second capacitors, respectively.
These and other objects of the present invention are also achieved by providing a method of forming a dynamic random access memory (DRAM), the DRAM including a plurality of bit lines and a plurality of capacitor pairs, the method comprising the steps of: forming a plurality of hexagon-shaped node electrodes into a first matrix over a substrate; forming a dielectric on said hexagon-shaped node electrodes; selectively forming plate electrodes to define said plurality of capacitor pairs; and selectively connecting said plurality of bit lines to said plate electrodes. The method further includes the steps of: forming a layer of electrode material over said substrate; and patterning said layer using a mask having a plurality of hexagonal apertures so as to form said plurality of hexagon-shaped node electrodes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
Brief Description of the Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together will the description serve to explain the principles of the drawings:
In the drawings:
FIGS. 1a and 1b provide a plane view and a sectional view, respectively, showing a cell array of a conventional CUB structure;
FIGS. 2a and 2b provide a plane view and a sectional view, respectively, showing a cell array of a conventional COB structure;
FIG. 3a is a plane view showing an array of components of a DRAM according to the present invention;
FIG. 3b is a sectional view taken along line III-III' of FIG. 3a;
FIG. 4 is a plane view showing a cell array of a DRAM according to the present invention; and
FIGS. 5a and 5b compare conventional and inventive plane views, respectively, to show how a capacitor's node electrode is distorted in shape relative to the pattern used to form it.
Detailed Description of the Preferred Embodiments
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
FIG. 3a is a plane view showing an array of components of a DRAM according to the present invention. FIG. 3b is a sectional view taken along the line III-III' of FIG. 3a.
As shown in FIGS. 3a and 3b, the DRAM according to the present invention comprises a semiconductor substrate 20, an active region 24, a first word line 25, a second word line 26, insulating layers 30a and 30b, a bit line 31, a first capacitor 32, and a second capacitor 33. The active region 24 includes a first (category) region 21 having a first impurity region, a second (category) region 22 having a third impurity region, and a bent region 23 between the first region 21 and the second region 22, having a second impurity region. The first word line 25 is formed on the substrate 20 and slightly over, but mostly between, the first impurity region and the second impurity region. The second word line 26 is formed on the substrate 20 and slightly over, but mostly between, the second impurity region and the third impurity region.
The insulating layer 30a, provided on the substrate 20 and the word lines 25 and 26, has a contact hole 28 on the second impurity region. The insulating 30b, provided on the substrate 20, the bit line 31, and the insulating layer 30a, has a first contact hole 27 on the first impurity region and a third contact hole 29 on the third impurity region. The bit line 31 is electrically connected to the second impurity region through the second contact hole 28 and extends partially over the word lines 25 and 26.
The first capacitor 32 is electrically connected to the first impurity region by conductive material 27a in the first contact hole 27 and has a hexagon-shaped planar portion centered substantially over the first region 21. The second capacitor 33 is electrically connected to the third impurity region by conductive material 29a in the third contact hole 29 and has a hexagon-shaped planar portion centered substantially over the third region 22. One side of the hexagon-shaped planar portion of the capacitor 33 parallels one side of the hexagon-shaped planar portion of the first capacitor 32. The second contact hole 28 is disposed between the first and second capacitors 32 and 33. The hexagon-planar portions are best seen in FIG. 3a.
The center of the bit line 31 is formed over the bent region 23 and intersects the central point of the second contact hole 28.
The bent region 23 of the active region 24 is preferably bent, or formed at an angle between and relative to, the central line of the first word line 25 and the central line of the second word line 26. The bent region 23 is preferably neither parallel to nor at right angles with the central lines of the word lines 25 and 26, i.e., the bit line 31 forms an oblique angle with the word lines 25 and 26, respectively.
The one side of the hexagonal planar portion shape of the first capacitor 32 and the one side of the hexagonal planar portion of the second capacitor 33 are disposed equidistantly from respective sides of the contact hole 28 or from the center of the contact hole 28.
An imaginary straight characteristic line connects the central point of the first contact hole 27, the central point of the second contact hole 28, and the central point of the third contact hole 29. Such imaginary characteristic lines are preferably parallel. Similarly, the bit lines e.g., 31 of FIG. 3a or 51 of FIG. 4, are preferably parallel.
The planar portions of the first and second regions 21 and 22 in the active region 24 preferably have rectangular shapes, respectively.
The central line of the bit line 31 defining the bent region 23 in the active region 24 is not parallel to the imaginary line connecting the central points of the contact holes 27, 28 and 29, rather it is oblique.
The first contact hole 27 and the third contact hole 29 are preferably aligned with the respective center lines of the hexagonal planes of the first and second capacitors 32 and 33. The center of the second contact hole 28 is preferably aligned with the center of the bent region 23.
Further, the first region 21 of the active region 24 crosses the first word line 25 preferably at a right angle. The bent region 23 extends at an acute angle or right angle from the end of the first region 21 thereby forming an obtuse or right angle with the first region 21. The second region 22 extends at an acute angle or right angle from the end of the bent region 23 thereby forming an obtuse or right angle with the bent region 23. The second region 22 preferably crosses the second word line 26 at a right angle.
The first word line 25 and the second word line 26 are preferably symmetrical with respect to the second contact hole 28.
The central line of the bit line 31 forms an angle .theta..sub.1 of 0.degree.<.theta..sub.1 <90.degree. counterclockwise and an angle .theta..sub.2 of 90.degree.<.theta..sub.2 <180.degree. clockwise against the respective central lines of the first word line 25 and the second word line 26.
The first impurity region at the first region 21, the second impurity region at the bent region 23, and the first word line 25 provide a first transistor. The second impurity region at bent region 23, the third impurity region at the third region 22, and the second word line 26 provide a second transistor.
The first, second and third contact holes 27, 28 and 29 preferably have substantially circular shapes in cross section. The word lines 25 and 26 and a portion of the bit line 31 lie at the same level. The first contact hole 27 and the third contact hole 29 are preferably disposed at the same distance from the corresponding bit line 31.
The node electrode 34a and the plate electrode 34c of the capacitors 32 and 33 include any one of metal materials having high insulating resistance when oxidized. For example, the metal materials may be Pt, RuO.sub.2, IrO.sub.2, and the like. A high dielectric layer 34b of the capacitors 32 and 33 preferably has a single grain.
The node electrode 34a and the high dielectric layer 34b of the capacitors 32 and 33 interact. Their component materials are selected by considering crystal orientation of the dielectric material. The high dielectric layers preferably include any one of Ta.sub.2 O.sub.5, SrTiO.sub.3, BaTiO.sub.3, PbZrO.sub.3, BST((Ba,Sr)TiO.sub.3), PZT(Pb(Zr,Ti)O.sub.3) PLZT((Pb,La) (Zr,Ti)O.sub.3), or PNZT((Pb,Nb) (Zr,Ti)O.sub.3)
FIG. 4 is a plane view showing a cell array of a DRAM according to the present invention.
As shown in FIG. 4, the DRAM comprises a semiconductor substrate (not labelled), a plurality of first word lines 45, a plurality of second word lines 46, an insulating layer (not labelled), a plurality of bit lines 51, a plurality of first capacitors 52, and a plurality of second capacitors 53. The semiconductor substrate has an active region 44 which includes a first region 41 having a first impurity region, a second region 42 having a third impurity region, and a bent region 43 disposed between the first region 41 and the second region 42 and having a second impurity region.
In FIG. 4, a plurality of the first word lines 45 are formed between respective first impurity regions and second impurity regions. A plurality of the second word lines 46 are formed between respective second impurity regions and third impurity regions. The insulating layer formed on the substrate and on the word lines 45 and 46 has a plurality of first contact holes 47 on the first impurity region, a plurality of second contact holes 48 on the second impurity region, and a plurality of third contact holes 49 on the third impurity region. A plurality of the bit lines 51 are electrically connected to the second impurity regions through corresponding second contact holes 48, and cross the respective first and second word lines 45 and 46 and the bent region 43 of the active region 44.
Also in FIG. 4, a plurality of the first capacitors 52 are electrically connected to the first impurity regions through corresponding first contact holes 47, and preferably have hexagonal planar portions substantially centered above the first regions 41. A plurality of the second capacitors 53 are electrically connected to the third impurity regions through corresponding third contact holes 49, and preferably have hexagonal planar portions substantially centered above the second regions 42. One side of the hexagonal shape of the planar portions of the second capacitors 53 is parallel to one side of the hexagonal shape of the planar portions of the first capacitors 52. The second contact holes 48 are disposed between the first and second capacitors 52 and 53.
The respective bit lines 51 connect to the central points of the second contact holes 48 to obliquely cross the word lines 45 and 46.
The first contact holes 47 and the third contact holes 49 adjacent to the respective bit lines 51 are preferably disposed at the same distance from the bit lines 51.
The central lines of the bit lines 51 are arranged above the bent regions 43 and intersect the central points of the second contact holes 48.
The bent region 43 of the respective active regions 44 is bent between the central line of the first word line 45 and the central line of the second word line 46.
The one side of the hexagonal shape of the first capacitors 52 and the one side of the hexagonal shape of the second capacitors 53 are disposed equidistant from the sides of the corresponding second contact hole 48. Imaginary straight lines connect the central points of the first contact holes 47, the second contact holes 48, and the third contact holes 49. These imaginary lines are parallel to each other and are oblique to the central lines of the bent regions 43, and cross the bent regions 43 at the central points of the corresponding second contact holes 48. The respective planar portions of the first region 41 and the second region 42 preferably have rectangular shapes.
The first contact holes 47 and the third contact holes 49 are preferably aligned with the respective centers of the hexagonal shapes of the first and second capacitors 52 and 53. The centers of the second contact holes 48 are preferably aligned with respective centers of the bent regions 43.
The first regions 41 of the active region 44 cross the first word lines 45, preferably at right angles. The bent region 43 extends at an angle between an oblique angle and a right angle from the end of the first region 41. The second region 42 extends at an acute angle or a right angle from the end of the bent region 43; crosses the second word lines 46 at right angles.
The first word lines 45 and the second word lines 46 are symmetrically disposed with respect to a corresponding second contact hole 48.
The central lines of the bit lines 51 form an angle .theta..sub.11 of 0.degree.<.theta..sub.11 <90.degree. counterclockwise and an angle .theta..sub.12 of 90.degree.<.theta..sub.12 <180.degree. clockwise against the respective central lines of the first word line 45 and the second word line 46.
The first impurity region at the first region 41, the second impurity region at the bent region 43, and the first word line 45 provide a first transistor. The second impurity region at the bent region 43, the third impurity region at the second region 42, and the second word line 46 provide a second transistor.
The first, second and third contact holes 47, 48 and 49 preferably have substantially circular shapes in cross-section. The word lines 45 and 46 and a portion of the bit lines 51 lie in the same level. The first contact hole 47 and the third contact hole 49 are preferably disposed at the same distance from the corresponding bit line 51.
The node electrode and the plate electrode of the capacitors 52 and 53 include any one of metal materials having high insulating resistance when oxidized. For example, the metal materials may be Pt, RuO.sub.2, IrO.sub.2, and the like.
High dielectric layers (not labelled) of the capacitors 52 and 53 preferably have a single grain, respectively. The node electrode (not labelled) and the high dielectric layers of the capacitors 52 and 53 interact. Their component materials are selected by considering crystal orientation of the dielectric material. The high dielectric layers preferably include any one of Ta.sub.2 O.sub.5, SrTiO.sub.3, BaTiO.sub.3, PbZrO.sub.3, BST, PZT, PLZT, or PNZT.
An alternative description of FIGS. 4 and 3a follows. Active regions of the substrate each include one of the plurality of first doped regions, one of the plurality of second doped regions and one of the plurality of third doped regions. A footprint of each of the active regions is non-linearly shaped. The footprint is shaped like an inverted letter Z that has been partially uncoiled such that ends of the inverted Z-shape perpendicularly intersect one of the plurality of first word lines and one of the plurality of second word lines, respectively. A center section of the inverted Z-shape obliquely intersects one of the plurality of straight bit lines.
As aforementioned, the reason why the node electrode of the capacitor has a hexagonal shape will be described with reference to FIGS. 5a and 5b.
FIG. 5a is a plane view contrasting the rectangular pattern (used in the conventional process of patterning to form a conventional node electrode) and the resulting conventional node electrode shape.
As shown in FIG. 5a, a conventional art cell has a node electrode 60 suitable for its array, which enhances an electrode region.
However, the node electrode 60 makes the capacitor region smaller due to heavy shrinkage at an edge of the rectangle-shaped pattern 62 by dispersion of light during the photolithographic patterning process. Thus, the cell structure having a conventional node electrode 60 formed from a conventional rectangular-shape pattern 62 causes a reduction in the effective area of the capacitor. That is, a dead space 68 unused by the capacitor region increases, which increases the unusable interior region 69 where four rectangular-shape pattern edges join at one place.
Meanwhile, as shown in FIG. 5b, a cell structure according to the present invention having a hexagon-shaped node electrode 64 formed from a hexagonal pattern 66 enhances the area of the capacitor since three hexagonal pattern edges join at one place. The dead space 70 is smaller as compared to the dead space 68 of the conventional art node electrodes of FIG. 5a, so that the unusable interior region 71 is smaller than region 69.
The DRAM according to the present invention has the following effects.
First, a cell according to the present invention can be operated with a significantly lower capacitance C.sub.S of the cell capacitor and a significantly lower parasitic capacitance C.sub.B of the bit line.
Second, since the parasitic capacitance of the bit line of a cell according to the present invention is small, the speed as well as the reliability of the cell operation is improved.
Third, a cell according to the present invention has an interval between the bit lines that is great enough to significantly reduce the parasitic capacitance there between.
Fourth, the hexagon-shaped node electrode i.e., the node electrode formed from a hexagonal-shaped pattern, makes the pattern shrinkage smaller so as to enhance the area of the capacitor thereby decreasing dead space between capacitors.
Fifth, it is likely that high dielectric layers of the respective capacitors of the present invention will be formed with a single grain due to the crystal boundary having three central points based on the hexagonal-shaped node electrode.
Finally, since the capacitor includes a high dielectric layer having a single grain, the dielectric ratio is high and leakage current is low.
It will be apparent to those skilled in the art that various modifications and variations can be made in the DRAM of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of the invention provided they come within the scope of the appended claims and their equivalents.
Claims
What is claimed is:
1. A method of forming a cell array of a DRAM having a semiconductor substrate having a first impurity region, a second impurity region, and a third impurity region, a first word line electrically connected to the first and second impurity regions, a second word line electrically connected to the second and third impurity regions, a first insulating layer having a second contact hole, a second insulating layer having a first contact hole and a third contact hole, a bit line electrically connected to the second impurity region through the second contact hole, a first capacitor, on the second insulating layer, with a hexagon-shaped planar portion above the first region, electrically connected to the first impurity region through the first contact hole, and a second capacitor, on the second insulating layer, with a hexagon-shaped planar portion above the second region, electrically connected to the third impurity region through the third contact hole, the method comprising the steps of: arranging the contact holes such that a respective first contact hole, second contact hole, and third contact hole are connectable by the imaginary straight line; arranging the first word line between the first contact hole and the second contact hole; arranging the second word line between the second contact hole and the third contact hole so as to be symmetric with the first word line relative to the central point of the second contact hole; disposing the central point of the second contact hole to be on the central line of the bit line; arranging the bit line to be a straight line forming an angle .theta..sub.21 of 0.degree.<.theta..sub.21 <90.degree. counterclockwise and an angle .theta..sub.22 of 90.degree.<.theta..sub.22 <180.degree. clockwise against the respective center lines of the first and second word lines; and arranging the first and second capacitors such that the respective central points of the first and third contact holes are aligned with the central lines of the first and second capacitors, respectively, and so that one side of the hexagon-shaped planar portion of the second capacitor is parallel to one side of the hexagon-shaped planar portion of the first capacitor.
2. A method of forming a dynamic random access memory (DRAM), the DRAM including a plurality of bit lines and a plurality of capacitor pairs, the method comprising the steps of: providing a substrate; providing a plurality of word lines on said substrate; providing said plurality of straight bit lines over said plurality of word lines at an oblique angle of intersection therewith; forming a plurality of hexagon-shaped node electrodes into a first matrix over said plurality of bit lines, said plurality of word lines and said substrate; forming a dielectric on said hexagon-shaped node electrodes; selectively forming plate electrodes to define said plurality of capacitor pairs; and selectively connecting said plurality of bit lines to said plate electrodes; and wherein: said substrate has a plurality of first doped regions, a plurality of second doped regions and a plurality of third doped regions; said plurality of word lines includes a plurality of first word lines; and a plurality of second word lines; said step of forming a plurality of hexagon-shaped node electrodes as said first matrix over a substrate includes establishing a first set of said plurality of hexagon-shaped node electrodes as plurality of first node electrodes, and establishing a second set of said plurality of hexagon-shaped node electrodes as a plurality of second node electrodes; and said method further comprises: organizing said DRAM as a plurality of basic organizational units each having one of said capacitor pairs; arranging said plurality of organizational units as a second matrix; establishing each said capacitor pair as having one of said first node electrodes and one of said second node electrodes; forming of said basic organizational units as follows: alternately forming one of said first word lines and one of said second word lines as parallel lines on said substrate; forming said first word line between one of said first doped regions and one of said second doped regions to define a first transistor; forming said second word line between said second doped region of said first transistor and one of said third doped regions to define a second transistor; forming one of said bit lines on said second doped region of said substrate at an oblique angle to said first word line and second word line; forming the first node electrode of said capacitor pair of said basic organizational unit to overlie said first doped region and said first word line; substantially centering said first node electrode over said first doped region; connecting said first node electrode to said first doped region via a first contact hole; forming the second node electrode of said capacitor pair of said basic organizational unit to overlie said third doped region and said second word line; substantially centering said second node electrode over said third doped region; and connecting said second node electrode to said third doped region via second contact hole.
3. The method of claim 2, wherein said step of forming a plurality of hexagon-shaped node electrodes includes the steps of: forming a layer of electrode material over said substrate; and patterning said layer using a mask having a plurality of hexagonal apertures so as to form said plurality of hexagon-shaped node electrodes.
4. The method of claim 2, wherein said step of forming said basic organizational units includes: forming said first word line partially on one of said first doped regions and partially on one of said second doped regions to define a first transistor; and forming said second word line partially the same second doped region as said first word line and partially on one of said third doped regions to define a second transistor.
5. The method of claim 2, wherein said step of forming said basic organizational units includes: forming a first side of said first hexagon-shaped node electrode of said basic organizational unit to be parallel to a first side of said second hexagon-shaped node electrode of said basic organizational unit; and forming said first side of said first hexagon-shaped node electrode and said first side of said hexagon-shaped node electrode of said basic organizational unit to be equidistant from a center point of said second doped region.
6. The method of claim 2, wherein said step of selectively forming plate electrodes includes using a single plate electrode for a given capacitor pair by shaping said single plate electrode to overlie said first hexagon-shaped node electrode and said second hexagon-shaped node electrode of said basic organizational unit.
7. The method of claim 2, wherein: a center point of each of said first doped region, second doped region and third doped region of said basic organizational unit are connectable by an imaginary straight characteristic line; and said characteristic lines of each of said basic organizational units being parallel.
8. The method of claim 2, further comprising: forming said plurality of bit lines to be parallel.
9. The method of claim 1, wherein said bit line and said first and second word lines are straight lines.
10. The method of claim 2, wherein said plurality of word lines are straight lines.
11. The method of claim 1, wherein said hexagon-shaped planar portions are symmetric.
12. The method of claim 2, wherein said hexagon-shaped planar portions are symmetric.
13. The method of claim 1, wherein active regions of said substrate each include one of said plurality of first doped regions, one of said plurality of second doped regions and one of said plurality of third doped regions, and wherein a footprint of each of said active regions is non-linearly shaped.
14. The method of claim 13, wherein said footprint is shaped like an inverted letter Z that has been partially uncoiled such that ends of the inverted Z-shape perpendicularly intersect one of said plurality of first word lines and one of said plurality of second word lines, respectively while a center section of said inverted Z-shape obliquely intersects one of said plurality of straight bit lines.
15. The method of claim 2, wherein said substrate has a plurality of active regions, a footprint of each of which is non-linearly shaped.
16. The method of claim 1, wherein said footprint is shaped like an inverted letter Z that has been partially uncoiled such that ends of the inverted Z-shape perpendicularly intersect two of the plurality of word lines, respectively, while a center section of said inverted Z-shape obliquely intersects one of said plurality of bit lines.
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Non-Patent Literature (2)
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