Look-Ahead Carry Structure With Homogeneous CLB Structure and Pitch Larger Than CLB Pitch

The present invention relates to a carry logic structure for use in a field programmable gate array (FPGA).

FPGAs typically use logic circuits to perform various a binary arithmetic function, such as addition. FIG. 1 is a diagram of a typical carry logic circuit 1. Carry logic circuit 1, which includes carry circuitry 2 and sum circuitry 3, receives three input signals A.sub.i, B.sub.i and C.sub.i and provides two output signals S.sub.i and C.sub.i+1. Carry logic circuit 1 can implement various arithmetic operations, including the addition of two digital numbers represented by input signals A.sub.i and B.sub.i. When adding input signals A.sub.i and B.sub.i, input signal C.sub.i is used as a carry signal which has a digital value which represents the result of the addition of two bits at a previous bit position. Output signal S.sub.i is a digital value which represents the sum of input signals A.sub.i, B.sub.i and C.sub.i. Output signal C.sub.i+1 is a digital value corresponding to the carry result of the addition of input signals A.sub.i, B.sub.i, and C.sub.i. Table 1 is a truth table defining an addition operation within carry logic circuit 1.

Logic circuit 1 has been implemented within FPGAs using various logic structures. FIG. 2A is a schematic diagram of a conventional carry logic circuit. Input signals A.sub.i and B.sub.i are routed through control logic 12 to a hard-wired exclusive OR gate 14. This circuit is also discussed in U.S. Pat. No. 5,267,187, incorporated herein by reference. The output terminal of exclusive OR gate 14 is coupled to the control terminal of multiplexer 16. Multiplexer 16 receives an input signal (typically either the A.sub.i or B.sub.i signal) on one input terminal. The other input terminal of multiplexer 16 is coupled to receive a carry input signal C.sub.i from a previous carry logic circuit (not shown). The carry signal C.sub.i+1 routed through multiplexer 16 is provided to a subsequent carry logic circuit (not shown) as a carry input signal C.sub.i. Signals A.sub.i, B.sub.i and C.sub.i are provided to function generator 18 of the FPGA. In response, function generator 18 generates sum signal S.sub.i, which is equal to A.sub.i XOR'ed with B.sub.i, XOR'ed with C.sub.i.

FIG. 2B is a schematic diagram of another conventional carry logic circuit. Logic unit 11 includes three two-input logic gates XOR gate 13, OR gate 15, and AND gate 17, which generate the XOR, OR, and AND functions respectively of input signals A.sub.i and B.sub.i. XOR gate 13 provides the half sum P.sub.i. Multiplexer 16 selects one of the AND and OR functions of input signals A.sub.i and B.sub.i as determined by carry-in signal C.sub.i. When C.sub.i is logic 0, multiplexer 16 selects the output of AND gate 17, which is logic 1 only when A.sub.i and B.sub.i are both logic 1. Thus multiplexer 16 carry output C.sub.i.about.1 is logic 1 when C.sub.i does not indicate a carry but both input signals are logic 1. When carry input signal C.sub.i is logic 1, the carry output C.sub.i.about.1 is logic 1 if either input is logic 1. Thus the structure of FIG. 12 is another structure for generating fast carry signals.

To provide a circuit which adds digital numbers having a plurality of bits, a plurality of carry logic circuits are typically coupled together in a serial manner, such that the carry signal C.sub.i.about.1 provided by each carry logic circuit is propagated to a subsequent carry logic circuit as a carry input signal C.sub.i. In the carry logic circuit of FIG. 2A, carry signal C.sub.i.about.1 is created by routing a signal (either the A.sub.i or B.sub.i input signal or carry input signal C.sub.i) through multiplexer 16. Multiplexer 16 delays the propagation of carry signal C.sub.i.about.1. In the carry logic circuit of FIG. 2B, carry signal C.sub.i.about.1 is created by routing the selected AND or OR function of the input signals to the output of multiplexer 16. As in FIG. 2A, multiplexer 16 delays the propagation of carry signal C.sub.i.about.1.

For each additional carry logic circuit connected in series, additional carry signal propagation delay is introduced by an additional multiplexer.

It would therefore be desirable to have a carry logic circuit for use in an FPGA which reduces carry signal propagation delay.

Accordingly, the present invention provides an FPGA having at least one carry logic circuit having two carry chains. One carry chain is initiated with logic 0 and the other is initiated with logic 1. The two chains extend for several bit positions, for example four bit positions. A multiplexer at the end is controlled by a carry-in signal to select between the two carry chains.

This carry logic circuit includes a first input lead coupled to receive a first input signal (A.sub.i), a second input lead coupled to receive a second input signal (B.sub.i), a first carry chain lead coupled to receive a first carry chain signal (CAi), a second carry chain lead coupled to receive a second carry chain signal (CBi), a third carry chain lead, a fourth carry chain lead, a carry input lead coupled to receive a carry input signal (Ci), and a local carry input lead for providing a local carry input signal (Ci+1) to a logic forming element of another carry logic circuit.

A programmable function generator of the FPGA is coupled to the first and second input leads. The function generator is programmed to perform an exclusive OR operation. In a particular embodiment, the function generator generates the exclusive OR signal in response to the first and second input signals.

The propagate signal is provided to control a first multiplexer and a second multiplexer. The propagate signal causes the first and second multiplexers to couple the first input lead to the third and fourth carry chain leads, respectively, when and only when the first input value is equal to the second input value. The propagate signal further causes the first multiplexer to couple the first carry chain lead to the third carry chain lead and causes the second multiplexer to connect the second carry chain lead to the fourth carry chain lead when and only when the first input signal is not equal to the second input signal.

The present invention also includes a third multiplexer for coupling either the third carry chain lead or the fourth carry chain lead to the local carry input terminal (Ci+1) in response to said carry input signal (Cin). When more than one carry logic circuit is provided in accordance with the present invention, each carry logic circuit has a multiplexer corresponding to the previously described third multiplexer. In such an embodiment, each of these multiplexers is controlled by the carry input signal, which is supplied to each multiplexer in parallel.

The carry logic signal can also include a carry output lead for transmitting a carry output signal from the carry logic circuit and a carry output signal selection circuit coupled to the carry output lead, the third carry chain lead, the fourth carry chain lead and the carry input lead. In such an embodiment, the carry output selection circuit transmits a signal from either the third or fourth carry chain leads to the carry output lead in response to the carry input signal. The carry input signal is provided to the carry output signal selection circuit and the third multiplexer in parallel. As a result, the carry signal propagation delay is minimized.

In another embodiment, delay is further reduced by generating conditional sums. In this embodiment, as before, the carry logic circuit includes two carry chains and a multiplexer for selecting between the carry chains.

In contrast to the first embodiment, a first conditional sum logic gate coupled to receive a first carry chain signal (CAi), a second conditional sum logic gate coupled to receive a second carry chain signal (CBi), both conditional sum logic gates coupled to receive a propagate signal (Pi), and a select multiplexer for selecting between output signals of the conditional sum logic gates and controlled by a carry input signal of a local logic unit.

In a further embodiment, the fast conditional sum is applied to an FPGA in which the carry-out signal is generated by a multiplexer receiving inputs from the AND and OR of bit input signals and a control signal from the carry-in signal. The sum is generated as a conditional sum. One potential sum is the XOR of the two input signals and the first carry-in signal. The other potential sum is the XOR of the two input signals and the second carry-in signal. In yet another embodiment, the carry is selected prior to generating the sum, and two carry-out signals are generated by multiplexers receiving inputs from the AND and OR of bit input signals and respective control signals from the carry-in signal on the two carry chains.

In another embodiment of the present invention, a carry logic circuit is provided for an array of configurable logic blocks (CLBs). Each of the CLBs includes an array of logic cells arranged in rows and columns. At least one column of logic cells includes a carry output signal selection circuit. At least one other column of logic cells includes a carry initialization circuit. The locations of the carry output signal selection circuits and carry initialization circuits are identical in each of the CLBs, such that each of the CLBs has an identical layout. Dedicated routing circuitry is provided for column shifting the carry chains between vertically adjacent CLBs. Column shifting is performed such that a column of logic cells in one CLB is coupled to a non-corresponding column of logic cells in a vertically adjacent CLB.

In a particular example, each CLB includes two rows and two columns of logic cells. Within each CLB, a carry initialization circuit is provided for the first column of logic cells, and a carry output signal selection circuit is provided for a second column of logic cells. The routing circuitry connects the first column of logic cells in a first CLB to the second column of logic cells in a second vertically adjacent CLB. Similarly, the routing circuit connects the second column of logic cells in the first CLB to the first column of logic cells in the second CLB. As a result, four logic cells are connected between the carry initialization circuit in the first CLB and the carry output signal selection circuit in the second CLB. In this example, the pitch of each carry chain is equal to two CLBs. The present invention will be more fully understood in light of the following detailed description taken together with the drawings.

FIGS. 1, 2A, and 2B are schematic diagrams of conventional carry logic circuits.

FIGS. 3 and 4 are schematic diagrams of carry logic circuits.

FIG. 5 is a schematic diagram of a carry logic circuit in accordance with one embodiment of the present invention.

FIG. 6 is a schematic diagram of a 4-bit carry logic structure using two carry chains in accordance with one embodiment of the present invention.

FIG. 7 is a schematic diagram of an optional carry output signal selection circuit.

FIGS. 8-10 show schematic diagrams of alternative embodiments of the carry out circuit of the invention.

FIG. 11 is a schematic diagram of a 4-bit carry logic structure using two carry chains with conditional sum in accordance with another embodiment of the present invention.

FIG. 12 is a schematic diagram of a 4-bit carry logic structure using two carry chains with conditional sum in which the carry signal is formed from the AND and OR function of bit input signals.

FIG. 13 is a schematic diagram of another 4-bit carry logic structure in which two carry signals are formed from the AND and OR function of bit input signals and where the sums and carry output are formed using carry select.

FIG. 14 is a block diagram of a CLB that is used to construct a carry logic system in accordance with another embodiment of the present invention.

FIG. 15 is a block diagram illustrating two vertically adjacent CLBs with connecting routing circuitry in accordance with one embodiment of the present invention.

FIG. 16 is a block diagram illustrating four vertically adjacent CLBs, each having a 2.times.4 array of logic cells in accordance with one embodiment of the present invention.

FIG. 17 is a block diagram illustrating four vertically adjacent CLBs, each having a 2.times.4 array of logic cells in accordance with another embodiment of the present invention.

FIG. 3 is a schematic diagram of carry logic circuit 20 for use in an FPGA. Input signals A.sub.i and B.sub.i are provided to function generator 21 of the FPGA. Function generator 21 is programmed to implement control logic 22 and exclusive OR gate 24. The output signal of exclusive OR gate 24 is routed to the control terminal of multiplexer 26 and to an input terminal of exclusive OR gate 28. Exclusive OR gate 28 can be hard-wired (not shown) or implemented by programming another function generator 29. Input signal B.sub.i is provided to one input terminal of multiplexer 26 and carry in signal C.sub.i is provided to the other input terminal of multiplexer 26. The signal routed through multiplexer 26 is provided to a subsequent carry logic circuit (not shown) as carry signal C.sub.i.about.1. Carry input signal C.sub.i is also provided to an input terminal of exclusive OR gate 28. In response, exclusive OR gate 28 provides sum signal S.sub.i.

Because function generator 29 can be programmed to implement logic functions in addition to an exclusive OR, flexibility is added to carry logic circuit 20. This in turn provides flexibility to an FPGA which uses carry logic circuit 20. However, carry logic circuit 20 does not solve the problem of carry signal propagation delay.

FIG. 4 is a schematic diagram of yet another carry logic circuit 40. Input signals A.sub.i and B.sub.i are provided to function generator 41 which is programmed to implement control logic 42 and exclusive OR gate 44. The output signal of exclusive OR gate 44 is provided to an input terminal of multiplexer 46. The other input terminal of multiplexer 46 is coupled to receive a signal from configurable bit latch 48. Configurable bit latch 48 is programmable to provide a logic high or logic low signal to multiplexer 46. The control terminal of multiplexer 46 is coupled to receive a signal from configurable bit latch 50.

The signal routed through multiplexer 46 is provided to the control terminal of multiplexer 52 and to an input terminal of exclusive OR gate 60. To operate carry logic circuit 40 as an adder circuit in accordance with Table 1, configurable bit latch 50 is programmed to couple exclusive OR gate 44 to the control terminal of multiplexer 52. Carry input signal C.sub.i is provided to the other input terminal of exclusive OR gate 60 and to an input terminal of multiplexer 52. The other input terminal of multiplexer 52 is coupled to multiplexer 54. Multiplexer 54 routes either input signal B.sub.i or a signal generated by configurable bit latch 56. Multiplexer 54 is controlled by a signal generated by configurable bit latch 58. To operate carry logic circuit 40 as an adder circuit in accordance with Table 1, configurable bit latch 58 is programmed to route input signal B.sub.i to multiplexer 52. The carry signal C.sub.i.about.1 routed through multiplexer 52 is provided to a subsequent carry logic circuit (not shown) as a carry in signal C.sub.i of the subsequent carry logic circuit. The output signal of exclusive OR gate 60 is transmitted as sum signal S.sub.i.

Because multiplexers 46 and 54 can be programmed to route predefined logic signals (provided by configurable bit latches 48 and 56), flexibility is added to carry logic circuit 40. This in turn provides flexibility to an FPGA which uses carry logic circuit 40. However, carry logic circuit 40 does not solve the problem of carry signal propagation delay.

FIG. 5 is a schematic diagram of carry logic circuit 100 in accordance with one embodiment of the present invention. Carry logic circuit 100 includes multiplexers 103, 104 and 131, function generators 121 and 151, and exclusive OR gates 125 and 141. Each of multiplexers 103, 104 and 133 has a control terminal, a "0" input terminal, a "1" input terminal and an output terminal. The signal applied to the control terminal determines whether the "0" input terminal or the "1" input terminal is coupled to the output terminal. A logic "0" signal applied to the control terminal causes the "0" input terminal to be coupled to the output terminal, and a logic "1" signal applied to the control terminal causes the "1" input terminal to be coupled to the output terminal.

Input signals A.sub.i and B.sub.i, which are typically product terms received from logic forming circuitry of an FPGA, are provided to function generator 121. Function generator 121 is a programmable circuit, such as a look-up table, which is present within a configurable logic block (CLB) of the FPGA. In the embodiment illustrated, function generator 121 is programmed to implement exclusive OR gate 125. The output signal of exclusive OR gate 125 is a propagate signal P.sub.i which is provided to the control terminals of multiplexers 103 and 104 and to an input terminal of exclusive OR gate 141. Exclusive OR gate 141 is implemented by function generator 151 of the FPGA on which carry logic circuit 100 is located. Exclusive OR gate 141 can alternatively be a hard-wired exclusive OR gate.

Input signal A.sub.i is also provided to the "0" input terminals of multiplexers 103 and 104. The "1" input terminals of multiplexers 103 and 104 are connected to receive carry chain signals CA.sub.i and CB.sub.i, respectively. The signals transmitted to the output terminals of multiplexers 103 and 104 are labeled as carry chain signals CA.sub.i.about.1 and CB.sub.i.about.1, respectively.

Carry chain signal CA.sub.i is provided to the "0" input terminal of multiplexer 131, and carry signal CB.sub.i is provided to the "1" input terminal of multiplexer 131. The control terminal of multiplexer 131 is coupled to receive express carry input signal C.sub.in. The output terminal of multiplexer 131 is coupled to the other input terminal of exclusive OR gate 141. The signal routed from multiplexer 131 to exclusive OR gate 141 is designated as local carry input signal C.sub.i. The output signal of exclusive OR gate 141 is designated as sum signal S.sub.i.

Express carry input signal C.sub.in is transmitted through carry logic circuit 100 without passing through circuit elements, such as multiplexers, which can cause signal delay. As described in more detail below, this feature allows signals to be propagated through carry logic circuit 100 more quickly than in conventional carry logic circuits.

FIG. 6 is a schematic diagram illustrating a 4-bit carry logic structure 500 which includes four cascaded carry logic circuits 100, 200, 300 and 400. Carry logic circuits 200, 300 and 400 are each identical to carry logic circuit 100 (FIG. 5). Carry logic circuits 200, 300 and 400 include multiplexers 105-110, 132-134, function generators 122-124 and 152-154, and exclusive OR gates 126-128 and 142-144. Carry logic structure 500 also includes carry chain initialization circuit 115 and carry output signal selection circuit 160. Carry chain initialization circuit 115 includes multiplexers 101-102 and configurable bit latches 111-113. Carry output signal selection circuit 160 includes AND gate 161, multiplexer 162 and amplifying buffer 163.

Express carry input signal C.sub.in is provided to each of multiplexers 131-134 in parallel. Express carry input signal C.sub.in is also provided to carry output signal selection circuit 160. Carry output signal selection circuit 160 is the only series connected circuitry that causes significant delay in the transmission of carry output signal C.sub.out.

Multiplexers 103, 105, 107 and 109 form a first carry chain through carry logic structure 500 and multiplexers 104, 106, 108 and 110 form a second carry chain through carry logic structure 500. Each carry chain propagates a series of carry chain signals. Thus, the first carry chain propagates carry chain signals CA.sub.i, CA.sub.i+1, CA.sub.i+2, CA.sub.i+3 and CA.sub.i+4 and the second carry chain propagates carry chain signals CB.sub.i, CB.sub.i+1, CB.sub.i+2, CB.sub.i+3, and CB.sub.i+4. Carry chain signals CA.sub.i and CB.sub.i are used to determine local carry signal C.sub.i, carry chain signals CA.sub.i+1 and CB.sub.i+1 are used to determine local carry signal C.sub.i+1, carry chain signals CA.sub.i+2 and CB.sub.i+2 are used to determine local carry signal C.sub.i+ 2, and carry chain signals CA.sub.i+3 and CB.sub.i+3 are used to determine local carry signal C.sub.i+3. Carry chain signals CA.sub.i+ 4 and CB.sub.i+4 are provided to carry output signal selection circuit 160.

Within carry output signal selection circuit 160, carry chain signal CB.sub.i+4 is provided to the "0" input terminal of multiplexer 162 and express carry input signal C.sub.in is provided to the "1" input terminal of multiplexer 162. AND gate 161 is connected to receive carry chain signal CB.sub.i.sub.4 and the inverse of carry chain signal CA.sub.i+4. The output terminal of AND gate 161 is connected to the control terminal of multiplexer 162. The output terminal of multiplexer 162 is connected to buffer 163. The output signal of buffer 163 is designated as carry output signal C.sub.out. Carry output signal C.sub.out is provided to a subsequent carry logic structure (not shown) as an express carry input signal (such as express carry input signal C.sub.in).

Carry logic structure 500 can be programmed to add the four least significant bits of two digital numbers. Alternatively, carry logic structure 500 can be programmed to add four bits other than the four least significant bits of two digital numbers. The programming of carry logic structure 500 is carried out by carry chain initialization circuit 115. In carry chain initialization circuit 115, the "0" input terminals of multiplexers 101 and 102 are coupled to receive a carry initialization signal on line 114. The "1" input terminals of multiplexers 101 and 102 are coupled to receive signals from configurable bit latches 111 and 112, respectively. The control terminals of multiplexers 101 and 102 are coupled to receive a signal from configurable bit latch 113.

When configurable bit latch 113 is programmed to provide a logic "0" signal, the carry initialization signal on line 114 is transmitted through multiplexers 101 and 102 as carry chain signals CA.sub.i and CB.sub.i. Thus, carry chain signals CA.sub.i and CB.sub.i are either both set to be logic "0" signals or both set to be logic "1" signals. If carry chain signals CA.sub.i and CB.sub.i are both set to be logic "0" signals, the local carry input signal C.sub.i provided within carry logic circuit 100 is effectively set to a logic "0" value, regardless of the value of the express carry input signal C.sub.in.

Similarly, if carry chain signals CA.sub.i and CB.sub.i are both set to be logic "1" signals, then the local carry input signal C.sub.i is set to a logic "1" value regardless of the value of express carry input signal C.sub.in.

When configurable bit latch 113 is programmed to provide a logic "1" signal, the signals programmed in configurable bit latches 111 and 112 are transmitted through multiplexers 101 and 102, respectively, as carry chain signals CA.sub.i and CB.sub.i, respectively. In one configuration which uses the carry chain circuit, configurable bit latches 111 and 112 are programmed to provide logic "0" and logic "1" signals, respectively. As a result, the local carry input signal C.sub.i is set to be equal to the value of C.sub.in. When using carry logic structure 500 to implement an adder circuit, carry chain initialization circuit 115 is not programmed such that configurable bit latches 111 and 112 provide logic "1" and logic "0" signals, respectively, as carry chain signals CA.sub.i and CB.sub.i. This is because this combination of signals will cause invalid results within the adder circuit.

To implement the least significant carry logic structure of an adder circuit (i.e., the structure which adds the four least significant bits), configurable bit latch 113 is programmed to provide a logic "0" signal and the carry initialization signal is set to a logic "0" signal. As a result, carry chain signals CA.sub.i and CB.sub.i are each logic "0" signals. This initializes local carry input signal C.sub.i of carry logic circuit 100 to be a logic "0" signal. Table 2 is the truth table for carry logic circuit 100 under these conditions.

Thus, carry logic circuit 100 adds input signals A.sub.i, B.sub.i and C.sub.i (which is always equal to logic "0" ) to create sum signal S.sub.i and local carry input signal C.sub.i+1 in a manner consistent with Table 1. Because both carry chain signals CA.sub.i and CB.sub.i are logic "0" signals, the express carry input signal C.sub.in has no effect on the value of sum signal S.sub.i or the value of local carry input signal C.sub.i. Moreover, because carry chain signals C.sub.i+1 and CB.sub.i+1 always have the same value, express carry input signal C.sub.in has no effect on the value of local carry input signal C.sub.i+1.

As illustrated in Table 2, when carry chain signals CA.sub.i and CB.sub.i are programmed to logic "0" values, there are only two possible combinations for carry chain signals CA.sub.i+1 and CB.sub.i+1. If both of carry chain signals CA.sub.i+1 and CB.sub.i+1 have logic "0" values, then carry logic circuit 200 operates in accordance with Table 2. Table 3 illustrates the operation of carry logic circuit 200 if both carry chain signals CA.sub.i+1 and CB.sub.i+1 have logic "1" values.

Thus, carry logic circuit 200 adds input signals A.sub.i+1, B.sub.i+1 and C.sub.i+1 (with C.sub.i+1 being set to logic "1" ) to create sum signal S.sub.i+1 and local carry input signal C.sub.i+2 in a manner consistent with Table 1. Because both carry chain signals CA.sub.i+1 and CB.sub.i+1 are logic "1" signals, the express carry input signal C.sub.in has no effect on the value of sum signal S.sub.i+1 or the value of local carry input signal C.sub.i+1. Moreover, because carry chain signals CA.sub.i+2 and CB.sub.i+2 always have the same value, express carry input signal C.sub.in has no effect on the value of local carry input signal C.sub.i+2.

By initializing the carry chain signals CA.sub.i and CB.sub.i to logic "0" signals, the pairs of carry chain signals which propagate between carry logic circuits in carry logic structure 500 are matched. That is, carry chain signals CA.sub.i+1 and CB.sub.i+1 have the same logic value, carry chain signals CA.sub.+2 and CB.sub.i+2 have the same logic value, and carry chain signals CA.sub.i+' and CB.sub.i+.sub.3 have the same logic value. As a result, the logic value of express carry input signal C.sub.in has no effect on local carry input signals C.sub.i, C.sub.i+1, C.sub.i+2 and C.sub.i+3.

If the carry chain signals CA.sub.i and CB.sub.i are initialized to both be logic "1" signals, local carry input signal C.sub.i is set to a logic one value. In this case, carry logic structure 500 is programmed to add a "1" value to the sum of the four bit numbers applied to structure 500.

To implement a structure which adds four bits which are not the four least significant bits of an adder circuit (e.g., the second carry logic structure of an 8-bit adder circuit), configurable bit latch 111 is programmed to provide a logic "0" signal, configurable bit latch 112 is programmed to provide a logic "1" signal and configurable bit latch 113 is programmed to provide a logic "1" signal. This effectively selects carry chain signal CA.sub.i to be a logic "0" signal and carry chain signal CB.sub.i to be a logic "1" signal. Table 4 describes the operation of carry logic circuit 100 under these conditions.

Thus, carry logic circuit 100 adds input signals A.sub.i, B.sub.i and C.sub.i to create sum signal S.sub.i and local carry input signal C.sub.i+1 in a manner consistent with Table 1. Carry logic circuit 200 can receive any one of three possible combinations of carry chain signals CA.sub.i+1 and CB.sub.i+1. If both of carry chain signals CA.sub.i+1 and CB.sub.i+1 have logic "0" values, then carry logic circuit 200 operates in accordance with Table 2. If both of carry chain signals CA.sub.i+1 and CB.sub.i+1 have logic "1" values, then carry logic circuit 200 operates in accordance with Table 3. If carry chain signal CA.sub.i+1 =0 and carry chain signal CB.sub.i+1 =1, then carry logic circuit 200 operates in accordance with Table 4. Carry logic circuits 300 and 400 operate in the same manner as carry logic circuit 200.

Carry output signal selection circuit 160 effectively routes carry chain signal CA.sub.i+4 as carry output signal C.sub.out if express carry input signal C.sub.in has a logic "0" value, and routes carry chain signal CB.sub.i+4 as carry output signal C.sub.out if express carry input signal C.sub.in has a logic "1" value. Proper operation of carry output signal selection circuit 160 requires that the carry input signals CA.sub.i and CB.sub.i are not selected to be logic "1" and logic "0" signals, respectively.

FIG. 7 illustrates a multiplexer 170 which is logically equivalent to carry output signal selection circuit 160. Multiplexer 170 has a "0" input terminal coupled to receive carry chain signal CA.sub.i+4, a "1" input terminal coupled to receive carry chain signal CB.sub.i+4, a control terminal coupled to receive express carry input signal C.sub.in, and an output terminal which receives carry output signal C.sub.out. Although carry output signal selection circuit 160 is logically equivalent to multiplexer 170, carry output signal selection circuit 160 transmits carry output signal C.sub.out with less delay. This is because express carry input signal C.sub.in is not used to control multiplexer 162 in carry output signal selection circuit 160.

When a plurality of 4-bit carry logic structures are cascaded together, the carry signal delay is calculated as follows. In the initial carry logic structure, there is a slight delay introduced as the input signals are routed through the exclusive OR gates to create the propagate signals. There is also one pass gate delay per bit. This is because for each bit, a pair of carry chain signals must pass through a pair of parallel multiplexers, such as multiplexers 103 and 104. In addition, within carry output signal selection circuit 160, there is a slight delay introduced by AND gate 161 and buffer 163, and one pass gate delay introduced by circuit multiplexer 162. However, in each additional carry logic structure, the carry signal delay is equal to the pass gate delay introduced by circuit 162 and the delay introduced by buffer 163. This is because the multiplexers in the carry chains of each of the coupled carry logic structures settle concurrently. By the time that the initial carry logic structure transmits the carry output signal C.sub.out to a subsequent carry logic structure, the multiplexers of the subsequent carry logic structure have settled. Consequently, the multiplexers of the carry chain of the subsequent carry logic structure do not significantly contribute to carry signal delay.

Consequently, carry logic structure 500 is capable of performing as a conventional adder circuit, while providing reduced propagation delay for the carry output signal C.sub.out.

FIGS. 8-10 show schematic diagrams of alternative embodiments of the carry out circuit of the invention. The structure of FIG. 8 is similar to two stages of the structure of FIG. 3, except that the A.sub.i and A.sub.i inputs are shown as separate signals and XOR gates 85 and 86 are shown as being provided in hardware.

FIG. 9 shows the logic reorganized for higher speed. Multiplexer 91, equivalent to multiplexer 81 of FIG. 8 is retained and is used to generate the sum signal in XOR gate 96. However, multiplexer 92 is a three-input multiplexer controlled as shown in the truth table at the right of FIG. 9 by the P.sub.i and P.sub.i+1 signals, and thus the carry chain delay of multiplexer 91 (or 81 in FIG. 8) is avoided.

The structure of FIG. 10 includes multiplexer 97, which selects between B.sub.i and B.sub.i+1 as controlled by P.sub.i+1 to provide an input to two-input multiplexer 98. Also included is AND gate 99, which causes multiplexer 98 to provide the output of multiplexer 97 only when P.sub.i and P.sub.i+1 are both logical 1. Thus in FIG. 10, the carry chain signal encounters the delay of only one two-input multiplexer for two stages. (Two-input multiplexers are typically faster than three-input multiplexers.)

FIG. 11 shows the conditional sum structure according to another embodiment of the invention. The structure of FIG. 11 is similar to the structure of FIG. 6. Equivalent elements have been given the same reference numbers in these two figures. In FIG. 11, instead of the XOR gates 141 through 144 of FIG. 6, the structure includes pairs of XOR gates 141a through 144a and 141b through 144b. These pairs of XOR gates generate conditional sums using the local carry chain signals. For example, XOR gate 141a generates the XOR function of CA.sub.i and P.sub.i and XOR gate 141b generates the XOR function of CB.sub.i and P.sub.i. When the carry-in signal C.sub.in arrives at multiplexer 131, the final sum S.sub.i is quickly available without the delay of switching XOR gate 141 in FIG. 6. Thus delay is further reduced.

FIG. 12 shows another structure for generating a fast carry signal in which the conditional sum can be employed. In FIG. 12, logic gates 125, 225, and 325 in logic unit 1201 generate the XOR, OR, and AND functions respectively of input signals A.sub.i and B.sub.i. As in earlier embodiments, XOR gate 125 provides the half sum P.sub.i. Multiplexer 103 selects one of the AND and OR functions of input signals A.sub.i and B.sub.i as determined by carry-in signal CA.sub.i. Operation of multiplexers 103 through 110 is as discussed in connection with FIG. 2B, modified to include two carry chains. Thus the structure of FIG. 12 is another structure for generating fast carry signals when two carry chains are provided. The structure of FIG. 12 includes the same arrangement of XOR gates and multiplexers at the right hand side of the figure for generating the conditional sum as shown in FIG. 11. The structure at the right hand side of FIG. 6 can alternatively be used. FIG. 13 shows such an embodiment. FIG. 12 shows a simplified structure replacing carry initialize structure 115 of FIG. 6 or FIG. 11. This structure is usable in a portion of an FPGA in which user control of the carry chain initialization is not required. As another embodiment, the structure of FIG. 12 can be modified to include the carry initialize structure of FIGS. 6 and 11 to achieve an embodiment in which a carry chain can be initialized. Alternatively, the hard 0 and hard 1 of FIG. 12 can be replaced with signals from memory cells that can be loaded during configuration.

FIG. 14 is a block diagram of a CLB 1401 that is used to construct a carry logic structure in accordance with another embodiment of the present invention. CLB 1401 includes an array of logic cells arranged in a row-column configuration. More specifically, CLB 1401 includes configurable logic cells 1411-1414, which are arranged in a 2.times.2 array as illustrated. Although CLB 1401 has a 2.times.2 logic cell array, CLBs having logic cell arrays of other dimensions can be used in other embodiments.

Each of logic cells 1411-1414 includes a 4-input function generator, carry/control logic, and a register. For example, logic cell 1411 includes function generator 401, carry/control logic 411 and register 421. Logic cell 1411 also includes a carry chain initialization circuit 431, which is identical to carry chain initialization circuit 115 (FIG. 6). Logic cell 1412 includes function generator 402, carry/control logic 412 and register 422. Carry/control logic 411 of logic cell 1411 is coupled to carry/control logic 412 of logic cell 1412 as illustrated. Logic cells 1411-1412, which are located in the first column of the logic cell array, form a first logic cell slice 1421.

Logic cell 1413 includes function generator 403, carry/control logic 413 and register 423. Similarly, logic cell 1414 includes function generator 404, carry/control logic 414 and register 424. Logic cell 1414 also includes carry output signal selection circuit 432, which is identical to carry output signal selection circuit 160 (FIG. 6). Carry/control logic 413 of logic cell 1413 is coupled to carry/control logic 414 of logic cell 1414 as illustrated. Logic cells 1413-1414, which are located in the second column of the logic cell array, form a second logic cell slice 1422.

In the described embodiment, function generators 401-404 are identical, carry logic circuits 411-414 are identical, and registers 421-424 are identical. These elements of CLB 1401 are described in more detail in U.S. patent application Ser. No. 08/806,997 [Attorney Docket No. X-277], which is hereby incorporated by reference in its entirety.

In the described embodiment, each of logic cells 1411-1414 is capable of being configured as a carry logic circuit identical to carry logic circuit 100 (FIG. 6). To accomplish this, each of function generators 401-404 is capable of being configured as an exclusive OR gate corresponding to exclusive OR gate 125 of carry logic circuit 100. Moreover, each of carry/control logic blocks 411-414 includes logic circuitry capable of being configured to form the remainder of carry logic circuit 100. More specifically, each of carry/control logic blocks 411-414 includes logic circuitry that is configurable to form multiplexers corresponding to multiplexers 103-104 and 131 of carry logic circuit 100. Each of carry/control logic blocks 411-414 further includes logic circuitry that is configurable to form an exclusive OR gate corresponding to exclusive OR gate 141 of carry logic circuit 100. Each of carry/control logic blocks 411-414 can therefore generate a sum output signal in the manner described above. These sum output signals can either be clocked through a corresponding one of registers 421-424, or routed directly out of the logic cell.

Carry chain initialization circuit 431 is configured to provide carry chain signals CA.sub.i and CB.sub.i in response to the carry chain initialization signal C.sub.I. The generation of carry chain signals CA.sub.i and CB.sub.i have been described above in connection with FIG. 6. Carry chain signals CA.sub.i and CB.sub.i are provided to carry/control logic 411, along with carry input signal C.sub.in.

In CLB 1401, function generator 401 and carry/control logic 411 are configured to correspond with carry logic circuit 100 of FIG. 6. Thus, function generator 401 is configured to receive input values A.sub.i and B.sub.i, and in response, provide the exclusive OR of these values as propagate signal P.sub.i to carry/control logic 411. Input value A.sub.i is also provided to carry logic 411. In response to signals A.sub.i, P.sub.i, CA.sub.i, CB.sub.i and C.sub.in, carry/control logic 411 generates carry signals CA.sub.i+1, CB.sub.i+1 and output signal S.sub.i. These signals are generated in the manner described above in connection with FIG. 6. Carry/control logic 411 also passes the C.sub.in signal.

Function generator 402 and carry/control logic 412 are configured to correspond with carry logic circuit 200 of FIG. 6. Thus, function generator 402 is configured to receive input values A.sub.i+1 and B.sub.i+1, and in response, provide the exclusive OR of these values as propagate signal P.sub.i+1 to carry/control logic 412. Input value A.sub.i+1 is also provided to carry logic 412. In response to signals A.sub.i+1, P.sub.i+1, C.sub.i+1, CBi+1 and C.sub.in, carry/control logic 412 generates carry signals CA.sub.i+2, CB.sub.i+2 and output signal S.sub.i+1. These signals are generated in the manner described above in connection with FIG. 6. Carry/control logic 412 also passes the C.sub.in signal.

In the above-described manner, first logic cell slice 1421 of CLB 1401 implements a carry chain initialization circuit and two carry logic circuits. However, two additional carry logic circuits and a carry output signal selection circuit are required to complete carry logic structure 500 of FIG. 6. As described in more detail below, these required circuits are provided by a vertically adjacent CLB, which is identical to CLB 1401.

FIG. 15 is a block diagram illustrating CLB 1401 and a vertically adjacent CLB 1501. Vertically adjacent CLB 1501 is identical to CLB 1401. Thus, CLB 1501 includes a first slice 1521 that is identical to first slice 1421, and a second slice 1522 that is identical to second slice 1422. More specifically, CLB 1501 includes function generators 501-504 (which are identical to function generators 401-404), carry/control logic blocks 511-514 (which are identical to carry/control logic blocks 411-414), registers 521-524 (which are identical to registers 421-424), carry chain initialization circuit 531 (which is identical to carry chain initialization circuit 431), and carry output signal selection circuit 532 (which is identical to carry output signal selection circuit 432).

Dedicated routing resources 1550 are located between vertically adjacent CLBs 1401 and 1501 as illustrated. Routing resources 1550 include three lines that connect carry/control logic 412 in CLB 1401 to carry/control logic 513 in CLB 1501. In this manner, carry input signal C.sub.in and carry signals CA.sub.i+2 and CB.sub.i+2 are provided to carry/control logic 513.

Function generator 503 and carry/control logic 513 are configured to correspond with carry logic circuit 300 of FIG. 6. Thus, function generator 502 is configured to receive input values A.sub.i+2 and B.sub.i+2, and in response, provide the exclusive OR of these values as propagate signal P.sub.i+2 to carry/control logic 513. Input value A.sub.i+2 is also provided to carry/control logic 513. In response to signals A.sub.i+2, P.sub.i+2, CA.sub.i+2, CB.sub.i+2 and C.sub.in, carry/control logic 513 generates carry signals CA.sub.i+3, CB.sub.i+3 and output signal S.sub.i+2. These signals are generated in the manner described above in connection with FIG. 6. Carry/control logic 513 also passes carry input signal C.sub.in to carry/control logic 514.

Function generator 504 and carry/control logic 514 are configured to correspond with carry logic circuit 400 of FIG. 6. Thus, function generator 504 is configured to receive input values A.sub.i+3 and B.sub.i+3, and in response, provide the exclusive OR of these values as propagate signal P.sub.i+3 to carry/control logic 514. Input value A.sub.i+3 is also provided to carry logic 514. In response to signals A.sub.i+3, P.sub.i+3, CA.sub.i+3, CB.sub.i+' and C.sub.in, carry/control logic 514 generates carry signals CA.sub.i+4, CB.sub.i+4 and output signal S.sub.i+3. These signals are generated in the manner described above in connection with FIG. 6. Carry/control logic 514 also passes the C.sub.in signal to carry output signal selection circuit 532.

Carry output signal selection circuit 532 generates the carry output signal C.sub.out in response to carry input signal C.sub.in and carry signals CA.sub.i+4 and CB.sub.i+4. The structure and operation of carry output signal selection circuit 532 is described above in connection with FIGS. 6 and 7. The carry output signal C.sub.out is routed to a vertically adjacent CLB (not shown) for further processing.

Dedicated routing resources identical to routing resources 1550 are provided between each pair of vertically adjacent CLBs. Consequently, the manner in which the carry output signal C.sub.out is routed from CLB 1501 to a vertically adjacent CLB (not shown) is identical to the manner in which a carry output signal is routed from carry output signal selection circuit 432 of CLB 1401 to CLB 1501. Routing resources 1550 provide a line to transmit a carry output signal from carry output signal selection circuit 432 to carry logic circuit 511 of CLB 1501 as a carry input signal (C.sub.in).

As described above, a carry logic structure can be formed by vertically adjacent CLBs. The carry logic structure shifts between the left and right slices of successive CLBs. Note that the second slice 1422 of CLB 1401 can be connected to the first slice 1521 of CLB 1501 in another carry chain structure. In this manner, two separate carry chain structures are formed in a single column of CLBs. Each carry chain structure has a pitch larger than the pitch of the CLBs. That is, each carry chain circuit has a pitch of four bits (between the carry initialization circuit and the carry output circuit), while each CLB has a pitch of 2 bits. Advantageously, the first logic cell slices in each of the CLBs are identical, and the second logic cell slices in each of the CLBs are identical, thereby enabling a uniform CLB array structure.

Although the example of FIGS. 14 and 15 have been described as using the carry chain structure of FIGS. 6 and 7, in other embodiments, the carry chain structures of FIGS. 8-13 can be substituted for the carry chain structure of FIGS. 6 and 7.

Moreover, although the example of FIGS. 14 and 15 use a CLB have a 2.times.2 logic cell array, the present invention can be extended to CLBs having logic cell arrays of other dimensions. For example, a 2.times.4 logic cell array can be used as illustrated in FIG. 16.

FIG. 16 is a block diagram illustrating four vertically adjacent CLBs 1611-1614, each having a 2.times.4 array of logic cells. CLBs 1611, 1612, 1613 and 1614 include logic cells 1601-1608, 1701-1708, 1801-1808 and 1901-1908, respectively. Logic cells 1601, 1701, 1801 and 1901 include carry initialization circuits, and logic cells 1608, 1708, 1808 and 1908 include carry output signal selection circuits. None of the other logic cells have carry initialization or carry output signal selection circuits. Advantageously, the layout of each of CLBs 1611-1614 is identical, resulting in a uniform layout pattern within the FPGA.

In the embodiment of FIG. 16, each carry chain circuit provides an 8-bit output and spans four CLBs. For example, one of the carry chains starts at the carry initialization circuit in logic cell 1601, runs through logic cells 1601-1602, 1703-1704, 1805-1806 and 1907-1908, and ends at the carry output signal selection circuit in logic cell 1908. Identical dedicated routing circuits 1651-1653 are provided between vertically adjacent CLBs. Routing circuits 1651-1653 shift the carry signals provided by the first, second and third logic cell slices of a CLB to the second, third and fourth logic cell slices, respectively, of a vertically adjacent CLB. Routing circuits 1651-1653 also shift the carry signal provided by the fourth cell slices of a CLB to the first logic cell slice of a vertically adjacent CLB. As a result, portions of four carry chain circuits extend through each CLB.

FIG. 17 is a block diagram of a carry logic structure in accordance with another embodiment of the present invention. Because the carry logic structure of FIG. 17 is similar to the carry logic circuit of FIG. 16, similar elements in FIGS. 16 and 17 are labeled with similar reference numbers. Note that in the carry logic structure of FIG. 17, carry initialization circuits are included in logic cells 1605, 1705, 1805 and 1905. Further note that carry output signal selection circuits are included in logic cells 1604-1704, 1804 and 1904. Again, the layout of each of CLBs 1611-1614 is identical, resulting in a uniform layout pattern within the FPGA.

In the embodiment of FIG. 17, each carry chain circuit provides an 4-bit output and spans two CLBs. For example, one of the carry chains starts at the carry initialization circuit in logic cell 1601, runs through logic cells 1601-1602 and 1703-1704, and ends at the carry output signal selection circuit in logic cell 1704. Identical dedicated routing circuits 1751-1753 are provided between vertically adjacent CLBs. Routing circuits 1751-1753 shift the carry signals provided by the first and third logic cell slices of a CLB to the second and fourth logic cell slices, respectively, of a vertically adjacent CLB. Routing circuits 1751-1753 also shift the carry signals provided by the second and fourth logic cell slices of a CLB to the first and third logic cell slices, respectively, of a vertically adjacent CLB. As a result, portions of four carry chain circuits extend through each CLB.

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. For example, carry logic structures having numbers of bits other than four are contemplated. Thus, the invention is limited only by the following claims.