US 6,141,630 AGrant
System and Method for Automated Design Verification
Issue Date:2000-10-31
•10 Claims
•7 Drawing Sheets
Abstract
A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.
Metadata
Assignee
- Verisity Design, Inc.
Inventors
- Michael Thomas York McNamara
- Chong Guan Tan
- David Todd Massey
Application Information
Application Number:US 9082484
Filing Date:1997-08-07
Priority Date:1997-08-07
Art Unit:273
Classifications
IPC:
G06F 1750
Field of Search:
395364714371716703500.06;500.05578;48928;30;25;32;724;735;738;73923;22.14;514
Patent Drawings (7 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates generally to systems and methods for testing circuit design descriptions, and more particularly to systems and methods for automated design description verification within an electronic design automation (EDA) environment.
2. Discussion of Background Art
Electronic Design Automation (EDA) is a process for using computer programs to design, simulate, and test electronic circuits before they are fabricated. By simulating designs with simulation software, on emulation systems, and/or by using simulation acceleration systems, design flaws are detected and corrected before fabrication of the silicon device. A testing before fabrication process saves manufacturers millions of dollars in non-recoverable engineering (NRE) costs. However, as designs increase in complexity, so too does the difficulty of testing. In fact, the difficulty of testing with traditional EDA verification tools increases geometrically with the number of gates. System designers are also asked to design and test these increasingly complex circuits within ever smaller time frames. As a result, manufacturers must choose between either taking more time to test the design, and thereby delaying product shipment, or only testing portions of the circuit, and thereby risking that many undiscovered bugs get passed on to the users.
One approach to this problem is to speed up the design simulation programs. Native Code Simulators, Simulation Acceleration, and Chip Emulation System all decrease the time it takes to simulate a design, and may sometimes decrease the time it takes to identify the next bug in a design. However, during early stages of the design process, design bugs are prevalent, and speeding up the simulation does little to help identify these bugs.
Another approach is to test the circuit design randomly. Random testing involves generating a plurality of unique test vectors that are randomly related to each other and then testing (or "exercising") the design with these vectors. In this approach, as time allotted for random testing increases, more of the circuit design is tested. Random testing is a time consuming and risky proposition, since discovering bugs then becomes a hit or miss proposition, and there is rarely sufficient time to test the circuit design fully. Moreover, it is quite possible, even likely that running a random simulation for ten or one hundred times longer will not significantly increase the verification density.
Other types of EDA testing tools, such as an Automatic Test Pattern Generation (ATPG) tools, produce tests which only identify manufacturing defects in an already fabricated circuit. Testing is performed by successively applying known input values to the pins of the circuit, and then comparing actual output values with a set of expected output values. However, ATPG tools assume that the circuit already has a fundamentally correct design and that any anomalies that are discovered are only due to physical defects introduced in the manufacturing process, such as broken wires.
EDA testing tools, such as Verilint, developed by InterHDL of Los Altos, Calif.; Vericov, developed by Simulation Technology of Saint Paul, Minn.; Vera, developed by System Science of Palo Alto, Calif.; and Specman, developed by Verisity of Yehud, Israel; also exist but they are difficult to use, sell, and integrate into a test bench for verifying the correctness of circuit designs.
What is needed is an apparatus and method for design verification that overcomes the problems of the prior art.
Summary of the Invention
The present invention is a system and a method for automated design verification. Within the system of the present invention, a test bench is created to stimulate a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies which portions of the design remain to be tested. A test generator produces test vectors and sends them to the test bench which exercises the portions of the simulated design which the coverage analysis tool has indicated remain to be tested.
With the method of the present invention, a design description is interpreted by a test generator as a state diagram composed of a set of basic blocks interconnected by transition arcs. The test generator produces a plurality of test vectors for exercising the basic blocks and transition arcs. A computer program processes the design description and creates a simulated design. Basic blocks and transition arcs within the simulated design are exercised by the plurality of test vectors. Those basic blocks and transition arcs which have (and have not) been exercised are identified by a coverage analysis program which monitors the simulated design's internal operation. The test generator receives these reports and in response produces a new set of test vectors to exercise the basic blocks and transition arcs which were not yet tested. A first set of output data from the simulated design may then be compared against a second set of output data received from a reference. The first set of output data may also be compared with a set of optional constraints. These comparisons result in an anomaly report if the first set of output data is not equivalent to either the second set of output data or the set of optional constraints. The test generator then correlates the basic blocks and transition arcs exercised by the test vectors with the results from the reporting step to localize and identify any of the basic blocks and transition arcs within the simulated design which were operating incorrectly or indeterminately.
The apparatus and method of the present invention are particularly advantageous over the prior art because a critical part of design verification--previously performed, manually and on a sporadic basis due to engineering resource requirements and time-to-market considerations--is now automated. The present invention permits testing of basic blocks, transition arcs, and paths of interest within the simulated design using a quick, easy, comprehensive, and integrated process. As a result, designers can proceed toward fabrication with confidence that the simulated design has been verified. A time savings of months is achieved, since any design flaws are discovered before the simulated design is fabricated.
These and other aspects of the invention will be recognized by those skilled in the art upon review of the detailed description, drawings, and claims set forth below.
Brief Description of the Drawings
FIG. 1 is a data-flow diagram of a first exemplary system for automated design verification according to the present invention;
FIG. 2 is a data-flow diagram of a second exemplary system for automated design verification according to the present invention;
FIG. 3 is a data-flow diagram of a third exemplary system for automated design verification according to the present invention;
FIG. 4 is a state diagram of an exemplary circuit design that is to be tested with the present invention;
FIG. 5 is a flowchart of a method for automated design verification; and
FIG. 6 is a flowchart of a method for generating a set of test vectors within the method for automated design verification.
Detailed Description of the Preferred Embodiment
FIG. 1 is a data-flow diagram of a first exemplary system 100 for automated design verification according to the present invention. The system 100 includes a design database 102, a coverage database 104, a test generator 106, a test bench 108, and a coverage analysis tool 110. The test bench 108 includes a simulated design 112 and an output log database 114.
The design database 102 contains one or more circuit designs. These circuit designs are typically coded in a known design language, such as Verilog, VHDL, or C++. These coding languages are also used with other Electronic Design Automation (EDA) tools to simulate, test and fabricate the design of the circuit. The coverage database 104 contains a map of each state and transition arc within a circuit design. As the circuit design's various states are entered and transition arcs are followed, the map in the coverage database 104 is updated to reflect that these states and/or transition arcs have been exercised. The coverage database 104 is coupled to the coverage analysis tool 110. The coverage analysis tool 110 is coupled to the simulated design 112 in the test bench 108, and uses output data from simulated design 112 to determine which areas of the circuit design have been tested. The coverage analysis tool 110 then updates the coverage database 104 based upon this information. Coverage analysis tools are well known in the art.
The test generator 106 is coupled to receive data from the design database 102 and the coverage database 104, and in response generates a set of test vectors which are sent to the simulated design 112 in the test bench 108. The simulated design 112 is coupled to receive the test vectors from the test generator 106, and in response generates output data which is sent to both the coverage analysis tool 110 and the output log database 114. The simulated design 112 includes software (such as Verilog or VHDL) which is executed within a computer (not shown) to model the operational characteristics of the circuit design. The output log database 114 stores the output data from the simulated design 112 for later analysis by other EDA tools (not shown). The test bench 108 which executes the simulated design 112 is well known in the art.
Before the test generator 106 generates the test vectors, the test generator 106 performs a complete syntax and synthesizability check on a circuit design within the design database 102 that is to be tested. The test generator 106 indicates whether there are any syntax errors in the circuit design, and whether all parts of the design are synthesizable. The test generator 106 then expands any macros and data structures within the design description. Next, the test generator 106 analyzes the design description and identifies all inputs and outputs. The test generator 106 interprets the design description as a series of basic-blocks that are connected by a series of transition arcs, forming a state diagram. This state diagram is also known as a decision tree or a design flow graph. The test generator 106 verifies the stability of each basic block within the state diagram independent of all other basic blocks.
A basic block is the smallest building block in a design description. Basic blocks are defined at each point in the state diagram where either a condition is met or a calculation occurs. A set of basic blocks visited by consecutive transition arcs in the state diagram define a path. In a typical design description there are a very large number of paths. However, only a limited number of paths may be of interest to users. These are labeled `paths-of-interest.`
For example, the following design description contains four basic blocks:
In the above example, transition arcs are defined between the 1.sup.st basic block and the 2.sup.nd basic block, the 1.sup.st basic block and the 3.sup.rd basic block, the 2.sup.nd basic block and the 4.sup.th basic block, and the 3.sup.rd basic block and the 4.sup.th basic block. Paths are defined from the 1.sup.st basic block through the 2.sup.nd basic block to the 4.sup.th basic block, and from the 1.sup.st basic block through the 3.sup.rd basic block to the 4.sup.th basic block.
The test generator 106 automatically constructs a first set of test vectors for causing each state of the state machine to be visited and each transition arc to be taken. This first set of test vectors proves whether each of the basic blocks that make up the design description are correct. The test generator 106 then produces a second set of test vectors for proving that user-selected subsets of the basic blocks work together correctly. These subsets of the basic blocks, when linked together, are equivalent to the paths of interest discussed above.
All test vectors are generated with the test generator 106 by first identifying any untested design description elements, such as basic blocks, transition arcs, or paths of interest, from the coverage database 104, and then automatically generating a set of test vectors to exercise those elements. This testing may take place at any level of granularity, ranging from the design description's top-level inputs and outputs, to the individual logic elements.
The test generator 106 creates a test vector by first determining which basic block, transition arc, or path is to be tested next. The test generator 106 then determines what variables need to be set or what conditions need to occur so that the simulated design 112 transitions to an untested element from a currently active basic block. This is called "back-solving." The test generator may also use a "forward solving" approach to decide what sequence of actions to take in order to activate targeted arcs, blocks, or paths from the given state of the design. In general, the test generator 106 chooses test vectors that exercise a greatest number of untested elements.
Active basic blocks are defined as those that are waiting for some variable to be set or condition to occur before passing control to another basic block. Conditions that need to occur are typically defined in terms of some timing constraint. For example, a variable may need to be set to a certain state ten clock pulses after another variable transitions to a different state in order for control to be passed from a currently active basic block to another basic block.
A complete set of test vectors is called a test frame. The test frame is submitted to the test bench 108 where the simulated design 112 simulated by the test vectors. In response, the simulated design 112 generates and sends a set of output data to the output log database 114 and the coverage analysis tool 110, as discussed above.
Based on the feedback provided by the coverage analysis tool 110, the test generator 106 again checks whether all of the basic blocks, transition arcs, and paths of interest have been tested. If any remain untested, the test generator 106 repeats the back-solving process.
During the course of this iterative testing, the test generator 106 uses the data in the coverage database 104 to explore whether the simulated design 112 is stable for all given inputs, and whether the simulated design 112 contains any un-reachable states or un-exercisable transition arcs.
FIG. 2 is a data-flow diagram of a second exemplary system 200 for automated design verification according to the present invention. In addition to the elements introduced in FIG. 1, the second system 200 includes a functional model 202. This model 202 is coupled to receive test vectors from the test generator 106, output data from the simulated design 112, and verify the output data's accuracy. The functional model 202 compares the output data from the simulated design 112 with a set of expected values generated by the functional model 202. These expected values are intended to reflect how the design description should operate in response to the test vectors generated by the test generator 106. The functional model 202 labels the output data from the simulated design 112 as either correct or incorrect. The functional model 202 also flags indeterminate conditions, such as when the simulated design 112 does not generate any output data in response to a test vector.
The functional model 202 is a non-cycle-accurate model of the simulated design 112. A non-cycle-accurate model is one that does not attempt to mimic the simulated design 112 during each cycle of the simulation. The functional model 202 can generate a set of expected values in one of several ways. For instance, the functional model 202 can be implemented as a database lookup table or as an algorithm. For example, while the simulated design may be comprised of a set of commands for defining a series of AND and OR gates interconnected with latches and registers, which together implement a multiplication function, the functional model 202 could simply perform a logical multiplication with a program written with an off-the-shelf C or C++ programming language.
The test generator 106 is coupled to receive the results generated by the functional model 202, thus creating a second feedback loop in the system 200. The test generator 106 correlates the test vectors sent to the simulated design 112 with the results from the functional model 202 to localize and identify which of the basic blocks, transition arcs, and/or paths within the simulated design 112 operate incorrectly or indeterminately. The test generator 106 can then be programmed to automatically generate a more detailed series of tests focused on the incorrect or indeterminate design elements. Alternatively, the test generator 106 only prints out the set of test results which a designer then uses to manually generate a more detailed series of tests.
FIG. 3 is a data-flow diagram of a third exemplary system 300 for automated design verification according to the present invention. In addition to the elements introduced in FIG. 1, the third system 300 includes a cycle accurate model 302 and an output sequence comparator 304. The cycle accurate model 302 is coupled to receive the test vectors from the test generator 106 and is designed to match cycle-for-cycle the output data from the simulated design 112. The output sequence comparator 304 is coupled to receive output data from both the simulated design 112 and the cycle accurate model 302. The output sequence comparator 304 compares every cycle of the output data and generates a set of results which labels the output data from the simulated design 112 as either correct, incorrect, or indeterminate.
The test generator 106 is coupled to receive the results generated by the output sequence comparator 304, thus creating a second feedback loop in the system 300. The test generator 106 then correlates the test vectors sent to the simulated design 112 with the results from the output sequence comparator 304 to localize and identify whether the basic blocks, transition arcs, and/or paths within the simulated design 112 are operating incorrectly or indeterminately. The test generator 106 is then programmed to either automatically generate a more detailed series of tests which center about any incorrect or indeterminate design elements, or to print out the results for a designer to review.
The test generator 106, the coverage analysis tool 110, the simulated design 112, the functional model 202, the cycle accurate model 302, and the output sequence comparator 304 are software modules comprised of computer program instructions that run on a computer (not shown). The computer includes a processing unit and a memory. The memory stores computer program instructions for controlling how the processing unit accesses, transforms and outputs data. Those skilled in the art will recognize that the internal memory can be supplemented with other computer useable storage media, including a compact disk, a magnetic drive or a dynamic random access memory.
FIG. 4 is a state diagram 400 of an exemplary circuit design tested using the present invention. The following discussion illustrates how the test generator 106 produces a set of test vectors to test the state diagram 400 and how the test generator 106 responds to the test results.
To begin, the test generator 106 has identified six basic blocks 402 through 412 and seven transition arcs 414 through 426. At least four paths exist, however, recursive arc 426 theoretically permits an infinite number of paths to be defined. The test generator 106 proceeds to generate test vectors which set variables A and B so that each basic block, transition arc, and path of interest is tested. Predetermined paths of interest are loaded into the test generator 106 by a user. The test generator 106 can also be pre-programmed with assertions, which will generate an alert upon the occurrence of certain conditions. (for example, if C ever equals D).
During testing of basic block 410 in the state diagram 400, for example, the test generator 106 exercises transition arc 424, where C<40, and transition arc 426, where C>40. However, the test generator 106 also attempts to test the case where C=40. Since a next state has not been defined in the state diagram 400 for the case where C=40, the test generator alerts a user to this indeterminate case. It is through this automatic testing process that the circuit design is fully tested and any errors in the design are brought to a user's attention.
FIG. 5 is a flowchart of a method for automated design verification. The method begins in step 502 where the test generator 106 imports a design description (typically defined in terms of a hardware description language such as Verilog or VHDL) from the design database 102, and the test bench 108 imports a reference description from another database (not shown). The reference description optionally forms the basis of either the functional model 202 or the cycle accurate model 302. Next, in step 504, the test generator 106 decomposes the design description into basic blocks, transition arcs, and paths of interest to form a state diagram. In step 506, the test generator 106 identifies all input, output, and internal variables in the design description. In step 508, the test generator 106 identifies all state machines in the design description. Then, in step 510, the test generator 106 imports coverage data, describing how much of the design description has already been tested, from the coverage database 104. In step 512, the test generator 106 generates a set of test vectors that test those areas of the design description that have not yet been covered. (Step 512 is further described in FIG. 6.) In step 514, the test generator 106 creates the simulated design 112 and a simulated reference on the test bench 108. The simulated reference is equivalent to a first portion of the functional model 202, or alternatively to the cycle accurate model 302. Now, in step 516, the test generator 106 transmits the test vectors to the test bench 108 for exercising the simulated design 112 and the simulated reference. In step 518, a second portion of the functional model 202, or alternatively the output sequence comparator 304, compares output data from both the simulated design 112 and the simulated reference. In step 520, the second portion of the functional model 202, or alternatively the output sequence comparator 304, reports that a bug exists in the simulated design 112 if the output data sets are not equivalent. Next, in step 522, the test generator 106 correlates the basic blocks, transition arcs, and/or paths exercised by the test vectors with the results from the reporting step (step 520) to localize and identify the basic blocks, transition arcs, and/or paths within the simulated design which operate incorrectly or indeterminately. In step 524, the coverage analysis tool 110 modifies the coverage data to indicate which new basic blocks, transition arcs, and/or paths of interest within the simulated design 112 have now been tested. In step 526, if any basic blocks, arcs, or paths of interest are still to be tested the method returns to step 510, otherwise the process ends.
FIG. 6 is a flowchart of a method for generating a set of test vectors for step 512 of the method of FIG. 5. The method begins in step 602 where the test generator 106 identifies which basic blocks are currently active in the simulated design description. A data base of active basic blocks is maintained by the system by continuously tracking the flow of control and data throughout the simulated system. Then, in step 604, the test generator 106 accesses the coverage database 104 to identify which basic blocks, transition arcs, and paths of interest have not yet been tested. In step 606, the test generator 106 identifies what variables need to be set and what conditions need to occur for the simulated design 112 to exercise, using one set of test vectors, a greatest number of those basic blocks, transition arcs, or paths of interest have not yet been tested. In step 608, the test generator 106 generates a set of test vectors for setting the identified variables and for causing the identified conditions to occur. After step 608, the method for generating a set of test vectors ends.
While the present invention has been described with reference to a preferred embodiment, those skilled in the art will recognize that various modifications may be made. Variations upon and modifications to the preferred embodiment are provided by the present invention, which is limited only by the following claims.
Claims
What is claimed is:
1. An automated simulated electronics design verification system for electronic design automation, comprising: a design database for storing a hardware design coding language representing a circuit design; a coverage database that contains a map of each state and transition arc represented within said circuit design; a test bench that includes a simulated electronics design converted from said hardware design coding language representing a circuit design in the design database, and including an output-log database, and providing for stimulation of said simulated electronics design with a test-frame of test vectors, wherein an output data results and is compiled in the output-log database; a coverage analysis tool for monitoring said output data, and for identifying to the test bench any portions of said simulated electronics design that remain to be tested; a comparator for comparing an output data from said simulated electronics design with at least one of a reference data and a constraint data, and for generating an anomaly report; and a test generator for sending said test-frame of test vectors to the test bench, and connected to receive design database and coverage database information, and for correlating any basic blocks and transition arcs exercised by said test-frame of test vectors with said anomaly report for localizing and identifying any defective ones of said basic blocks and transition arcs; wherein, the test bench exercises portions of said simulated electronics design as directed by the coverage analysis tool.
2. The system of claim 1, wherein: the test generator interprets a simulated electronics design as a state diagram comprising a set of basic blocks interconnected by transition arcs, and it produces a plurality of test vectors for exercising said set of basic blocks and transition arcs, and a computer program is included that processes said simulated electronics design to create said simulated electronics design.
3. The system of claim 1, wherein: the coverage analysis tool monitors internal operations of said simulated electronics design to identify which basic blocks and transition arcs have been exercised, and reports which have not yet been exercised to the test generator for subsequent testing.
4. The system of claim 1, wherein: the test generator provides for a syntax and synthesizability check on a circuit design to be tested, and flags any syntax errors in said circuit design, and indicates if all parts of said circuit design are synthesizable; the test generator provides for expansion of any macros and data structures within said circuit design, and provides for an identification of any and all inputs and outputs; the test generator further provides for an interpretation of said circuit design as a series of basic-blocks that are connected by a series of transition arcs in a state diagram; and the test generator 106 verifies the stability of each basic block within said state diagram independent of all other basic blocks.
5. The system of claim 1, wherein: the test generator provides for an automatic construction of a first set of test vectors for causing each state of a state machine to be visited and each transition arc to be taken and that proves that each basic block in a circuit design are correct; and the test generator provides for a second set of test vectors to prove any user-selected subsets of said basic blocks work together correctly in a path-of-interest.
6. The system of claim 1, further comprising: a functional model coupled to receive test vectors from the test generator and output data from said simulated electronics design for verifying the accuracy of said output data, and providing a comparison of said output data with a set of expected values intended to reflect how said simulated electronics design should operate in response to test vectors generated by the test generator; wherein, the functional model labels said output data from said simulated electronics design as either being correct or incorrect, and flags any failure to generate an output data in response to a test vector.
7. The system of claim 6, wherein: the functional model comprises a non-cycle-accurate model of said simulated electronics design that does not attempt to mimic said simulated electronics design during each cycle of a simulation, and that generates a set of expected values with at least one of a database lookup table and an algorithm.
8. The system of claim 1, further comprising: a cycle-accurate model coupled to receive said test vectors from the test generator, and provides for cycle-for-cycle matches of said output data from the simulated electronics design; and an output-sequence comparator coupled to receive output data from both said simulated electronics design and the cycle-accurate model, and that compares every cycle of said output data to label each of said output data as being one of correct, incorrect, and indeterminate; wherein, the test generator is coupled to receive the results generated by the output sequence comparator, thus creating a second feedback loop, and the test generator correlates said test vectors sent to said simulated electronics design with results from the output sequence comparator to localize and identify whether the basic blocks, transition arcs, and/or paths within said simulated electronics design are operating incorrectly or indeterminately.
9. The system of claim 8, wherein: the test generator, the coverage analysis tool, said simulated electronics design, the functional model, the cycle-accurate model, and the output sequence comparator are embodied as program instruction software modules that execute on a computer that includes a processing unit and a memory.
10. A method of automatic circuit design verification, the method comprising the steps of: importing a design description in a hardware description language with a test generator from a design database; inputting a reference description from another database with a test bench; decomposing said design description into basic blocks, transition arcs, and paths-of-interest to form a state diagram with said test generator; identifying all state machines and all input, output, and internal variables in said design description with said test generator; fetching coverage data that describes how much of said design description has already been tested from a coverage database; generating with said test generator a set of test vectors to test any areas of said design description that have not yet been covered; creating with said test generator a simulated design and a simulated reference on said test bench, wherein said simulated reference is equivalent to a first portion of at least one of a functional model and a cycle-accurate model; transmitting with said test generator a plurality of test vectors to said test bench 108 to exercise said simulated design and said simulated reference; comparing with at least one of a second portion of said functional model and an output sequence comparator any output data from both said simulated design and said simulated reference; reporting with said second portion of the functional model or said output sequence comparator that a bug exists in said simulated design if an output data set is not equivalent; correlating with said test generator said basic blocks, transition arcs, and/or paths exercised by said test vectors with results from a reporting step to localize and identify any basic blocks, transition arcs, and/or paths within said simulated design which operate incorrectly or indeterminately; modifying with a coverage analysis tool a coverage data to indicate which new basic blocks, transition arcs, and/or paths of interest within said simulated design have been tested; and returning to the step of fetching coverage data if any basic block, arc, or path-of-interest remains untested.
Patent Citations (9)
Non-Patent Literature (17)
- Abhijit Ghosh, Sequential Test Generation and Synthesis for Testability at the Register-Transfer and Logic Levels, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 1993, vol. 12, No. 5, pp. 579-598, whole document.
- Steve Carlson et al., HDL Automation Targets Network Designs. Engineering Times, Nov. 11, 1996, No. 927, pages (4), whole document.
- http://www.silicon-sorcery.com/verilog-faq.html.
- Ho et al.; "Architecture Validation for Processors", Proceedings of the 22nd Annual International Symposium on Computer Architectures, pp. 404-413, Jun. 1995.
- Ho et al.; "Validation Coverage Analysis for Complex Digital Designs", Digest of Technical Papers of the IEEE/ACM International Conference on Computer-Aided Design, pp. 146-151, Nov. 1996.
- Armstrong, J. R.; "Efficient Approaches to Testing VHDL DSP Models", 1995 International Conference on Acoustics, Speech and Signal Processing, vol. 5, pp. 2865-2867, May 1995.
- Kapoor et al., "An Automatic Test Bench Generation System", Proceedings of the VHDL International Users Forum, pp. 8-17, May 1994.
- McCabe, P. A.; "VHDL-based System Simulation and Perfromance Measurement", Proceedings of the VHDL International Users Forum, pp. 48-57, May 1994.
- Hoskote et al.; "Automatic extraction of the Control Flow Machine and Application to Evaluating Coverage of Verification Vectors", Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 532-537, Oct. 1995.
- Mingyu et al., "Fault Coverage Analysis in Respect to an FSM Specification", Preceedings of the IEEE INFOCOM '94--Networking for Global Communications, vol. 2, pp. 768-775, Jun. 1994.
- Kapoor, S.; Armstrong, J.R.; Rao, S. R.; "An Automatic Test Bench Generation System", Proceedings of the VHDL International Users Forum, Spring Conference, pp. 8-17, May 4, 1994.
- Armstrong, J.R.; "Efficient Approaches to Testing VHDL DSP Models", International Conference on Acoustics, Speech and Signal Processing, ICASSP-95, vol. 5, pp. 2865-2867, May 12, 1995.
- Yao, M.; Petrenko, A.; v. Bochmann, G.; "Fault Coverage Analysis in Respect to an FSM Specification", 13th Proceedings IEEE INFOCOM '94: Networking for Global Communications, vol. 2, pp. 768-775, Jun. 16, 1994.
- Ho, R. C.; Han Yang, C.; Horowitz, M.A.; Dill, D. L.; "Architecture Validation for Processors", Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 404-413, Jun. 24, 1995.
- Ho, R.C., Horowitz, M. A., "Validation Coverage Analysis for Complex Digital Designs", Digest of Technical Papers from the IEEE/ACM International Conference on Computer-Aided Design, pp. 146-151, Nov. 1996.
- Hoskote, Y. V.: Moundanos, D.; Abraham, J. A.; "Automatic Extraction of the Control Flow Machine in Application to Evaluating Coverage of Verification Vectors", Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Pro, Oct. 4, 1995.
- McCabe, P. A.; "VHDL-Based System Simulation and Performance Measurement", Proceedings of the VHDL International Users Forum. Spring Conference, pp. 48-57, May 4, 1994.