US 6,138,211 AGrant
High-Performance LRU Memory Capable of Supporting Multiple Ports
Issue Date:2000-10-24
•20 Claims
•10 Drawing Sheets
Abstract
In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU memory capable of performing a pseudo replacement policy and supporting multi-port required for operating various blocks included in the microprocessor. The LRU memory comprises an address decoding block for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD and a WRITE.sub.-- WORD in response to the first phase and a second phase of the CLOCK signal, respectively; an LRU storing block; a way hit decoding block for decoding a WAY.sub.-- HIT to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying block for latching a READ.sub.-- DATA from the LRU storing block to produce a DETECTED DATA and modifying it in response to the MODIFY CONTROL signal so as to produce a WRITE.sub.-- DATA to the LRU storing block; and a write way decoding block for analyzing the DETECTED DATA so as to produce a WRITE.sub.-- WAY. This LRU memory reduces the load of superscalar microprocessor required for controlling the cache memory, TLB and BTB and simplifies an interface therebetween, so as to perform the LRU updating process in high speed, thereby improving the performance of the superscalar microprocessor.
Metadata
Assignee
- Hyundai Electronics Industries Co., Ltd.
Inventors
- Mun Weon Ahn
- Hoai Sig Kang
Application Information
Application Number:US 1074180
Filing Date:1998-06-30
Priority Date:1997-06-30
Art Unit:271
Classifications
IPC:
G06F 1212
Field of Search:
711136;160;118;156;159;128;167
Patent Drawings (10 sheets)
Description
Background of the Invention
The present invention relates to a superscalar microprocessor, more particularly, to an LRU (Least Recently Used) memory for storing the history of memory access which is made for replacement or updating the content of the memory.
As is well known in this art, the superscalar structured microprocessor performs two or more instructions at every cycle. For doing this, a cache memory, TLB (Translation Lookaside Buffer), BTB (Branch Target Buffer), and etc. must support two or more ports and are in general implemented by 4-way set associative.
At this time, for the purpose that LRU memory required for implementation of 4-way set associative supports two or more ports, it is noted that the results of entries being simultaneously accessed should be reflected to change the entry access history (LRU data).
As an example, considering the memory access result of a cache memory for supporting two port, there are cases that both of two ports are missed; that the first port is missed and the second port is hit; that the first port is hit and the second port is missed; and that both of two ports are hit. The cache memory access information corresponding these four cases is discriminated so as to reflect the entry access history (that is, LRU data), in which the operations of accessing the LRU memory, modifying the LRU data, and then writing the modified LRU data to the LRU memory should be performed at every cycle. Such operations are made in a cache control block in the conventional.
In this case, the LRU data path is read out from the LRU memory and transferred to the cache control block. The modification (or reflection) of the LRU data path is made in the cache control block and then transferred to the LRU memory to be recorded. This may be a critical path of the cache memory access.
FIG. 1 illustrates a conventional 8-entry 4-way set associative LRU memory for supporting two ports, which includes an address decoder block 102 and an LRU SRAM block 104.
Referring to FIG. 1, the address decoder block 102 latches and decodes the 3-bit index address for 8 entries in synchronization with a CLOCK. In addition, when the LRU.sub.-- READ signal is activated, the word line signal WORD[7:0] is made in synchronization with the READ.sub.-- TIME signal and then outputted to the LRU SRAM block 104. Also, when the LRU.sub.-- WRITE signal is activated, the word line signal WORD[7:0] is made based on the decoding result in synchronization with the WRITE.sub.-- TIME signal so as to be outputted to the LRU SRAM block 104.
When the LRU.sub.-- READ signal is activated, the LRU SRAM block 104 reads only the enabled entry in response to the WORD[7:0] supplied from the address decoder block 102, and produces the stored 3-bit READ.sub.-- DATA to a control block (not shown). Alternatively, when the LRU.sub.-- WRITE signal is activated, the LRU SRAM block 104 stores the externally applied 3-bit WRITE.sub.-- DATA to the enabled entry in response to the WORD[7:0] supplied from the address decoder block 102.
The conventional LRU memory as described above, can be easily implemented, but has a difficulty in that the control block should control the READ.sub.-- TIME, WRITE.sub.-- TIME, WRITE.sub.-- DATA, and etc., in high accuracy. Also, there is a burden in that the operation of the receiving the READ.sub.-- DATA and generating the WRITE.sub.-- DATA (LRU updating data) reflecting the way-hit information, must be speedily performed. Moreover, there is a problem that, since all of the reading out operation from the LRU memory and the operations of the control block for receiving the read out data READ.sub.-- DATA and for generating and then transferring the WRITE.sub.-- DATA to the LRU memory, must be performed at every cycle, these operations impede the implementation of high performance.
Summary of the Invention
Accordingly, the present invention is provided for solving the above problems. The object of the present invention is to provide an LRU memory for supporting a high performance multi-port, capable of improving the performance of the superscalar microprocessor by speedily performing the LRU modification and simply implementing the control block.
To accomplish the above object of the present invention, there is provided an LRU memory capable of performing a pseudo replacement policy, comprising: an address decoding means for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD in response to a first phase of a CLOCK signal and to produce a WRITE.sub.-- WORD in response to a second phase of the CLOCK signal; an LRU storing means for storing a plurality of LRU data, producing an LRU data from a cell corresponding to the READ.sub.-- WORD as a READ.sub.-- DATA, and writing a WRITE.sub.-- DATA to a cell corresponding to the WRITE.sub.-- WORD; a way hit decoding means for decoding a WAY.sub.-- HIT so as to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying means for latching the READ.sub.-- DATA from the LRU storing means to produce a DETECTED DATA and modifying the READ.sub.-- DATA in response to the MODIFY CONTROL signal so as to producing the WRITE.sub.-- DATA to the LRU storing means; and a write way decoding means for analyzing the DETECTED DATA in accordance with the pseudo replacement policy, so as for producing a WRITE.sub.-- WAY.
The LRU memory further comprises a control means for generating a plurality of control signals required for the LRU memory in response to a CLOCK signal, an LRU.sub.-- READ signal used for enabling a read operation for the LRU memory, and an LRU.sub.-- WRITE signal used for enabling a write operation for the LRU memory; and wherein said control means produces: a READ PRECHARGE.sub.-- TIME signal which becomes non-active in response to a first phase of the CLOCK signal and being used for precharging the READ.sub.-- DATA; a READ.sub.-- TIME signal activated when the CLOCK signal is the first phase, the READ PRECHARGE.sub.-- TIME signal is non-active and the LRU.sub.-- READ is active, and being used for producing the READ.sub.-- WORD in said address decoding means; a READ LATCH TIME signal which becomes active after an activation of the READ.sub.-- TIME signal and being used in said data modifying means; an LRU MODIFY.sub.-- TIME signal activated in responsive to the second phase of the CLOCK signal and being used for generating the MODIFY CONTROL signal in said way hit decoding means; and a WRITE.sub.-- TIME signal activated when the CLOCK signal is the second phase, the LRU MODIFY.sub.-- TIME signal is active and the LRU.sub.-- WRITE signal is active, and being used for producing the WRITE.sub.-- WORD in said address decoding means. This control means may further produces a WAY DECODER LATCH.sub.-- TIME signal activated when the CLOCK signal is the second phase, the LRU MODIFY.sub.-- TIME signal is active and the LRU.sub.-- READ is active, and being used for producing the WRITE.sub.-- WORD in said write way decoding means.
According to the preferred embodiment of the present invention, the LRU memory further comprises a plurality of ports and the INDEX.sub.-- ADDRESS includes a plurality of port INDEX.sub.-- ADDRESS signals, for example A.sub.-- INDEX.sub.-- ADDRESS signal and B.sub.-- INDEX.sub.-- ADDRESS signal, each of which relates to one port (that is, A-port and B.sub.-- port, respectively). Also, the address decoding means compares the port INDEX.sub.-- ADDRESS signals with one another, and if all of the port INDEX.sub.-- ADDRESS signals are the same, said address decoding means makes only one WRITE.sub.-- WORD related to one port activated. The address decoding means may also produce a COMPARE.sub.-- HIT signal activated when the plurality of said port INDEX.sub.-- ADDRESS signals are the same with each other and provide the COMPARE.sub.-- HIT signal to said way hit decoding means.
According to the preferred embodiment of the present invention, the WRITE.sub.-- WORD includes a first port WRITE.sub.-- WORD (e.g. A.sub.-- WRITE.sub.-- WORD) and a second port WRITE.sub.-- WORD (e.g. B.sub.-- WRITE.sub.-- WORD); the WRITE.sub.-- DATA includes a first port WRITE.sub.-- DATA (e.g. A.sub.-- WRITE.sub.-- DATA) and a second port WRITE.sub.-- DATA (e.g. B.sub.-- WRITE.sub.-- DATA); the READ.sub.-- WORD includes a first port READ.sub.-- WORD (e.g. A.sub.-- READ.sub.-- WORD) and a second port READ.sub.-- WORD (e.g. B.sub.-- READ.sub.-- WORD); and the READ.sub.-- DATA includes a first port READ.sub.-- DATA (e.g. A.sub.-- READ.sub.-- DATA) and a second port READ.sub.-- DATA (e.g. B.sub.-- READ.sub.-- DATA).
The write way decoding means may determine the least recently used way as the WRITE.sub.-- WAY.
In addition, the LRU memory can support a single port as well as multiple ports.
Brief Description of the Drawings
For a more complete understanding of the present invention and the advantage thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 illustrates a conventional LRU memory for supporting 8-entry and 4-way set associative 2-port;
FIG. 2 is a block diagram of a high-performance LRU memory for supporting a multi-port according to one embodiment of the present invention;
FIG. 3 is a detailed circuit diagram of the address decoder block shown in FIG. 2;
FIG. 4 is a logic circuit diagram for illustrating an implementation of the LRU SRAM block shown in FIG. 2;
FIG. 5 is a detailed logic circuit diagram of the self time generating block shown in FIG. 2;
FIG. 6 is a signal timing chart at the self time generating block shown in FIG. 2;
FIG. 7 is a detailed logic circuit diagram of the way hit decoder block shown in FIG. 2;
FIG. 8 is a detailed logic circuit diagram of the data detect/modify block shown in FIG. 2;
FIG. 9 is a detailed logic circuit diagram of the write way decoder block shown in FIG. 2;
FIG. 10 is a block configuration of an LRU memory for supporting a single port according to the preferred embodiment of the present invention.
Detailed Description of the Present Invention
The preferred embodiment of the present invention will hereinafter be described in detail with reference to the accompanying drawings.
At first, the technical distinctive characteristic of the present invention is that the LRU memory supports in itself the functions which are implemented at the control block in the conventional. So, though the memory structure becomes a little complex, but the simplification of the data path and the control path can be attained so that the high performance of the object of the present invention can be implemented.
In addition, according to the present invention, the LRU memory is read out and the read out data is modified by the way-hit information. The critical path of the LRU memory access for recording the modified LRU data to the LRU memory is divided into an LRU memory read/modification data path and an LRU modification/record path so as for simultaneously performing, which results in realization of high performance.
FIG. 2 is a block configuration diagram of LRU memory for supporting high performance multi-ports according to a preferred embodiment of the present invention, which is an implementation example of 8-entry 4-way associative LRU memory for supporting 2 ports.
As shown in FIG. 2, the LRU memory of the present invention, comprises an address decoder block 202, an LRU SRAM block 204, a self time generating block 206, a write way decoder block 212, a data detect/modify block 210 and a way hit decoder block 208.
Referring to FIG. 2, in the address decoder block 202, since this embodiment supports 8 entries, both of A.sub.-- port and B.sub.-- port receive 3-bit index address and latch it in synchronization with the CLOCK externally applied thereto, and then decode the 3-bit index address. Both of A.sub.-- port and B.sub.-- port also transfer 8-bit READ.sub.-- WORD to the LRU SRAM block which will be described below, in response to the READ.sub.-- TIME signal provided from the self time generating block 206 which is also described below, and both ports generate the WRITE.sub.-- WORD in response to the WRITE.sub.-- TIME signal provided from the self time generating block 206, so as to transfer the WRITE.sub.-- TIME signal to the LRU SRAM block 204.
In addition, in the address decoder block 202, when the A.sub.-- port and B.sub.-- port access the same entry, the modified data should be written only one time. Therefore, an A.sub.-- port index and a B.sub.-- port index are compared with each other, and if the comparison result is "same", a COMPARE.sub.-- HIT signal is activated to the way hit decoder block 208 which will be described below, and then B WRITE.sub.-- WORD is disabled and A WRITE.sub.-- WORD is enabled.
Like this, the address decoder block 202 adopted by the LRU memory of the present invention, can be implemented by a plurality of logic gates, as shown in FIG. 3, which should be considered as only one example.
In other words, the address decoder block 202 adopted as an example according to the preferred embodiment of the present invention, comprises latch blocks 2021 and 2023, a B.sub.-- port read/write word generating block 2027 and a comparator 2029. The latch block 2021 includes three latches LH31, LH32 and LH33 each of which receives and latches 3-bit of A.sub.-- port index address. The latch block 2023 includes three latches LH34, LH35 and LH36 each of which receives 3-bit of B.sub.-- port index address. The B.sub.-- port read/write word generating block 2027 receives and decodes the index address from the latch block 2023 in response to the READ.sub.-- TIME and the WRITE.sub.-- TIME signals, so as to generate 8-bit of WRITE.sub.-- WORD and READ.sub.-- WORD for B.sub.-- port. The comparator 2029 compares the A.sub.-- port index address from the latch block 2021 with the B.sub.-- port index address from the latch block 2023 so as to produce a COMPARE.sub.-- HIT signal.
Referring to FIG. 3, each of latches LH31, LH32 and LH33 of the latch block 2021, latches the 3-bit index address applied thereto through the A.sub.-- port and then transfers it to the next stage of A.sub.-- port read/write word generating block 2025 in synchronization with the CLOCK signal and the inverted CLOCK signal from an inverter I31, respectively, during the high state duration of the CLOCK. Also, each of latches LH34, LH35 and LH36 of the latch block 2023, latches the 3-bit index address applied thereto through the B.sub.-- port and then transfers it to the next stage of B.sub.-- port read/write word generating block 2027 in synchronization with the CLOCK signal and the inverted CLOCK signal from the inverter I31, when the CLOCK signal is a high level.
Next, the A.sub.-- port read/write word generating block 2025, includes a first NAND gate group, a first NOR gate group and a second NOR gate group. The first NAND gate group is composed of eight NAND gates each of which has 3-inputs for selectively receiving among the outputs of three latches LH31, LH32 and LH33 and the three inverted outputs from the inverters I32, I33 and I34. The first NOR gate group includes eight 2-input NOR gates each of which receives an output of the corresponding NAND gate in the first NAND gate group and the inverted READ.sub.-- TIME signal from the inverter I38, in which the inverted READ.sub.-- TIME signal is made by inverting the READ.sub.-- TIME signal provided from the self time generating block 206 of FIG. 2, so that the first NOR gate group generates A.sub.-- READ.sub.-- WORD[7:0] . The second NOR gate group includes eight 2-input NOR gates each of which receives an output of the corresponding NAND gate in the first NAND gate group and the inverted WRITE.sub.-- TIME signal from the inverter I39, in which the inverted WRITE.sub.-- TIME signal is made by inverting the WRITE.sub.-- TIME signal provided from the self time generating block 206 of FIG. 2, so that the second NOR gate group generates A.sub.-- WRITE.sub.-- WORD[7:0]. Here, it can be seen that the first NAND gate group within the block 2025 and the inverters I32, I33 and I34 are commonly used for generating the A.sub.-- READ.sub.-- WORD as well as the A.sub.-- WRITE.sub.-- WORD.
Also, the B.sub.-- port read/write word generating block 2027, includes a second NAND gate group, a third NOR gate group and a fourth NOR gate group. The second NAND gate group includes eight NAND gates each of which has three inputs for selectively receiving among the outputs of three latches LH34, LH35 and LH36 and the three inverted outputs from the inverters I35, I36 and I37. The third NOR gate group includes eight 2-input NOR gates each of which receives an output of the corresponding NAND gate in the second NAND gate group and the inverted READ.sub.-- TIME signal from the inverter I38, in which the inverted READ.sub.-- TIME signal is made by inverting the READ.sub.-- TIME signal provided from the self time generating block 206 of FIG. 2, so that the third NOR gate group generates B.sub.-- READ.sub.-- WORD[7:0]. The fourth NOR gate group includes eight 2-input NOR gates each of which receives an output of the corresponding NAND gate in the second NAND gate group and the inverted WRITE.sub.-- TIME signal from the inverter I39, in which the inverted WRITE.sub.-- TIME signal is made by inverting the WRITE.sub.-- TIME signal provided from the self time generating block 206 of FIG. 2, so that the fourth NOR gate group generates B.sub.-- WRITE.sub.-- WORD[7:0]. Here, it can be seen that the second NAND gate group within the block 2027 and the inverters I35, I36 and I37 are commonly used for generating the A.sub.-- READ.sub.-- WORD as well as the A.sub.-- WRITE.sub.-- WORD.
In addition, the comparator 2029 receives the outputs of the respective latches LH31, LH32 and LH33 of the latch block 2021 and the outputs of the respective latches LH34, LH35 and LH36 of the latch block 2023 so as to compare them, thereby generating a COMPARE.sub.-- HIT signal based on the comparing result and applying it to the way hit decoder block 208 described below. When the A.sub.-- port and B.sub.-- port access the same entry, the modified LRU data is written only once. So, in case that the A.sub.-- port index address is the same with B.sub.-- port index address, the B.sub.-- WRITE.sub.-- WORD is disabled and the A.sub.-- WRITE.sub.-- WORD is enabled by enabling the COMPARE.sub.-- HIT signal.
Returning to FIG. 2, the LRU SRAM block 204 is a 8*3 SRAM cell array block for supporting 2 port (A.sub.-- port and B.sub.-- port) access dual port (read port and write port) and stores LRU history bit by entries. Here, the reason for supporting the dual port is that the read operation and the write operation are separated, thereby concurrently processing the write operation and the read port precharge operation, so that the LRU read data path and the modification/write data path can be divided.
The respective cell constituting the LRU SRAM block of the present invention, as shown in FIG. 4 as an example, is dual-structured. This cell includes six transistors TR41-TR46, two inverters I41 and I42. So, it can be implemented a dual port in which a simultaneous access to the both A.sub.-- port and B.sub.-- port can be supported and the read operation and the write operation can be separated, thereby realizing the high performance by precharging the read data port at write duration after the read operation.
That is, the respective SRAM cell comprises transistors TR41, TR42, TR43, TR44, TR45 and TR46 and inverters I41 and I42. For the transistor TR41, the gate thereof is coupled to the A.sub.-- WRITE.sub.-- WORD line and the source thereof is coupled to the A.sub.-- WRITE.sub.-- DATA line. The gate of the transistor TR42 is coupled to the output of the inverter I41 and the source thereof is coupled to a ground. In the transistor TR43, the gate thereof is coupled to A.sub.-- READ.sub.-- WORD line, the source thereof is coupled to the drain of the transistor TR42 and the drain thereof is coupled to A.sub.-- READ.sub.-- DATA line. In the transistor TR44, the gate thereof is coupled to B.sub.-- WRITE.sub.-- WORD, the source thereof is coupled to B.sub.-- WRITE.sub.-- DATA line and the drain thereof is coupled to the output of the inverter I42. In the transistor TR45, the gate thereof is coupled to the output of the inverter I41 and the source thereof is coupled to the ground. In the transistor TR46, the gate thereof is coupled to the B.sub.-- READ.sub.-- WORD line, the source thereof is coupled to the drain of the transistor TR45 and the drain thereof is coupled to the B.sub.-- READ.sub.-- DATA line. Here, the drain of the transistor TR41, the input of the inverter I41, the drain of the transistor TR44 and the output of the inverter I42 are commonly coupled, and the input of the inverter I41, the gate of the transistor TR42, the output of the inverter I42 and the gate of the transistor TR45 are commonly coupled.
Returning to FIG. 2, the self time generating block 206 is a block for generating in itself control clocks and control signals, in which the control clocks and the control signals are required to be complex and be accurate for the purpose of realizing a high speed operation intended in this invention. The self time generating block 206 generates the READ.sub.-- TIME signal and the WRITE.sub.-- TIME signal based on the CLOCK signal, the LRU.sub.-- READ signal and the LRU.sub.-- WRITE signal which are applied from an external control block (not shown), thereby providing them the above-mentioned address decoder block 202. Also, the block 206 generates a WAY DECODER LATCH.sub.-- TIME signal to provide it to the write way decoder block 208 described below and generates a READ LATCH.sub.-- TIME signal and a READ PRECHARGE.sub.-- TIME signal to provide it to the data detect/modify block 210. The block 206 also generates an LRU MODIFY.sub.-- TIME signal to provide it to the way hit decoder block 208.
The timing of various signals generated in the self time generating block 206 is in detail illustrated in FIG. 6. Referring to this figure, it can be known through this figure that the active duration of the READ.sub.-- TIME signal (which is a "high" active signal) doesn't overlap with the active duration of the READ PRECHARGE.sub.-- TIME signal (which is a "low" active signal) and the active duration of the READ PRECHARGE.sub.-- TIME signal (which is a "low" active signal) doesn't overlap with the active duration of the READ LATCH.sub.-- TIME signal (which is a "high" active signal). Also, after the LRU MODIFY.sub.-- TIME signal (which is a "high" active signal) is enabled, the WRITE.sub.-- TIME signal (which is a "high" active signal) is activated, and the active duration of the READ LATCH.sub.-- TIME signal (which is a "high" active signal) doesn't overlaps with the active duration of the WAY DECODER LATCH.sub.-- TIME (which is a "high" active signal). Therefore, the timing relationship between such control clocks plays a very important role in implementing a high performance multi-port LRU memory which is intended to acquire in this invention.
At this time, the READ.sub.-- TIME signal among the signals generated in the self time generating block 206 is enabled when the eight decoded lines are effective, in which the eight decoded lines are controlled by decoding the 3-bit index address. The READ.sub.-- TIME signal is then disabled when the READ.sub.-- DATA becomes effective by sufficiently performing an operation regarding to the READ.sub.-- WORD. The WRITE.sub.-- TIME signal is activated when the write data is effective in the data detect/modify block 210 and is deactivated when the SRAM cell of the LRU SPAM block 204 is updated by sufficiently performing an operation regarding to the WRITE.sub.-- WORD. The LRU MODIFY.sub.-- TIME signal is enabled when the write data is latched in the data detect/modify block 210 and the way hit information gets an information required for modifying the LRU data modification from the way hit decoder block 208, and it is disabled when the way hit decoding result is fully reflected to the LRU data in the data detect/modify block 210.
In addition, the READ PRECHARGE.sub.-- TIME signal among the signals generated in the self time generating block 206 becomes active when the READ.sub.-- WORD signal is disabled, and it becomes nonactive before the READ.sub.-- WORD signal is enabled. The READ LATCH.sub.-- TIME signal represents the time at which a latching the READ.sub.-- DATA is made when the READ.sub.-- WORD signal becomes active and the READ.sub.-- DATA becomes effective. The WAY DECODER LATCH.sub.-- TIME signal is a signal used for latching the decoded write way data in the write way decoder block 208.
As described above, the self time generating block 206 for generating various signal required for high speed processing, can be implemented using 2-phase non-overlap clock driver, as shown in FIG. 5 as one example, for the purpose that it is not affected by the frequency change of the CLOCK signal. Here, the READ PRECHARGE.sub.-- TIME signal is a "low" active signal and the other signals are "high" active signals.
As shown in FIG. 6, the operations related to "LRU data reading" are performed in response to the first phase (e.g. "high" state) of the CLOCK signal, while the operations related to "LRU data writing" are performed in response to the second phase (e.g. "low" state) of the CLOCK signal. So, the operations of the LRU memory can be in parallel processed, thereby improving the operation speed.
That is, referring to FIG. 5, the READ PRECHARGE.sub.-- TIME signal generated in the self time generating block 206, can be generated through a logic circuit group including inverters I51, I52 and I53 and a NAND gate ND51. The inverter I51 receives and inverts the CLOCK signal. The NAND gate ND51 is coupled for receiving the output of the inverter I51 and the output of the inverter I55. The inverters I52 and I53 are coupled in series for receiving the output of the NAND gate ND51.
Also, the READ.sub.-- TIME signal generated in the self time generating block 206, can be generated through a logic circuit group including a NAND gate ND52, two inverters I54 and I55 and a NOR gate NR51. The NAND gate ND52 is coupled for receiving the CLOCK signal and the output of the inverter I60. The inverters I54 and I55 are coupled in series for receiving the output of the NAND gate ND52 and the NOR gate NR51 is coupled for receiving the output of the inverter I55 and the LRU.sub.-- READ signal provided from an external control block. The READ LATCH.sub.-- TIME signal can be generated through a logic circuit group including two inverters I56 and I57 which are coupled in series for receiving the output of the NOR gate NR51.
In the meantime, the LRU MODIFY.sub.-- TIME signal generated in the self time generating block 206, can be generated through a logic circuit group including inverters I58, I59, I60 and I61 and a NAND gate ND53. The inverter I58 is coupled for receiving the CLOCK signal and the NAND gate ND53 is coupled for receiving the output of the inverter I55 and the output of the inverter I58. The three inverters I59, I60 and I61 are coupled in series for receiving the output of the NAND gate ND53.
Next, the WAY DECODER LATCH.sub.-- TIME signal generated in the self time generating block 206, can be generated through a logic circuit group including a NAND gate ND54 and a NOR gate NR52. The NAND gate ND54 is coupled for receiving the output of the inverter I61 and the output of the inverter I58 and the NOR gate NR52 is coupled for receiving the LRU.sub.-- READ signal applied from an external control block and the output of the NAND gate ND54. Here, the LRU.sub.-- READ signal and the LRU.sub.-- WRITE signal are "low" active signals. The WRITE.sub.-- TIME signal can be generated through a NOR gate NR53 which is coupled for receiving the output of the NAND gate ND54 and the LRU.sub.-- WRITE signal applied from an external control block.
Referring again to FIG. 2, the way hit decoder block 208 receives the way hit signal from an TAG block of an external cache and obtains an information regarding to the modified bit based on the pseudo LRU replacement policy, in which the way hit signal is composed of 4 bits for respective ports A and B. Also, the block 208 generates a modify control signal based on the LRU MODIFY.sub.-- TIME signal applied from the above-described self time generating block 206, and provides it to the data detect/modify block 210, in which the modify control signal is 6 bits for respective ports A and B. If the COMPARE.sub.-- HIT signal generated from the above-described address decoder block 202 is enabled, the block 208 generates the modify control signal using sequentially the way hit information of A.sub.-- port and B.sub.-- port, so as to reflect it to the modify control signal of A.sub.-- port.
At this time, the modify control signal can be made by 6 bits per port, which means that the modify control signal includes two signals, that is a set enable signal and a reset enable signal, per bit of the LRU data. This is used in setting (that is, changing from logic "0" to logic "1") or resetting (that is, changing from logic "1" to logic "0") the LRU bit to be intended to change based on the decoding result of the way hit or in resetting, which makes it easy and faster to modify the LRU data, thereby making the high performance operation intended in the present invention possible. For supporting this function, the read data latch circuit in the data detect/modify block 210 described below, supports the setting and the resetting functions.
FIG. 7 shows the detailed logic circuit diagram of the way hit decoder block according to the present invention, which has such a function as above.
Referring to FIG. 7, the way hit decoder block 208 includes NAND gate groups ND71, ND72, ND73, ND74, ND75, ND76 and ND77, OR gate groups OG71, a inverter I71, and inverter groups I72, I74 and I75. The inverter group I72 includes 4 inverters each of which receives a corresponding bit of the A.sub.-- WAY.sub.-- HIT[3:0] signal. The NAND gate group ND 71 includes 4 NAND gates each of which is coupled for receiving the corresponding output of the inverter group I72 and an inverted COMPARE.sub.-- HIT signal from the inverter I71, in which the inverted COMPARE.sub.-- HIT signal is made by inverting the COMPARE.sub.-- HIT signal provided from the address decoder block 202 of FIG. 2. The NAND gate group ND76 includes 4 NAND gates each of which is coupled for receiving a corresponding bit of B.sub.-- WAY.sub.-- HIT[3:0] and the corresponding output of the inverter group I72. The NAND gate group ND77 includes 4 NAND gates each of which is coupled for receiving the corresponding output of the NAND gate group ND76 and the corresponding output of the inverter group I72. The OR gate group OG71 includes 4 OR gates each of which is coupled for receiving the corresponding output of the NAND gate group ND77 and the inverted COMPARE.sub.-- HIT signal from the inverter I71. The NAND gate group ND72 includes 4 NAND gate each of which is coupled for receiving the corresponding output of the NAND gate group ND71, the corresponding output of the OR gate group OG71 and the LRU MODIFY.sub.-- TIME signal provided from the self time generating block 206 of FIG. 2. The NAND gate group ND73 includes 2 NAND gates, in which one NAND gate is coupled for receiving the two outputs of the NAND gate group ND72 so as to produce an A0.sub.-- CLEAR signal and the other NAND gate is coupled for receiving the other two outputs of the NAND gate group ND72 so as to produce an A0.sub.-- SET signal. The inverter group I74 includes 4 inverters each of which is coupled for receiving the corresponding output of the NAND gate group ND72 so as to produce an A1.sub.-- CLEAR, an A1.sub.-- SET, an A2.sub.-- CLEAR and an A2.sub.-- SET, respectively. Here, the A1.sub.-- CLEAR, the A1.sub.-- SET, the A2.sub.-- CLEAR, and the A2.sub.-- SET constitutes a part of the modify control signals for A.sub.-- port which is composed of 6 bits.
In addition, the NAND gate group ND74 includes 4 NAND gates each of which is coupled for receiving the corresponding bit of the B.sub.-- WAY.sub.-- HIT[3:0] supplied from an external cache tag block and the LRU MODIFY.sub.-- TIME signal provided from the self time generating block 206 of FIG. 2. The NAND gate group ND75 includes 2 NAND gates, in which one NAND gate is coupled for receiving the first two outputs of the NAND gate group ND74 so as to produce a B0.sub.-- CLEAR and the other NAND gate is coupled for receiving the remnant outputs of the NAND gate group ND74 so as to produce a B0.sub.-- SET. The inverter group I75 includes 4 inverters each of which is coupled for receiving the corresponding output of the NAND gate group ND74, so as to produce a B1.sub.-- CLEAR, a B1.sub.-- SET, a B2.sub.-- CLEAR and a B2.sub.-- SET, respectively.
Referring back to FIG. 2, the data detect/modify block 210 is coupled to the above-described LRU SRAM block 204 through A.sub.-- READ.sub.-- DATA line, B.sub.-- READ.sub.-- DATA line, A.sub.-- WRITE.sub.-- DATA line and B.sub.-- WRITE.sub.-- DATA line each of which is composed of 3 bit. The data detect/modify block 210 precharges the READ.sub.-- DATA lines in response to a READ PRECHARGE.sub.-- TIME signal provided from the self time generating block 206 described above, and detects the READ.sub.-- DATA so as to store the detected READ.sub.-- DATA in synchronization with the READ LATCH.sub.-- TIME signal, in which the detected A.sub.-- READ.sub.-- DATA is stored in two places and the detected B.sub.-- READ.sub.-- DATA is stored in one place. The block 210 also makes a detect data based on the A.sub.-- port stored data so as to transfer it to the write way decoder block 212 and makes an LRU data so as to transfer it to an external control block which is not shown.
In addition, the data detect/modify block 210 receives the modify control signal from the way hit decoder block 208 and changes the other A.sub.-- port latch data and B.sub.-- port latch so as to provide the changed modify LRU data as write data, in which the modify control signal is needed for modifying the LRU modification and is composed of 6 bits per bit.
FIG. 8 shows one embodiment of the data detect/modify block 210 described above, which illustrates only a portion for one bit among 3 bits for A.sub.-- port and 3 bits for B.sub.-- port. In FIG. 8, the READ.sub.-- DATA is applied from the LRU SRAM block 204 of FIG. 2 and the READ.sub.-- DATA line is precharged to "high" level by the READ PRECHARGE.sub.-- TIME which is a "low" active signal. If the READ.sub.-- WORD signal is enabled, the corresponding data to the word is detected. At this time, the two inverters I81 and I82 may be replaced with amplifiers, if necessary.
Referring to FIG. 8, the data detect/modify block 210 includes two PMOS transistors TR81 and TR82 and a plurality of inverters I81, I82, I83, I84 and I85. The PMOS transistors TR81 and TR82 are applied with the READ PRECHARGE.sub.-- TIME signal provided from the self time generating block 206, through respective gates. The inverters I81 and I82 are coupled in series for receiving the A.sub.-- READ.sub.-- DATA and the inverter I85 is coupled for receiving the READ LATCH.sub.-- TIME signal. Here, the drain-source paths of the PMOS transistors TR81 and TR82 are coupled in series between the A.sub.-- READ.sub.-- DATA line and the B.sub.-- READ.sub.-- DATA line and the common source node thereof is coupled for receiving the power supply voltage.
Also, the data detect/modify block 210 further comprises three latches LH81, LH82 and LH83 which store data synchronizing with the READ LATCH.sub.-- TIME when the READ.sub.-- DATA is detected. The latch LH81 stores (or latches) data only in case of A.sub.-- port, and makes a detect data and an LRU data based on the latched data. The latch LH82 stores data in case of A.sub.-- port, and sets or makes the latched data clear so as to produce the WRITE.sub.-- DATA, when the A.sub.-- SET signal or the A.sub.-- CLEAR signal are enabled. The latch LH83 stores only in case of B.sub.-- port, and when the B.sub.-- SET signal or the B.sub.-- CLEAR signal are enabled, the latch LH83 makes the latched data set or clear so as to produce the WRITE.sub.-- DATA.
Here, the two latches LH82 and LH83 have substantially the same configuration with each other. For example, the latch LH82 includes a plurality of MOS transistors TR85, TR86, TR87 and TR88, inverters I86, I87 and I88. The sources of the transistors TR85 and TR86 are commonly coupled to the output of the inverter I82 and the drains thereof are commonly coupled. The gate of the transistor TR85 is applied with the READ LATCH.sub.-- TIME signal and the gate of the transistor TR86 is coupled for receiving the output of the inverter I85. The inverter I86 is coupled for receiving the common output of the transistors TR85 and TR86. The inverter I87 is coupled for receiving the output of the inverter I86 and its output is coupled to the common output of the transistors TR85 and TR86. The inverter I88 is coupled for receiving the output of the inverter I86 and its output is coupled to the A.sub.-- WRITE.sub.-- DATA line. The transistor TR87 receives the A.sub.-- CLEAR signal through its gate and its source is coupled to the ground and its drain is coupled to the common drain of the transistors TR85 and TR86. The transistor TR88 receives the A.sub.-- SET signal through its gate and its source is coupled to the ground and its drain is coupled to the output of the inverter I86 and to the input of the inverter I87.
Therefore, the data detect/modify block 210 stores the data to the respective latches LH81, LH82 and LH83 in accordance with the READ LATCH.sub.-- TIME signal, when the READ.sub.-- DATA is detected. In more detail, the latches LH81 and LH82 are used for storing the data in case of the A.sub.-- port, while only the latch LH83 is used for storing the data in case of the B.sub.-- port. When the SET signal or the CLEAR signal provided from the way hit decoder block are activated with the data being stored as such, the corresponding latch LH82 or LH83 is set or made to be clear so as to transfer the WRITE.sub.-- DATA to the LRU SRAM block 204.
Referring back to FIG. 2, the write way decoder block 212 receives the detected 3-bit data from the data detect/modify block 210 and discriminates the least recently used way based on a pseudo LRU replacement policy. The write way decoder block 212 also latches the discriminated result in accordance with the WAY DECODER LATCH.sub.-- TIME signal provided from the above-described self time generating block 206, so as to produce the WRITE.sub.-- WAY signal. One example of such a write way decoder block 212 is shown in FIG. 9.
Referring to FIG. 9, the write way decoder block 212 adopted in the present invention, includes a plurality of inverters I91, I92, I93, I94, I95, I96 and I97, four NAND gates ND91, ND92, ND93 and ND94 and four latches LH91, LH92, LH93 and LH94. The three inverters I91, I92 and I93 receives 3 bits of the detected data, respectively and the three inverters I94, I95 and I96 are coupled to the outputs of the inverters I91, I92 and I93, respectively. The NAND gate ND91 is coupled for receiving the output of the inverter I94 and the output of the inverter I95; the NAND gate ND92 is coupled for receiving the output of the inverter I91 and the output of the inverter I95; the NAND gate ND93 is coupled for receiving the output of the inverter I92 and the output of the inverter I96; the NAND gate ND94 is coupled for receiving the output of the inverter I92 and the output of the inverter I93. The four latches LH91, LH92, LH93 and LH94 receive the corresponding output of the NAND gates ND91, ND92, ND93 and ND94, respectively, and also receive the WAY DECODER LATCH.sub.-- TIME signal as latch enable signal and the inverted WAY DECODER LATCH.sub.-- TIME signal from the inverter I97 as latch disable signal.
Accordingly, the write way decoder block 212 decodes the discriminated 3-bit data, and if the detected data [1] is a logic "1" and the detected data [0] is a logic "1", since the way.sub.-- 0 is the least recently used way, the write way decoder block 212 generates a logic "0001" as the WRITE.sub.-- WAY[3:0]. Alternatively, if the detected data[1] is a logic "0" and the detected data [0] is a logic "1", the write way decoder block 212 recognizes the way.sub.-- 1 as the least recently used way, so as to produce a logic "0010" of WRITE.sub.-- WAY{3:0]. Similarly, if the detected data [2] is a logic "1" and the detected data [0] is a logic "0", the write way decoder block 212 produces a logic "0100" of WRITE.sub.-- WAY[3:0], and if the detected data [2] is a logic "0" and the detected data [0] is a logic "0", the write way decoder block 212 produces a logic "1000" of WRITE.sub.-- WAY[3:0].
This is because the self updating LRU memory according to the present invention uses LRU[0], LRU[1] and LRU[2] as a group bit, a low group bit and a high group bit, respectively, so as to store the pseudo LRU history. For the LRU[0] as the group bit, if the WAY.sub.-- HIT is a low group (that is, if the way.sub.-- 0 or the way.sub.-- 1 are hit), the LRU[0] becomes a logic "0", and if the WAY.sub.-- HIT is a high group (that is, if the way.sub.-- 2 or the way.sub.-- 3 are hit), the LRU[0] becomes a logic "1". For the low group bit of LRU[1], if the way.sub.-- 0 of the WAY.sub.-- HIT is hit, the LRU[1] becomes a logic "0", and if the way.sub.-- 1 is hit, the LRU[1] becomes a logic "1". The LRU[2] as the high group bit becomes a logic "0", if the way.sub.-- 2 of the WAY.sub.-- HIT is hit, and it becomes a logic "1" if the way.sub.-- 3 is hit.
In the meantime, in the present invention, the function of the LRU[2:0] of the pseudo LRU replacement policy may be changed for implementation as required. For example, the group bit, the low group bit and the high group bit may be exchanged with one other. For such an exchange, the write way decoder block and the way hit decoder block should be adapted to the exchanged LRU bit function so as to implement a high performance LRU memory for supporting a multi-port.
In addition, when the access entries are the same, the preferred embodiment of the present invention is implemented such that the modified LRU data is written into the A.sub.-- port, but it may be implemented that the B write word is enabled by the address decoder and the way hit information of the A.sub.-- port and the B.sub.-- port is represented by the modify control signal of the B-port, so that the LRU data can be updated by the B.sub.-- port.
Moreover, in the preferred embodiment of the present invention, the modify control signal is implemented, such that, when the access entries is the same, the B.sub.-- port is first accessed and then the A.sub.-- port is accessed, but it can be implemented such that the access order is changed and the way hit decoder block is simply modified according to the changed access order, so as to provide a high performance LRU memory for supporting a multi-port.
Meanwhile, in the preferred embodiment of the present invention, the LRU memory for supporting 8 entries is illustrated as one example, but the present invention is not limited to this, but can be applicable to the LRU memories for supporting 16 entries, 32 entries, 64 entries, and etc. For such cases, the address decoder block and the LRU SRAM block can be scaled so as to provide a high performance LRU memory for supporting a multi-port.
Also, in the preferred embodiment of the present invention, the LRU memory for supporting a multi-port (that is, A.sub.-- port and B.sub.-- port) is described as one example, the present invention is not limited to this, but is applicable to the LRU memory for supporting a single-port. In such a case, the LRU memory can includes the same structure as that shown in FIG. 10 and can be implemented by much simpler structure for the single port.
The LRU memory according to the preferred embodiment of the present invention, can be applicable to a cache memory using a Pseudo Least Recently Used replacement policy, and it includes the entry access history modify function in itself. Also, it has a write type of decoding function so that it can be suitable to be used for an LRU memory such as a cache memory of high performance superscalar microprocessor, a TLB (Translation Lookaside Buffer), BTB (Branch Target Buffer) and etc.
As described above, the present invention provides an LRU memory for supporting a multi-port, which is needed for operating various blocks, in a high performance microprocessor which adopts a superscalar technique and must use a cache memory, a TLB, a BTB or the like and is implemented by 4-way set associative. This LRU memory receives the way hit information from a cache tag block and analyzes the LRU history so as to provide in itself a write way based on a pseudo LRU replacement policy when the cache memory writes the 4-way. Also, for stably supporting these functions, the LRU memory includes the self time generating block, and reduces the load of control blocks for the cache memory, the TLB block or the BTB block, and makes an interface simple, thereby fast performing the LRU updating process so as to improve the performance of the superscalar microprocessor.
Although preferred embodiments of the present invention has been illustrated and described, various alternatives, modifications and equivalents may be used. Therefore, the foregoing description should not be taken as limiting the scope of the present invention which is defined by the appended claims.
Claims
What is claimed is:
1. An LRU memory capable of performing a pseudo replacement policy, comprising: an address decoding means for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD in response to a first phase of a CLOCK signal and to produce a WRITE.sub.-- WORD in response to a second phase of the CLOCK signal; an LRU storing means for storing a plurality of LRU data, producing an LRU data from a cell corresponding to the READ.sub.-- WORD as a READ.sub.-- DATA, and writing a WRITE.sub.-- DATA to a cell corresponding to the WRITE.sub.-- WORD; a way hit decoding means for decoding a WAY.sub.-- HIT so as to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying means for latching the READ.sub.-- DATA from the LRU storing means to produce a DETECTED DATA and modifying the READ.sub.-- DATA in response to the MODIFY CONTROL signal so as to producing the WRITE.sub.-- DATA to the LRU storing means; and a write way decoding means for analyzing the DETECTED DATA in accordance with the pseudo replacement policy, so as for producing a WRITE.sub.-- WAY.
2. An LRU memory according to claim 1, further comprising a control means for generating a plurality of control signals required for the LRU memory in response to the CLOCK signal, an LRU.sub.-- READ signal used for enabling a read operation for the LRU memory, and an LRU.sub.-- WRITE signal used for enabling a write operation for the LRU memory; and wherein said control means produces: a READ PRECHARGE.sub.-- TIME signal which becomes non-active in response to the first phase of the CLOCK signal and being used for precharging the READ.sub.-- DATA; a READ.sub.-- TIME signal activated when the CLOCK signal is the first phase, the READ PRECHARGE.sub.-- TIME signal is non-active and the LRU.sub.-- READ signal is active, and being used for producing the READ.sub.-- WORD in said address decoding means; a READ LATCH TIME signal which becomes active after an activation of the READ.sub.-- TIME signal and being used in said data modifying means; an LRU MODIFY.sub.-- TIME signal activated in responsive to the second phase of the CLOCK signal and being used for generating the MODIFY CONTROL signal in said way hit decoding means; and a WRITE.sub.-- TIME signal activated when the CLOCK signal is the second phase, the LRU MODIFY.sub.-- TIME signal is active and the LRU.sub.-- WRITE signal is active, and being used for producing the WRITE.sub.-- WORD in said address decoding means.
3. An LRU memory according to claim 2, wherein said control means further produces: a WAY DECODER LATCH.sub.-- TIME signal activated when the CLOCK signal is the second phase, the LRU MODIFY.sub.-- TIME signal is active and the LRU.sub.-- READ signal is active, and being used for producing the WRITE.sub.-- WORD in said write way decoding means.
4. An LRU memory according to claim 3, wherein said control means comprises: a) a first combination logic means for generating the READ PRECHARGE.sub.-- TIME signal including: a first inverter for receiving the CLOCK signal; a first NAND gate having 2 inputs one of which is coupled for receiving an output of the first inverter; and a second and a third inverters coupled in series for receiving an output of said first NAND gate and for producing the READ PRECHARGE.sub.-- TIME signal; b) a second combination logic means for generating the READ.sub.-- TIME signal including: a second NAND gate having 2 inputs one of which is coupled for receiving the clock signal; a fourth and a fifth inverters coupled in series for receiving an output of said second NAND gate, wherein an output of said fifth inverter is applied to the other input of said first NAND gate; and a first NOR gate coupled for receiving the output of the fifth inverter and the LRU.sub.-- READ signal and for producing the READ.sub.-- TIME signal; c) a sixth and a seventh inverters coupled in series for receiving the READ.sub.-- TIME signal so as to produce the READ LATCH.sub.-- TIME signal; d) a third combination logic means for producing the LRU MODIFY.sub.-- TIME signal, including: a eighth inverter for receiving the CLOCK signal; a third NAND gate for receiving an output of the eighth inverter and the output of the fifth inverter; and a ninth, a tenth and an eleventh inverters coupled in series for receiving an output of the third NAND gate, so as to produce the LRU MODIFY.sub.-- TIME signal, wherein an output of said tenth inverter is applied to the other input of said second NAND gate; e) a fourth combination logic means for producing the WAY DECODER LATCH.sub.-- TIME signal, including: a fourth NAND gate for receiving the output of the eighth inverter and the LRU MODIFY.sub.-- TIME signal; and a second NOR gate for receiving the LRU.sub.-- READ signal and an output of said fourth NAND gate so as to produce the WAY DECODER LATCH.sub.-- TIME signal; and f) a third NOR gate for receiving the output of the fourth NAND gate and the LRU.sub.-- WRITE signal so as to produce the WRITE.sub.-- TIME signal.
5. An LRU memory according to claim 1, further comprising a plurality of ports, wherein said INDEX.sub.-- ADDRESS includes a plurality of port INDEX.sub.-- ADDRESS signals each of which relates to one port, respectively; and wherein said address decoding means compares the port INDEX.sub.-- ADDRESS signals with one another, and if all of the port INDEX.sub.-- ADDRESS signals are the same, said address decoding means makes only one WRITE.sub.-- WORD related to one port activated.
6. An LRU memory according to claim 1, further comprising a plurality of ports; wherein said INDEX.sub.-- ADDRESS includes a plurality of port INDEX.sub.-- ADDRESS signals each of which relates to one port; and wherein said address decoding means produces a COMPARE.sub.-- HIT signal activated when the plurality of said port INDEX.sub.-- ADDRESS signals are the same with each other, to provide the COMPARE.sub.-- HIT signal to said way hit decoding means.
7. An LRU memory according to claim 6, wherein the number of ports is 2 and the INDEX.sub.-- ADDRESS includes a first port INDEX.sub.-- ADDRESS signal and a second port INDEX.sub.-- ADDRESS signal each of which is composed of N-bits; and wherein said address decoding means comprises: a first latch means including N latches for latching the first port INDEX.sub.-- ADDRESS signal; a second latch means including N latches for latching the second port INDEX.sub.-- ADDRESS signal; a comparing means for comparing an output of said first latch means with an output of said second latch means, so as to produce the COMPARE.sub.-- HIT signal; a first READ.sub.-- WORD generating means for decoding the output of said first latch means when the READ.sub.-- TIME signal is active, so as to produce a first port READ.sub.-- WORD; a first WRITE.sub.-- WORD generating means for decoding the output of said first latch means when the WRITE.sub.-- TIME signal is active, so as to produce a first port WRITE.sub.-- WORD; a second READ.sub.-- WORD generating means for decoding the output of said second latch means when the READ.sub.-- TIME signal is active, so as to produce a second port READ.sub.-- WORD; and a second WRITE.sub.-- WORD generating means for decoding the output of said second latch means when the WRITE.sub.-- TIME signal is active, so as to produce a second port WRITE.sub.-- WORD.
8. An LRU memory according to claim 7, wherein said N is 3 and said first latch means and said second latch means comprise 3 latches, respectively.
9. An LRU memory according to claim 8, wherein said first READ.sub.-- WORD generating means comprises: three inverters each of which is coupled for receiving one bit of the output of said first latch means; eight NAND gates each of which selectively receives the output of said first latch means and outputs of said three inverters; and eight NOR gates each of which is coupled for receiving the READ.sub.-- TIME signal and an output of said corresponding NAND gate, so as to produce a corresponding bit of the first port READ.sub.-- WORD.
10. An LRU memory according to claim 8, wherein said first WRITE.sub.-- WORD generating means comprises: three inverters each of which is coupled for receiving one bit of the output of said first latch means; eight NAND gates each of which selectively receives the output of said first latch means and outputs of said three inverters; and eight NOR gates each of which is coupled for receiving the WRITE.sub.-- TIME signal and an output of said corresponding NAND gate, so as to produce a corresponding bit of the first port WRITE.sub.-- WORD.
11. An LRU memory according to claim 8, wherein said second READ.sub.-- WORD generating means comprises: three inverters each of which is coupled for receiving one bit of the output of said second latch means; eight NAND gates each of which selectively receives the output of said second latch and outputs of said three inverters; and eight NOR gates each of which is coupled for receiving the READ.sub.-- TIME signal and an output of said corresponding NAND gate, so as to produce a corresponding bit of the second port READ.sub.-- WORD.
12. An LRU memory according to claim 8, wherein said second WRITE.sub.-- WORD generating means comprises: three inverters each of which is coupled for receiving one bit of the output of said second latch means; eight NAND gates each of which selectively receives the output of said second latch means and outputs of said three inverters; and eight NOR gates each of which is coupled for receiving the WRITE.sub.-- TIME signal and an output of said corresponding NAND gate, so as to produce a corresponding bit of the second port WRITE.sub.-- WORD.
13. An LRU memory according to claim 2, wherein the number of ports is 2; the WRITE.sub.-- WORD includes a first port WRITE.sub.-- WORD and a second port WRITE.sub.-- WORD; the WRITE.sub.-- DATA includes a first port WRITE.sub.-- DATA and a second port WRITE.sub.-- DATA; the READ.sub.-- WORD includes a first port READ.sub.-- WORD and a second port READ.sub.-- WORD; the READ.sub.-- DATA includes a first port READ.sub.-- DATA and a second port READ.sub.-- DATA; wherein said LRU storing means comprises a number of unit memory cells each of which includes: a first transistor being turned on in response to the first port WRITE.sub.-- WORD so as to transfer the first port WRITE.sub.-- DATA; a first inverter for receiving an output of said first transistor; a second transistor being turned on in response to the second port WRITE.sub.-- WORD so as to transfer the second port WRITE.sub.-- DATA; a second inverter for receiving an output of said second transistor; a third transistor being turned on in response to an output of the first inverter and its source being coupled to a ground; a fourth transistor whose drain is coupled to a drain of said third transistor and whose gate is coupled for receiving the first port READ.sub.-- WORD signal, so as to produce the first port READ.sub.-- DATA through its source; a fifth transistor being turned on in response to an output of the second inverter and its source being coupled to a ground; and a sixth transistor whose drain is coupled to a drain of said fifth transistor and whose gate is coupled for receiving the second port READ.sub.-- WORD signal, so as to produce the second port READ.sub.-- DATA through its source.
14. An LRU memory according to claim 7, wherein said way hit decoding means comprises: a first combination logic means including a plurality of inverters each of which is coupled for receiving a corresponding bit of a first port WAY.sub.-- HIT signal; a second combination logic means including a plurality of NAND gates each of which is coupled for receiving a corresponding output of said first combination logic means and an inverted COMPARE.sub.-- HIT signal; a third combination logic means including a plurality of NAND gates each of which is coupled for receiving one bit of a second port WAY.sub.-- HIT signal and one output of said first combination logic means; a fourth combination logic means including a plurality of NAND gates each of which is coupled for receiving a corresponding output of said third combination logic means and a corresponding output of said first combination logic means; a fifth combination logic means including a plurality of OR gates each of which is coupled for receiving one bit of an output of said fourth combination logic means and the inverted COMPARE.sub.-- HIT signal; a sixth combination logic means including a plurality of 3-input NAND gates each of which is coupled for receiving one bit of an output of said second combination logic means, one bit of an output of said fifth combination logic means, and the LRU MODIFY.sub.-- TIME signal; a seventh combination logic means including a plurality of 2-input NAND gates each of which receives any two bits of an output of said sixth combination logic means; an eighth combination logic means including a plurality of inverters each of which is coupled for receiving one bit of the output of said sixth combination logic means, said seventh and said eighth combination logic means producing a first port CLEAR signal and a first port SET signal; a ninth combination logic means including a plurality of 2-input NAND gates each of which is coupled for receiving one bit of the second port WAY.sub.-- HIT signal and the LRU MODIFY.sub.-- TIME signal; a tenth combination logic means including a plurality of 2-input NAND gates each of which receives any two bits of an output of said ninth combination logic means; and a eleventh combination logic means including a plurality of inverters each of which is coupled for receiving one bit of the output of said ninth combination logic means, said tenth and said eleventh combination logic means producing a second port CLEAR signal and a second port SET signal.
15. An LRU memory according to claim 2, wherein said data modifying means comprises: a first transistor whose gate is applied with the READ PRECHARGE.sub.-- TIME signal, whose drain is applied with a power supply voltage and whose source is applied with a first port READ.sub.-- DATA signal; a second transistor whose gate is applied with the READ PRECHARGE.sub.-- TIME signal, whose drain is applied with the power supply voltage and whose source is applied with a second port READ.sub.-- DATA; a first and a second inverters coupled in series for receiving the first port READ.sub.-- DATA signal; a third and a fourth inverters coupled in series for receiving the second port READ.sub.-- DATA signal; a first latch means for latching an output of said second inverter in synchronization with the READ LATCH.sub.-- TIME signal so as to produce the DETECTED DATA; a second latch means for storing the first port READ.sub.-- DATA signal in response to the READ LATCH.sub.-- TIME signal, for setting a stored signal therein in response to a first port SET signal, and for clearing the stored signal in response to a first port CLEAR signal; and a third latch means for storing the second port READ.sub.-- DATA signal in response to the READ LATCH.sub.-- TIME signal, for setting a stored signal therein in response to a second port SET signal, and for clearing the stored signal in response to a second port CLEAR signal, said first port SET signal, said second port SET signal, said first port CLEAR signal and said second port CLEAR signal being included in the MODIFY CONTROL signal.
16. An LRU memory according to claim 15, wherein each of said second latch means and said third latch means, comprises: a first transfer gate for transferring the corresponding output of said second inverter or said fourth inverter in response to the READ LATCH.sub.-- TIME signal; a fifth inverter coupled for receiving an output of said first transfer gate; a sixth inverter coupled for receiving an output of said fifth inverter and whose output is coupled to the output of said first transfer gate; a seventh inverter coupled for receiving the output of said fifth inverter for producing the corresponding port WRITE.sub.-- DATA signal; a third transistor being gated by the corresponding port CLEAR signal and whose drain-source path is coupled between the output of said first transfer gate and the ground; and a fourth transistor being gated by the corresponding port SET signal and whose drain-source path is coupled between the output of said fifth inverter and the ground.
17. An LRU memory according to claim 2, wherein said write way decoding means comprises: a first, a second and a third inverters each of which is coupled for receiving a corresponding bit of the DETECTED DATA; a fourth, a fifth and a sixth inverters each of which is coupled for receiving a corresponding output of said first, said second and said third inverters, respectively; a first 2-input NAND gate coupled for receiving outputs of said fourth inverter and said fifth inverter; a second 2-input NAND gate coupled for receiving outputs of said first inverter and said fifth inverter; a third 2-input NAND gate coupled for receiving outputs of said second inverter and said sixth inverter; a fourth 2-input NAND gate coupled for receiving outputs of said second inverter and said third inverter; and four latches for latching a corresponding output of said first, said second, said third and said fourth NAND gates, in response to the WAY DECODER LATCH.sub.-- TIME signal, so as to produce the WRITE.sub.-- WAY.
18. An LRU memory according to claim 17, wherein said write way decoding means determines the least recently used way as the WRITE.sub.-- WAY.
19. An LRU memory according to claim 1, wherein said write way decoding means determines the least recently used way as the WRITE.sub.-- WAY.
20. An LRU memory according to claim 1, wherein said LRU memory supports a single port.
Patent Citations (5)
Non-Patent Literature (1)
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