Method of Testing Multi-Core Processors and Multi-Core Processor Testing Device

The present invention relates generally to testing integrated circuits and more particularly to testing multi-core processors.

Many current testing methods are used for integrated circuits with many microprocessor cores. In one technique, a single test is performed on each of the many (N) microprocessor cores at the same time and the test result is read from N output pin sets. In another conventional method, a single output pin set is used, but the test is repeated N times. It would be desirable to test the integrated circuit with multiple processor cores using a single test and using a single output pin set since a premium is placed on reducing the number of pin sets and reducing testing time.

Accordingly, there is a need for an improved method and device for testing multi-core processor integrated circuits.

While the invention is pointed out with particularity in the appended claims, other features of the invention are disclosed by the following detailed description and the accompanying drawings, in which:

FIG. 1 is a block diagram of an embodiment of a system that uses a multi-core processor testing device in accordance with the present invention.

FIG. 2 is a block diagram of the multi-core processor testing device of FIG. 1.

FIG. 3 is a flow chart illustrating operation of the multi-core processor testing device of FIG. 2.

Generally, the present invention relates to a method of testing a multi-core processor and to a multi-core processor testing device. In accordance with a particular embodiment, the method includes the steps of receiving a plurality of input signals from a plurality of processor cores and producing an output signal corresponding to a disable state when at least two of the plurality of input signals represent a different logic value.

In accordance with another aspect of the present invention, the method includes the steps of receiving a plurality of input signals from a plurality of processor cores and producing an output signal that corresponds to one of a first and second state when each of the plurality of input signals represent the same digital logic value and corresponds to a third state when at least two of the plurality of signals represent different logic values.

In accordance with another aspect of the present invention, the multi-core processor testing device includes a multiplexer responsive to a plurality of input signals from a plurality of processor cores and an output driver responsive to the multiplexer. The output driver produces an output signal that corresponds to a disable state when at least two of the plurality of signals represent different logic values.

It should be noted that the particular terms and expressions employed and the particular structural and operational details disclosed in the detailed description and accompanying drawings are for illustrative purposes only and are not intended to in any way limit the scope of the invention as described in the appended claims.

Referring to FIG. 1, an embodiment of a system 10 that uses a testing device 12 is disclosed. The system 10 includes a plurality of microprocessor cores 14, 16, 18, and 20 to be tested by the testing device 12. The testing device 12 receives a core selection 22 and a plurality of input signals 24, 26, 28 and 30 from the plurality of processor cores 14, 16, 18 and 20. The testing device 12 produces a test result output 32 that is to be compared with an expected logic value using an external tester 70 to determine a testing result 76. While the particular exemplary embodiment of FIG. 1 illustrates four processor cores, it is to be understood that the present invention is applicable to testing a plurality of processor cores .

Referring to FIG. 2, an embodiment of the testing device 12 is disclosed. The testing device 12 includes a multiplexer 40, a first selector 42, a second selector 44, digital comparison and masking logic 46, and an output driver 48. The multiplexer 40 receives the plurality of input signals 24, 26, 28 and 30 from the plurality of processor cores 14-20 and produces a multiplexed output 50. The first selector 42 receives the multiplexed output 50 and feeds either the multiplexed output 50 or functional data 52 to the input 54 of the driver 48. The output driver 48 has an enable/disable input 56 that receives an output of the second selector 44. The second selector 44 receives a functional enable signal 58 and receives a comparison logic output 60 from comparison and masking logic module 46. The comparison and masking logic module 60 includes masking digital logic to mask out any processor cores that are de-selected for testing by the masking control input lines 64. An example of the illustrative masking logic is disclosed in FIG. 2.

In a particular illustrative embodiment, the output driver 48 is a Motorola/Somerset model xb.sub.13 ocd driver from the Hip4 cell library. The multiplexer 40 and the selectors 42, 44 are ots.sub.13 1112.sub.-- mux4 model multiplexers from the Motorola/Somerset Hip4 custom cell library. The processor cores 14, 16, 18 and 20 may be PowerPC.RTM. 750 type of processors available from Motorola. The input signals 24, 26, 28 and 30 may be signal sets generated by the processor cores 14, 16, 18 and 20. The above described specific components are only to provide a specific example configuration and are not intended to in any way limit the scope of the present invention. Those skilled in the art will appreciate that many other types of components may be used.

During operation, the output driver 48 may operate in a non-test mode or in a testing mode. In the non-test mode, the driver 48 is enabled by the second selector 44 passing the functional enable signal 58. In this mode, the driver 48 passes on functional data 52 input to the first selector 42. In this non-test mode, the operation of the testing device 12 is essentially transparent to the system 10.

In the test mode, the output driver 48 receives input from the multiplexed output 50 of the multiplexer 40. In addition, the output driver 48 receives the comparison logic output 60 from the comparison and masking logic module 46 at its enable/disable input 56. The logic in the comparison and masking logic module 46 is configured such that the output driver 48 produces an output signal 62 that is a logical zero when all of the input signals 24, 26, 28 and 30 from the processor cores 14, 16, 18 and 20 are also at a logical zero value and produces a logical one when all of the input signals 24, 26, 28 and 30 are at a logical one value. However, when at least two of the input signals have different values, then the output driver 48 is disabled by the comparison logic output 60 being applied to the disable input 56 of the output driver 48. In this case, the output driver 48 produces an output signal 62 that corresponds to a disable state, such as a z-state signal. The z-state signal has a detectable impedance that differs from either the digital logic zero or digital logic one values. The output signal 62 is then available for comparison with an expected test value 74 by an external testing device 70. The external testing device 70 includes a comparator 72 to compare the output signal 62 with the expected test value to produce a test result signal 76.

Referring to FIG. 3, a flow chart of a method of testing a multi-core processor is disclosed. A plurality of input signals from a plurality of processor cores is received, at step 100. A comparison is performed on the input signals, at step 102. If all of the input signals have the same logic value, then that logic value is output, at step 104. If all of the input signals do not have the same logic value, then a disable state value is output, at state 106. Next, an expected test output is compared to the output signal, at step 108, and a test result is determined, at step 110. Typically, the test result is either a pass or a fail indication. In a particular testing method, a pass is indicated when the expected testing output either matches the output signal (e.g. expect a logic zero and receive a logic zero) or when the expected testing output is a don't care state. For example, when a don't care state is the expected testing output, either a logic zero, a logic one, or a disable output (e.g. z-state) will result in a test pass. When either a logic zero or a logic one is the expected testing output, then the test result will be a failed test if the output signal is the disable state.

After the testing result is produced and preferably recorded, a comparison is made to determine if testing is completed, at step 112. If testing is completed, then processing stops at step 114. Otherwise, the testing method is repeated for the next test, at step 100.

By testing multiple processor cores at the same time using a single output from the output driver 48, testing time is beneficially reduced. In addition, since the output driver 48 may be routed to a single output pin set, the number of pins at the testing output is also beneficially reduced. In this manner, the above embodiment has provided an improved method and device for testing multi-core processor integrated circuits. More specifically, the above described method and testing device beneficially allows testing of an integrated circuit with multiple cores using a single test and using a single output pin set.

Thus, there has been described herein at least one embodiment including at least one preferred embodiment of a method and device for testing multi-core processors. It will be apparent to those skilled in the art that the disclosed subject matter may be modified in numerous ways and may assume many embodiments other than the preferred form specifically set out and described above.

Accordingly, the above disclosed subject matter is to be considered illustrative and not restrictive, and to the maximum extent allowed by law, it is intended by the appended claims to cover all such modifications and other embodiments which fall within the true spirit and scope of the present invention. The scope of the invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents rather than the foregoing detailed description.