Temperature Compensated Current and Voltage Reference Circuit

The invention relates to a reference circuit, such as a reference circuit that provides a reference voltage and/or a reference current, for example.

Quite often a circuit may use a reference voltage that is different from available power supply voltage(s). As a result, the circuit may be coupled to another circuit, called a voltage reference circuit, that converts one or more of the available power supply voltage(s) into the desired reference voltage. For example, referring to FIG. 1, a voltage reference circuit 4 may include a resistor divider that is formed from resistors 1 and 2 that are serially coupled together between a positive power supply voltage (called V.sub.DD) and a negative power supply voltage (called V.sub.SS). In this manner, an output terminal 3, formed from the union of the two resistors 1 and 2, may provide a reference voltage (called V.sub.REF) that has a voltage level somewhere between the V.sub.DD and V.sub.SS power supply voltages.

Assuming that a load that is coupled to the output terminal 3 sinks/sources negligible current, certain circuit applications may benefit from using the voltage reference circuit 4. For example, it may be desirable for the V.sub.REF reference voltage to vary proportionately with changes in the levels of the V.sub.DD and V.sub.SS supply voltages, a feature that is inherent in the resistor divider topology of the voltage reference circuit 4. Furthermore, the resistor divider topology of the voltage reference circuit 4 permits the level of the V.sub.REF reference voltage to be substantially low, such as a voltage level in the range of approximately 0.2 to 0.9 volts, for example. The V.sub.REF reference voltage may also vary little with a temperature of the voltage reference circuit 4 because a temperature-induced change in the resistance of the resistor 1, 2 is matched by a proportionate change in the resistance of the other resistor 1, 2.

Unfortunately, the resistors 1 and 2 may dissipate excessive power, and as a result, a voltage reference circuit having a different topology may be used. For example, a bandgap voltage reference circuit (not shown) typically dissipates less power. The bandgap voltage reference circuit typically includes one or more p-n junctions that are connected in a manner to provide a reference voltage that varies little with temperature. However, unfortunately, the reference voltage that is provided by the bandgap voltage reference circuit may not vary with the supply voltage(s), the bandgap voltage reference circuit may not produce low reference voltages (e.g., voltages from 0.2 to 0.8 volts), and non-ideal characteristics of the p-n junctions may affect the circuit's performance.

Thus, there is a continuing need for a reference circuit that addresses one or more of the above-stated problems.

In one embodiment, a reference circuit includes a first resistive element and a current source. The first resistive element is adapted to produce an output voltage based on a first current and a resistance of the first resistive element. The resistance of the first resistive element is a function of a temperature of the reference circuit. The current source includes a second resistive element that has a resistance that is a function of the temperature. The current source is adapted to adjust the first current to minimize variation of the output voltage with the temperature based on the resistance of the second resistive element.

In another embodiment, a method includes routing a first current through a first resistive element to produce an output voltage and changing a resistance of the first resistive element in response to a change in temperature. The resistance of a second resistive element is changed in response to the change in temperature. The change in resistance of the second resistive element is used to regulate the first current to substantially prevent the output voltage from changing when the temperature changes.

FIG. 1 is a schematic diagram of a voltage reference circuit of the prior art

FIG. 2 is a schematic diagram of a reference circuit according to an embodiment of the invention.

FIGS. 3 and 4 are more detailed schematic diagrams of the reference circuit of FIG. 2 according to different embodiments of the invention.

Referring to FIG. 2, an embodiment 20 of a reference circuit in accordance with the invention includes a resistive element 8 (a resistor 24, for example) that furnishes a reference voltage (called V.sub.REF) at an output node 9 of the circuit 20. The V.sub.REF reference voltage may be used by another circuit 10, such as a voltage converter, a comparator or an analog-to-digital converter (ADC), as just a few examples. In this manner, the circuit 10 uses a reference voltage that is different from the available power supply voltages. To cause the resistive element 8 to furnish the V.sub.REF reference voltage, the reference circuit 20 includes a temperature compensating current source 6 that produces a current (called I.sub.OUT) in the resistive element 8. As described below, in some embodiments, the current source 6 compensates the I.sub.OUT current in a manner that minimizes fluctuations in the level of the V.sub.REF reference voltage due to a change in temperature of the reference circuit 20. Furthermore, in some embodiments, the current source 6 may compensate for a change in power supply voltages (a positive power supply voltage called V.sub.DD and a negative power supply voltage called V.sub.SS (ground, for example), as examples) by proportionally changing the level of the VREF reference voltage. As described below, the reference circuit 20 may accomplish these features while dissipating substantially less power than a conventional resistor divider, for example.

More particularly, when the temperature of the reference circuit 20 changes, the resistance of the resistive element 8 may also change. For example, for embodiments where the resistive element 8 includes a resistor 24, the resistance of the resistor 24 may vary directly with the temperature. Therefore, when the temperature of the reference circuit 20 increases, the resistance of the resistor 24 also increases, a condition that might otherwise increase the V.sub.REF reference voltage if not for the current compensation (described below) that is introduced by the current source 6. Similarly, for a decrease in temperature, the resistance of the resistor 24 may decrease, a condition that might otherwise decrease the V.sub.REF reference voltage if not for the current compensation that is introduced by the current source 6, described below.

In some embodiments, to compensate the I.sub.OUT current, the current source 6 bases the level of the I.sub.OUT current on the resistance of a resistive element 7, such as a resistor 22, for example. For example, in some embodiments, the current source 6 may decrease the level of the I.sub.OUT current proportionately to the increase in resistance of the resistor 22 and increase the level of the I.sub.OUT current proportionately to the decrease in resistance of the resistor 22. In this manner, the level of the I.sub.OUT current may vary inversely with the resistance of the resistive element 7, and thus, the level of the I.sub.OUT current may vary inversely with the temperature. Therefore, the I.sub.OUT current tends to decrease the level of the V.sub.REF reference voltage in response to a temperature increase and tends to increase the V.sub.REF reference voltage in response to a temperature decrease. Because the level of the V.sub.REF voltage may be approximately proportional to the level I.sub.OUT current (that tends to vary inversely with the temperature) and may be approximately proportional to the resistance of the resistive element 8 (that tends to vary directly with the temperature), the above-described arrangement may substantially prevent variation of the V.sub.REF reference voltage due to changes in temperature.

Because the V.sub.REF reference voltage may be formed via a resistive element 8, the above-described arrangement may be used to furnish low voltage level that is close to the V.sub.DD or the V.sub.SS power supply voltage. For example, for the case where the V.sub.SS power supply is approximately ground, the level of the V.sub.REF reference voltage may be in the range of approximately 0.2 to 0.8 volts, as an example. Other voltage levels for the V.sub.REF reference voltage are possible.

If a bandgap reference circuit is available in the system and a subband gap voltage is needed, the bandgap reference circuit may be used to generate the V.sub.DD positive power supply voltage.

FIG. 3 depicts a more detailed schematic diagram of the reference circuit 20 in accordance with an embodiment of the invention in which the resistive elements 7 and 8 include resistors 22 and 24, respectively. In particular, the current source 6 may include a current mirror 28, the resistor 22 and an amplifier 26 that electrically interact with each other to regulate the level of the I.sub.OUT current, as described below. In this manner, via its input terminals, the amplifier 26 may compare the V.sub.REF reference voltage to a voltage of a node 21 that may be set by the voltage drop across the resistor 22. Based on this comparison, the amplifier 26 may regulate an n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) 30 (of the current mirror 28) to control the level of a current (called I.sub.1) in the resistor 22 and thus, the voltage of the node 21. If the amplifier 26 has a sufficiently high gain, then the voltage of the node 21 is approximately equal to the VREF reference voltage for steady state conditions. It is assumed for purposes of simplifying the discussion of the voltage reference circuit 20 that the input terminals of the amplifier 26 conduct negligible current.

The resistor 22 may be coupled between the V.sub.DD positive power supply voltage and the node 21, i.e., two relatively constant voltage levels. As a result of this arrangement, the I.sub.1 current varies inversely with the temperature, as the resistance of the resistor 22 varies directly with the temperature.

The current mirror 28 produces the I.sub.OUT current by scaling and mirroring the I.sub.1 current. To accomplish this, the gate of the transistor 30 may be coupled to the gate of another nMOSFET transistor 38. Because the sources of the transistors 30 and 38 are coupled to the V.sub.SS negative power supply voltage, the gate-source voltages of the two transistors 30 and 38 are approximately the same. Therefore, a resultant current (called I.sub.2) in the drain-source path of the transistor 38 may mirror the I.sub.1 current. The I.sub.2 current flows through the source-drain path of a p-channel metal-oxide semiconductor field-effect-transistor (pMOSFET) 34, and in some embodiments, the aspect ratio (i.e., the width-to-length (W/L) ratio of the channel) of a mirroring pMOSFET 36 may be larger than the aspect ratio of the transistor 34 to introduce a current gain that may be described by the following equation:

where I.sub.REF is the current in the source-drain path of the transistor 36, "K" is a ratio of the aspect ratio of the transistor 36 to the aspect ratio of the transistor 34. In some embodiments, K may be greater than one.

In some embodiments, the transistor 34 may have its source-drain path coupled in series with the drain-source path of the transistor 38. The gates of the transistors 32, 34 and 36 are coupled together, and the sources of the transistors 32, 34 and 36 are coupled to the V.sub.DD positive power supply voltage. The drain-source path of the transistor 32 produces the I.sub.OUT current (assuming input terminal of the amplifier 26 sinks/sources negligible current). Therefore, as a result of this arrangement, the I.sub.OUT current mirrors the I.sub.2 current and thus, mirrors the I.sub.1 current. The aspect ratios of the transistors 32 and 34 may be adjusted to further scale the I.sub.OUT current with respect to the I.sub.1 current.

In some embodiments, the I.sub.OUT current has a substantially higher magnitude than the I.sub.1 current, a relationship that permits the I.sub. current to be small and thus, cause the resistor 22 to dissipate very little power. As a result, the voltage reference circuit 20 may use two resistors 22 and 24 to establish the V.sub.REF reference voltage while dissipating substantially less power than a resistor divider topology, for example, that also uses two resistors. However, similar in result to the resistor divider topology, the voltage reference circuit 20 may scale the V.sub.REF reference voltage in accordance with a change in the V.sub.DD and/or V.sub.SS power supply voltages as described by the following equation: ##EQU1## where "R.sub.22 " represents the resistance of the resistor 22, and "R.sub.24 " represents the resistance of the resistor 24 and "K.sub.TOT " represents the total current gain that is applied to the I.sub.1 current by the current mirror 28.

Among the other features of the reference circuit 20, the output terminal of the amplifier 26 may be coupled to the gates of the transistors 30 and 38 to regulate the I.sub.1, I.sub.2 and I.sub.OUT currents. The positive input terminal of the amplifier 26 may be coupled to the node 21, and the negative input terminal of the amplifier 26 may be coupled to the output node 9. A capacitor 27 may have one terminal that is coupled to the output terminal of the amplifier 26 and to the gates of the transistors 30 and 38 and another terminal that receives the V.sub.SS negative power supply voltage. The capacitor 27 effectively serves as a voltage source to stabilize the level of the V.sub.REF reference voltage loop during transient load conditions, for example.

Other embodiments are within the scope of the following claims. For example, referring to FIG. 4, in some embodiments, the voltage reference circuit 20 may be replaced by a voltage reference circuit 40. The voltage reference circuit 40 may be similar in design to the voltage reference circuit 20 except that the resistive elements 7 and 8 may include a pMOSFET transistor 42 and an nMOSFET transistor 44, respectively, that replace the resistors 22 and 24. In this manner, the transistor 42, 44 may be configured as an active load in which the gate of the transistor 42, 44 is coupled to the drain of the transistor 42, 44. Thus, the source-drain path of the transistor 42 is coupled between the V.sub.DD positive supply voltage and the node 21; and the drain-source path of the transistor 44 is coupled between the output node 9 and the V.sub.DD negative power supply voltage. In some embodiments, the transistor 44 may be replaced by a pMOSFET that has its gate coupled to the V.sub.SS negative power supply voltage.

While the invention has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the invention.