Television Signal Data Transmission System

The present invention relates to the field of high-speed data transmission, and more particularly, to a system for providing high-speed data transmission using a television signal.

There has been a failure in the field of data transmission systems to recognize the potential of a television signal, and in particular, the large bandwidth available using a television signal. At present, methods of encoding data into a television signal have been restricted to relatively low bandwidth and inefficient use of the television signal medium. The reason for this appears to be that the data encoding methods in use were designed more than twenty-five years ago, and the bandwidth required for the original purpose is relatively low. For instance, these methods were designed to allow a television signal to carry closed-captioning and/or teletext information. The data rate needed for carrying this information is extremely low, and though the bit rate of the data transmission was fairly high (e.g., 4.5 million bits per second in bursts), the overall bandwidth utilization of the television signal generally does not exceed 45,000 bits per second, Moreover, the data encoding methods used for captioning and teletext are fairly rudimentary. In this regard, these methods divide a signal line of a television picture up into a number of time slices, and then impress digital information into the slots as a series of black or white spots, representing the digital values of zero and one. The data bytes are encoded into changing voltages (i.e., black and white spots), and decoded back into bytes by using a commonly available electronic device, such as UART (Universal Asynchronous Receiver Transmitter) or an ACIA (Asynchronous Communications Interface Adapter). One limitation of this "binary coding" scheme is that it limits the data transmission rate. In order to achieve greater transmission rates, data has been encoded into complex waveforms, such as tones, which are then phase, frequency, and amplitude modulated in order to carry the information. For instance, this method is used in data modems for use in longer distance high-speed communications. Other forms of encoding for high-speed data transmission include RF (Radio Frequency) modulation, networks such as Ethernet or Arcnet, QAM (Quadrature Amplitude Modulation), ASK (Amplitude Shift Keying), PSK (Phase Shift Keying), FSK (Frequency Shift Keying), TCM (Trellis Coded Modulation) and QPSK (Quadrature Phase Shift Keying). All of the foregoing methods encode data on to waveforms for transmission, which is the next step beyond raw digital data.

In order to derive further benefits from the use of the television signal as a transmission medium, it would be advantageous to encode multiple data bits in parallel as discreet levels into the television image.

The "information highway" of the future relies on high-speed data transmission to distribute image, sound and video to multiple access points worldwide. Currently, the distribution bottleneck is the data rate (defined in bits per second) capabilities of the communications medium in use. For example, one minute of compressed digital video data may be represented by approximately ten megabytes of data. Currently available communications mediums include voice grade modems, leased line modems, ISDN services, fiber-optic or high-speed land-line links, radio modems and satellite data links.

Prior art approaches to achieving higher data transmission rates have typically involved trying to compress the data or to pack more bits per basic transmission unit (baud) within the same channel bandwidth. For example, a 9.6 Kbps modem for use on standard two-wire telephone lines operates within the 3 Khz bandwidth available. To reach 9.6 Kbps, it may use a basic baud rate of 2400 baud, and encode 4 bits per baud. The "baud" defines a number of transitions made on the base carrier each second, and the number of bits per baud multiplied by the baud rate provides a number of bits per second (bps).

Another aspect of the present invention is directed to the encoding of digital data. Prior art data encoding methods for encoding digital information have used two voltage levels, where each voltage level represents a single bit. In this respect, a first voltage level represents a digital value "0," while a second voltage level represents a digital value "1." As a result, a set of eight of these voltage levels is needed to encode one byte of digital data. Data bytes are encoded into changing voltages and decoded back into bytes. This is typically done by using a UART or an ACIA. UARTs convert parallel data (usually eight-bit words) to a serial data stream for transmission over a single wire cable and likewise convert a received serial bit stream to parallel words. The serial data stream is comprised of a signal having two voltage levels, one representing a digital "0," the other representing a digital "1."

In many cases, the data rate achievable by UARTs and ACIAs is insufficient for the desired application. In order to achieve greater data rates for high-speed communications, data has been encoded into complex waveforms such as tones, which are then phase, frequency and amplitude modulated. As mentioned above, data has been encoded using RF, QAM, ASK, PSK, FSK, TCM and QPSK. All of the foregoing methods encode data into AC waveforms for transmission.

The present invention provides a novel system for transmitting and receiving digital data using a conventional television signal for data transfer. In a preferred embodiment of the present invention an encoding system is used which overcomes the data transfer rate limitations of the prior art encoding systems, and provides a system for encoding multiple data bits in parallel as transitions between discrete levels.

In accordance with a preferred embodiment of the present invention, there is provided a television signal data transmission system having a transmitter for encoding digital data and a mock television signal, and a receiver for decoding the encoded digital data and the mock television signal.

It is an object of the present invention to provide a data transmission system which uses a conventional television signal to transmit encoded digital data at very high data transmission rates.

It is another object of the present invention to provide a data transmission system which encodes mock television signals to comply with government standards for regular broadcast television signals.

It is another object of the present invention to provide a data transmission system which uses a multi-level encoding system to further increase the data transmission rate.

It is another object of the present invention to provide a data transmission system which uses a television signal as a high-speed data transmission medium.

It is still another object of the present invention to provide a data transmission system which uses the active video portion of the television signal to transmit data.

It is still another object of the present invention to provide a data transmission system which significantly reduces the data transmission time and cost.

It is yet another object of the present invention to provide a data transmission system which uses standard, readily available television transmission and receiving devices.

It is yet another object of the present invention to provide a data transmission system which provides greater bandwidth at lower cost.

These and other objects will become apparent from the following description of a preferred embodiment taken together with the accompanying drawings and appended claims.

The above-mentioned and other features and objects of the invention and the manner of attaining them will become more apparent and the invention will be best understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings and appended claims, wherein:

FIG. 1 is a state diagram for encoding two different input values into three output levels, according to a preferred embodiment of the present invention;

FIG. 2 is a state diagram for encoding three different input values into four output levels, according to a preferred embodiment of the present invention;

FIG. 3 is a state diagram for encoding four different input values into five output levels, according to a preferred embodiment of the present invention;

FIG. 4 is a timing diagram illustrating the encoding of four different input values according to the state diagram shown in FIG. 3;

FIG. 5 is a flow chart illustrating a preferred embodiment of the algorithm for encoding the input values according to the state diagram shown in FIG. 3;

FIG. 6 is a flow chart illustrating a preferred embodiment of the algorithm for decoding output levels into input values;

FIG. 7 is a timing diagram illustrating the encoding of four different input values;

FIG. 8 is a block diagram of the hardware arrangement for implementing the encoding algorithm of the present invention;

FIG. 9 is a block diagram of the hardware arrangement for implementing the decoding algorithm of the present invention;

FIG. 10 is a horizontal timing pictorial for an NTSC compatible television signal;

FIG. 11 is a vertical timing pictorial for an NTSC compatible television signal;

FIG. 12 is a block diagram of the television signal data transmission system, according to a preferred embodiment of the present invention;

FIG. 13 is an NTSC television signal waveform for a black and white television transmission;

FIG. 14A is a table showing the states of the encoder state machine and corresponding outputs of the encoder;

FIG. 14B is a timing diagram showing the digital encoded data for the first four phases of an NTSC signal and the first two scan lines of the active video phase;

FIG. 14C is a timing diagram showing the digital encoded data for the first scan line shown in FIG. 14B;

FIG. 14D is a timing diagram showing the digital encoded data for a portion of the first scan line shown in FIG. 14C;

FIGS. 15A and 15B provide a diagram illustrating the control unit logic for encoding data;

FIGS. 16A and 16B provide a diagram illustrating the control unit logic for decoding data;

FIG. 17 is a table showing the outputs of the decoder state machine and corresponding inputs;

FIG. 18 is a table showing the outputs for various signal generated by the control unit logic for decoding data; and

FIG. 19 is a timing diagram showing the outputs of the decoder.

In a preferred embodiment of the present invention, a novel system for encoding N input values into at least N+1 output levels is used. This novel encoding system is described in detail below. However, it should be appreciated that other suitable encoding systems may be used with the present invention to yield similar results In a preferred embodiment of the novel encoding system each output level is represented by a different voltage. However, each output level may also be represented by a different frequency, phase, or amplitude. Referring now to the drawings wherein the showings are for the purpose of illustrating a preferred embodiment of the invention only, and not for the purpose of limiting same, FIG. 1 shows a state diagram 20 illustrating the transition between states for encoding two different input values (i.e., "0" and "1") into three output levels (i.e., output levels A, B and C), according to a preferred embodiment of the present invention. For instance, beginning at state 22 (output level A), if the next input value is a "0," the system transitions to state 24 (output level B). In contrast, if the next input value is a "1," the system transitions to state 26 (output level C). The system will transition from one state to one of the other two remaining states as each consecutive input value is encoded. Importantly, it should be noted that no two consecutive input values will be encoded as the same output level.

FIG. 2 shows a state diagram 30 illustrating the transition between states for encoding three input values (i.e., "0," "1" and "2") into four output levels (i.e., output levels A, B, C and D), according to a preferred embodiment of the present invention.

FIG. 3 shows a state diagram 40 illustrating the transition is between states for the encoding of four input values (i.e., "0", "1", "2" and "3",' into five output levels (i.e., output levels A, B, C, D and E), according to a preferred embodiment of the present invention. It should be appreciated that since there are four input values, each input value may represent a bit pair (i.e., "00," "01," "10," and "11").

Therefore, each output level will represent two bits, rather than one bit, as in conventional encoding systems. Moreover, where N different input values are encoded into at least N+1 output levels, each input value can represent log.sub.2 (N) bits. As a result of using a single input value to represent a plurality of bits, higher data transfer rates are achievable, and bandwidth can be conserved. It should be appreciated that while in a preferred embodiment of the present invention the input values encode base 2 data (i.e., log.sub.2 (N) bits) the input values may also encode base X data. Therefore, the input values may represent values 0 through X-1 in base X with the encoded output having at least X different output levels. It should also be understood that there may be more than N+1 output levels and transitions thereof for encoding N different input values. This allows for simplified implementation of various error detection and correction methods.

A detailed description of the present invention as applied to the encoding of four input values into five output levels, will now be described with reference to FIGS. 4 and 5. FIG. 4 provides a timing diagram 50 which shows the transition of the output levels as each input value is encoded. It should be appreciated that in the embodiment shown in FIG. 4, each input value represents a bit pair. For the purpose of illustration, input value "0" represents bit pair "01," input value "1" represents bit pair "01," input value "2" represents bit pair "10" and input value "3" represents bit pair "11." As can be seen from FIG. 4, each consecutive output level will be different. Each output level A thru E is a discrete voltage level. For instance, output levels A thru E may correspond to voltages in the range of 0 to 5 volts. The input values shown in FIG. 4 are encoded into output levels A thru E according to the algorithm shown in flow chart 60 of FIG. 5. Beginning with step 62, a FIRST flag is set to TRUE. This will indicate that this is the first input value to be encoded. At step 64, an input value will be read in. Next, at step 66, it is determined whether the input value is the first input value to be encoded, by determining the status of the FIRST flag. If the input value is the first input value to be encoded, a first set of rules (steps 70-76) will be applied. If the input value is not the first input value to be encoded, it will be determined whether a second set of rules (steps 80-86) should be applied, as will be discussed below. For instance, in FIG. 4, the first input value is a "0" (corresponding to bit pair "0"). Accordingly, the conditions exist for applying the first set of rules. In particular, step 70 will be executed. In this respect, the output level will be set to A and the LAST variable will be set to "0." The LAST variable is used as the reference value to determine the appropriate set of rules to be applied following the first input value, as will be described below in connection with step 68.

It should be understood that only one of the steps 70-76 will be valid when applying the first set of rules. Accordingly, step 90 will follow step 70. Step 90 sets the FIRST flag to FALSE for the subsequent input values. The algorithm then returns to step 64 to read in the next input value. In FIG. 4, the next consecutive input value is a "1." Since the FIRST flag is now set to FALSE, the algorithm will proceed from step 66 to step 68. At step 68, it is determined whether the input value is less than the LAST variable. This step determines whether the first set of rules (steps 70-76) should be applied or whether the second set of rules (steps 80-86) should be applied. In the present example, the input value of "1" is greater than the LAST variable, which has been previously set to "0" at step 70. Therefore, the algorithm will apply the second set of rules (steps 80-86). Since the input value is "1," step 82 will be executed. Step 82 sets the output level to C and the LAST variable to 2. The algorithm then proceeds to step 90 and returns again to step 64 for reading in the next consecutive input value. The algorithm will continue in this manner until all of the input values have been encoded as output levels.

With reference to FIG. 4, it should be appreciated that the output level of the preceding encoded input value will determine the output level for the next consecutive encoded input value. In particular, the next consecutive input value will be encoded as one of the four remaining output levels. As a result, when two consecutive input values are the same, such as the consecutive 3's following the first three input values in FIG. 4, each of the 3's will be encoded as different output levels. In the case of the first "3," the output level is E, whereas the second 3 is encoded as output level D. Since no consecutive output level will be the same, the output levels will transition for each consecutive encoded input value.

Referring now to FIG. 6, there is shown a flow chart 100 which illustrates an algorithm for decoding output levels back into input values, according to a preferred embodiment of the present invention. Beginning with step 102, the FIRST flag is set to TRUE indicating that this is the first output level to be decoded. At step 104, the output level is read in. For steps 106-114, an input value is determined based upon the output level read in. However, in some cases this input value will be modified, as will be explained below in connection with step 118. Therefore, the decoded input value will be determined based upon a set of rules determined by both the current output level and one or more prior output levels. If the output level is the first output level read in (i.e., FIRST=TRUE), then the input value is not modified. In this respect, the algorithm will proceed from step 116 to step 120 where the LAST variable will be set the input value 5. It should be appreciated that the LAST variable is used to det if an input value needs to be modified, as will be explained in connection with step 118. Proceeding next to step 122, the FIRST flag is set to FALSE for reading subsequent output levels. At step 124, the input value is stored. The algorithm now returns to step 104, to read in the next consecutive output level. After evaluating the output level at steps 106-114, if the FIRST flag is no longer true (step 116), the algorithm proceeds to step 118. At step 118, it is determined whether the input value (obtained at one of the steps 106-114) is greater than the LAST variable If so, the input value is modified by decrementing it by one. If the input value is not greater than the LAST variable, then the input value is not modified. The algorithm then proceeds to step 120, where the LAST variable is set equal to the present input value, and step 122. At step 124, the input value is stored. The algorithm then returns to step 104 to read in the next consecutive output level. The algorithm will continue in this manner until all of the output levels have been decoded back to the original input values.

As noted above, each consecutive output level in the encoded waveform will be different, and thus necessitate a transition. As a result, the decoding system will not require an external clocking signal to synchronize with the encoded waveform. In this regard, the decoding system is self-synchronizing with the encoded waveform by using the transition of each consecutive output level as the indicator that a new output level has been received for decoding. Thus, the decoder can be easily synchronized with an encoded waveform having a variable transmission speed.

It should be understood that while FIGS. 4-6 show the implementation of only five output levels, the number of output levels may be significantly greater. As a result, the number of different input values may also be significantly greater. By increasing the number of output levels and input values, the number of bits represented by each input value can also be increased. Accordingly, as noted above, the present invention can be used to substantially increase the data transfer rate and conserve bandwidth.

It should also be appreciated that FIGS. 4-6 illustrate fixed timing relationship between one output level and the next solely the purpose of illustrating the present invention. In this regard, the time scale itself is completely arbitrary, and the time required to transition from one output level to another is also completely arbitrary. Accordingly, it should be understood that the present invention can maximize the use of available bandwidth by varying the timing relationship from one transition to another For example, in a bandwidth limited transmission medium, a change from one output level to a nearby output level, such as from A to B, will stabilize quickly, whereas a change from one output level to a distant output level, such as from A to E, will take longer to stabilize. Therefore, small changes can be transmitted more quickly. FIG. 7 provides a timing diagram 160 which shows the timing where stabilization of the transitions varies depending upon the relative difference between consecutive output levels. As can be seen from the diagram, the time for a single level change (e.g., A to B) takes approximately half the time needed for a change of two levels (e.g., B to D).

It should be appreciated that large changes between consecutive output levels may generate significant noise, and thus require increased bandwidth. As a result, it might be necessary in some cases to limit the changes between consecutive output levels to the nearest 50 percent of the available output levels. Therefore, there may be more than N+1 output levels for encoding N input values. For instance, an encoder having ten output levels might produce a step of one of four levels per each transition, encoding two bits at a time, but reducing the needed bandwidth of the channel.

Referring now to FIG. 8, there is shown a block diagram of a hardware arrangement 130 for encoding input values into output level transitions. Arrangement 130 is generally comprised of a buffer 132, encoding logic 134, and a digital-to-analog converter 136. In a preferred embodiment of the present invention, buffer 132 is a FIFO chip for buffering the received data. For instance, buffer 132 may take the form of a Cyprus Semiconductor CY7C464. Encoding logic 134 is programmed to implement the algorithm in the manner as described in connection with FIG. 5. In a preferred embodiment of the present invention, encoding logic 134 takes the form of an EPLD device, as the Altera EPM7128ELC. Digital-to-analog converter 136 may take the form of an 8-bit video DAC, such as the TDA8702 from Philips Components.

Arrangement 130 operates in the following manner. Unencoded data is stored in buffer 132. The unencoded data are input values which may represent one or more bits. Encoding logic 134 reads out the unencoded data and encodes it into output levels transitions which are sent to digital-to-analog converter 136. It should be appreciated that the analog coded data may be transmitted using a variety of different mediums, including a television signal. For instance, encoded data may be transmitted during the active video portion of the television signal. Accordingly, large quantities of data can be quickly and conveniently transferred.

Referring now to FIG. 7, there is shown a block diagram of hardware arrangement 150 for decoding output levels transitions into input values. Arrangement 150 is generally comprised of an analog-to-digital converter 152, a buffer 154 and decoding logic 156. Analog-to-digital converter 152 is preferably an 8-bit video ADC, such as the TDA8708B from Philips Components. In a preferred embodiment of the present invention, buffer 154 is a FIFO chip for buffering than digital data. For instance, buffer 154 may take the form of a Cyprus Semiconductor CY7C464. Decoding logic 156 is programmed to implement the algorithm in the manner as described in connection with FIG. 6. In a preferred embodiment of the present invention, decoding logic 156 takes the form of an EPLD device, such as the Altera EPM7128ELC.

Arrangement 150 operates in the following manner. Analog-to-digital converter 152 receives the encoded output levels and converts them to digital data, Buffer 154 stores the digital data. Decoding logic 156 reads out the digital data from buffer 154 and decodes the encoded output level transitions into input values. These input values in turn may be converted to one or more bits.

It should be appreciated that arrangements 130 and 150, as described above, are provided solely for the purpose of illustrating a preferred embodiment of the present invention and that numerous other arrangements are suitable as well.

As indicated above, digital data encoded as analog coded data may be transmitted using a variety of different mediums, including a television signal. In this regard, encoded data may be transmitted during the active video portion of a television signal, thus allowing for extremely high data transfer rates. A data transmission system including a system for encoding the digital data as encoded analog data and transmitting the encoded analog data as a mock television signal compatible with the NTSC standard, and a system for receiving the encoded analog data as a mock television signal compatible with the NTSC standard and decoding the encoded analog data to retrieve the original digital data, will now be described in detail. It should be appreciated that while the present invention is described with reference to a "television signal" (which includes VHF and UHF FM RF signals, cable TV signals, satellite TV signals, microwave TV signals and closed-circuit TV signals), the present invention is also applicable to other radio frequencies.

Reference is first made to FIGS. 10 and 11, which respectfully illustrate horizontal and vertical timing for an NTSC-compatible television signal. It should be appreciated that while the present invention will be described with reference to an NTSC-compatible television signal, the present invention may be modified for use with other television signal standards, including PAL, SECAM, HDTV, as well as proprietary television signals. As is well known, the NTSC specification calls for interlace scanning. A scanning pattern has 262.5 lines per field and two fields per frame. Therefore, each frame has 525 lines, which forms one complete image. Moreover, the scanning rate is 15,750 lines per second (i.e., 63.55 .mu.sec per line), thus providing 30 frames per second (i.e., 60 fields per second). It should be understood that the value 15,750 lines per second and 60 fields per second are approximate values. The actual values are dependent upon whether a color or black & white television signal standard is being used. In a preferred embodiment of the present invention frequencies for a color signal are used, thus there are 15734.265 scan lines per second and 59.94 fields per second. However, approximate values are used herein for the purpose of describing the present invention.

To prevent horizontal retrace lines from being observed on the screen as the electron beam scans horizontally across the screen to begin a tracing a new line, a horizontal blanking pulse is applied to the video signal, the leading edge of which precedes the leading edge of a horizontal synchronizing pulse. Accordingly, a horizontal blanking interval of 11.122 .mu.sec is established, during which a horizontal synchronizing pulse lasting 4.77 .mu.sec is generated. Since the horizontal blanking period is 11.122 .mu.sec (including the 4.77 .mu.sec for the horizontal synchronizing pulse) and there are 63.555 .mu.sec per line, this leaves 52.433 .mu.sec for an active video period per line, during which visual information is displayed (FIG. 10).

Similarly, to prevent vertical retrace lines from being observed on the screen as the electron beam scans vertically across the screen to begin tracing another field, a vertical blanking pulse is applied to the video signal (FIG. 11). Accordingly, a vertical blanking interval of 21 lines (i.e., 1.334 millisec) is established, during which a vertical synchronizing pulse (0.381 millisec) and equalizing pulses (2.3 .mu.sec each) are generated. Since the vertical blanking period is 21 lines or 1.333 millisec (including the 0.381 millisec for the vertical synchronizing pulse and the 2.3 .mu.sec for equalizing pulses), this leaves only 241.5 lines (15.33 millisec) for an active video period per field, (FIG. 11). Of course, some of this active video period per field will be unavailable for displaying information due to the horizontal blanking interval described above.

The NTSC standard waveform is divided into five phases: pre-equalization, serration, post-equalization, subphase and "video active". The first four phases occur during the vertical blanking interval, while the "video active" phase occurs during the active video period and the horizontal blanking interval.

In a preferred embodiment of the present invention the active video period of the television signal is used to transmit encoded digital data. At the same time, "mock" blanking, synchronizing, and equalizing pulses are generated to comply with the NTSC standard. However, it should be appreciated that the present invention is suitably modified to also transmit encoded digital data during horizontal and vertical blanking intervals, since in actuality the present invention makes no use of the signals generated during these intervals. The "mock" signals are generated solely to comply with the requirements of the NTSC standard.

Referring now to FIG. 12, there is shown a block diagram of television signal data transmission system 200. Data transmission system 200 is generally comprised of a transmitter/encoder 202, a receiver 302, general purpose computer systems 210 and 310, and a communications medium 190. Transmitter/encoder 202 includes an oscillator 204, a digital-to-analog (D/A) converter 206, a control unit 220 and a FIFO (First-In-First-Out) memory 208. Oscillator 204 provides a clock signal to both D/A converter 206 and control unit 220. Oscillator 204 takes the form of a suitable high speed crystal oscillator of approximately 25 MHz (e.g., 25.175 Mhz) or other suitable frequency. D/A converter 206 receives encoded data in a digital form from control unit 220, and converts it to corresponding analog data. In a preferred embodiment of the present invention D/A converter 206 takes the form of an 8-bit video D/A converter, such as the TDA8702 from Philips Components. Control unit 220 performs the operations necessary to encode data, as will be described in detail below. Control unit 220 communicates with FIFO (first-in-first-out) memory 208 and with computer system 210 (via PC bus 212). In this regard, control unit 220 receives status data from FIFO 208 and sends/receives data to/from FIFO 208. FIFO 208 stores the raw data to be encoded. Control unit 220 also send status data to computer system 210 and sends/receives data to/from computer system 210. In a preferred embodiment of the present invention, control unit 220 takes the form of a suitable logic device, such as an EPLD, PAL, GAL, PLD, FPGA, ASIC or CPU. For purposes of illustrating a preferred embodiment of the present invention control unit 220 takes the form of an Altera EPM7128ELC EPLD. Importantly, the EPLD provides for parallel logic, which allows for simultaneous operations. In a preferred embodiment of the present invention FIFO 208 takes the form of a Cyprus Semiconductor CY7C464.

It should be appreciated that a preferred embodiment of transmitter/encoder 202 does not include a standard 3.58 MHz color reference oscillator. In this regard, a "mock" black & white signal is generated, in order to attain higher bandwidth available for encoding data.

Receiver/decoder 302 includes an oscillator 304, an analog-to-digital (D/A) converter 306, a control unit 320 and a FIFO (First-In-First-Out) memory 308. Oscillator 304 provides a clock signal to both D/A converter 306 and control unit 320. Oscillator 304 takes the form of a suitable high speed crystal oscillator of approximately 25 MHz (e.g., 25.175 Mhz), or other suitable frequency. A/D converter 306 receives encoded data in a digital form from control unit 320, and converts it to corresponding analog data. In a preferred embodiment of the present invention A/D converter 306 takes the form of an 8-bit video A/D converter, such as the TDA8708B from Philips Components. Control unit 320 performs the operations necessary to decode data, as will be described in detail below. Control unit 320 communicates with FIFO 308 and with computer system 310 (via PC bus 312). In this regard, control unit 320 receives status data from FIFO 308 and sends/receives data to/from FIFO 308. FIFO 308 stores the decoded data. Control unit 320 also send status data to computer system 310 and sends/receives data to/from computer system 310. In a preferred embodiment of the present invention, control unit 320 takes the form of a suitable logic device, such as an EPLD, PAL, GAL, PLD, FPGA, ASIC or CPU. For purposes of illustrating a preferred embodiment of the present invention control unit 320 takes the form of an Altera EPM7128ELC EPLD. As noted above, the EPLD provides for parallel logic, which allows for simultaneous operations. In a preferred embodiment of the present invention FIFO 308 takes the form of a Cyprus Semiconductor CY7C464.

In a preferred embodiment of the present invention, computer systems 210 and 310 take the form of an 80.times.86 or Pentium based personal computer (PC). However, computer systems 210, 310 are not limited to personal computers, and may take other forms, including a SUN Sparc station, Silicon Graphics Workstation, and a set-top satellite receiver. It should be appreciated that in a preferred embodiment of the present invention transmitter/encoder 202 and receiver/decoder 302 take the form of plug-in PC boards which respectively interface with PC buses 212, 312 of computer systems 210, 310.

Communications medium 190 may take the form of any medium suitable for transmission of television signals, including a cable system, a satellite system, a microwave system, a closed-circuit system, or an over-the-air broadcast system.

Data transmission system 200 operates in the following manner, Computer system 210 sends raw data (digital) to control unit 220. In turn, control unit 220 stores the raw data in FIFO 208. Simultaneous with this operation, control unit 220 reads raw data from FIFO 208 and encodes the raw data as part of an encoded NTSC compatible television signal, as will be described in detail below. The encoded data, which is still in digital form, is fed to D/A converter 206 for conversion to analog form. The analog encoded data is then transmitted via communications medium 190 to receiver 302. A/D converter 306 receives the analog encoded data and converts it to digital form. In turn, control unit 320 stores the encoded data in FIFO 302. Simultaneous with this operation, control unit 320 reads the encoded data from FIFO 308 and decodes the data to obtain the original raw data, as will be described in detail below. Control unit 320 sends the decoded data to computer system 310. The decoded data may be displayed by computer system 310 on a monitor, in a case where the decoded data represents visual data.

It should be understood that the foregoing hardware configuration is described solely for the purpose of illustrating a preferred embodiment of the present invention, and that numerous other hardware configurations are also suitable for carrying out the present invention.

The encoding operation performed by control unit 220 will now be described in detail. It should be understood that the encoding operation will be described with reference to the encoding of four input values (i.e., 0, 1, 2, and 3) into five output levels (i.e., output levels A, B, C, D and E), according to the system of encoding described in detail above. Each input value represents a respective bit pair (i.e., 00, 01, 10, 11). Accordingly, a byte (8 bits) of data is defined by a set of four input values. The specific system of encoding, and the number of input values and output levels are exemplary, and are thus provided solely for the purpose of illustrating a preferred embodiment of the present invention, and not for limiting same.

As a part of the encoding operations, control unit 220 performs basically two sets of operations. The first set of operations is to encode the appropriate NTSC signals for the first four phases of the NTSC television signal, namely, pre-equalization, serration, post-equalization, and subphase. These first four phases include the vertical blanking pulse, equalizing pulses and vertical synchronizing pulses. The second operation is to encode the appropriate NTSC signals for the fifth phase (i.e., "video active" phase) of the NTSC television signal. The "active video" phase includes the horizontal blanking pulses, horizontal synchronizing pulses, as well as the encoded bit pairs.

It should be appreciated that the NTSC television signal waveform has a range of voltages that corresponds to different degrees of brightness. Referring now to FIG. 13, there is shown an NTSC television signal waveform for a black and white transmission. The "picture information" ranges from "black" (IRE level 0) to "white" (IRE level 100). The picture information will correspond to the encoded bit pairs. The vertical blanking pulses, vertical synchronizing pulses, equalizing pulses, horizontal blanking pulses, and horizontal synchronizing pulses range from "black" (IRE level 0) to "blacker than black" (IRE level -40). A digital output value is assigned to each required output voltage level. The voltage range from white to "blacker than black" has been considered and an appropriately spaced digital output value has been assigned thereto. In this respect, a digital output value of 0 is assigned to "blacker than black" and subsequent digital output values are assigned at appropriate increments.

The state of the encoder state machine and corresponding outputs are shown in the TABLE 1 of FIG. 14A. Control unit 220 presents digital encoded data to D/A converter 206, which in turn converts the digital encoded data to analog encoded data. The digital encoded data is an 8-bit binary number. The 3 most significant bits (MSB) of the 8-bit binary number will vary depending upon the encoded output information. The remaining five bits of the digital encoded data are fixed to zero. As a consequence, the possible values for the digital encoded data are 0, 32, 64, 96, 128, 160, 192 and 224, where each value corresponds to different encoded output information. Digital encoded data values 224,192,160,128 and 96 correspond respectively to output levels E, D, C, B and A/Idle. It should be understood that "idle" refers to a pause in the transmission of data. Digital encoded data value 64 indicates horizontal and vertical blanking pulses, while digital encoded data value 0 indicates horizontal and vertical synchronizing pulses, as well as equalization pulses. Digital encoded data value 32 is unused because no encoded information requires a voltage level between the voltage level corresponding to digital encoded data values 64 and 0. Moreover, there is a need to preserve the difference in voltage levels between the levels for blanking and synchronizing in order to comply with the NTSC standard.

Referring now to FIG. 14B, there is shown a timing diagram showing the encoded digital data for the first four phases of the NTSC signal (which includes vertical blanking pulses, vertical synchronizing pulses and equalizing pulses) and the first two scan lines of an active video phase. The encoded digital data shown in FIG. 14B is input to the digital-to-analog converter. As can be seen, the digital encoded data for the first four phases of the NTSC signal will toggle between 64 and 0. As noted above, the digital encoded data value of 32 is skipped in order to preserve the appropriate difference in voltage for the vertical blanking pulses, vertical synchronizing pulses and equalizing pulses, according to the NTSC standard. FIG. 14C provides a more detailed view of the digital encoded data for the first scan line, shown in FIG. 14B. FIG. 14D shows a portion of the first scan line shown in FIG. 14C. This timing diagram shows transitions between the levels A thru E for encoding bit pairs. In this regard, the first transition of the scan line is from level A to level B, which encodes bit pair "00." The next transition from level B to level E encodes bit pair "11." Four transitions encodes a byte of data. It should be appreciated that according to a preferred embodiment of the present invention, the bit pairs are encoded in the order of least significant bit pair to most significant bit pair. Therefore, in the example shown in FIG. 14D, the first byte of data is actually "00 00 11 00" or 12 (base 10).

For the first set of operations, the EPLD (i.e., control unit 220) is programmed as a state machine to generate digital representations of the appropriate NTSC waveform signals for the first four phases of the NTSC signal, as discussed above. The control logic for carrying out this first set of operations is a part of the EPLD program code listing set forth below:

The steps for programming the EPLD to generate digital representations of these NTSC waveform signals is well known to those skilled in the art, and thus will not be described in further detail herein. For further details regarding the programming of the EPLD to carry out the first set of operations reference is made to the Application Notes available from Altera Corporation, which are incorporated herein by reference.

In a preferred embodiment of the present invention oscillators 204 provides a master clock signal to control unit 220 at a frequency of 25.175 Mhz. This provides a faster data transfer rate than the typical NTSC clocking frequency of 14.318 Mhz, while still complying with the NTSC standard. Since the master clock frequency is 25.175 Mhz and the active video period is 52.433 .mu.sec per line, there are 1320 clock pulses per line. The EPLD is programmed to have a pair of counters. The first counter is a 12 bit counter, where the 4 lowest bits form a decade counter. Accordingly, the first counter counts 10 clock pulses 132 times (for a total of 1320 clock pulses). On every 10th clock pulse a transition occurs. 132 transitions occur for each horizontal line. When the first counter reaches a full count of 1320, the first counter will hold while waiting for the horizontal blanking interval to finish. Because there are 132 transitions per line, 132 different output levels can be encoded on each line. Moreover, since the active video period is 52.433 .mu.sec per line, the period of each transition is 0.3972 .mu.sec.

The second counter is a 6 bit counter, where the 4 lowest bits form a decade counter. Accordingly, the second counter counts 10 clock pulses 4 times (for a total of 40 clock pulses). Since a transition occurs every 10 clock pulses, a new pair of bits is encoded to an output level every 10 clock pulses. As a result, every 40 clock pulses indicates the encoding of 8 bits (1 byte) of data.

Referring again to FIG. 14A, control unit 220 (EPLD) is programmed to operate as a state machine to generate the appropriate signals for the horizontal blanking interval and for encoding the data bits. In this regard, the state machine has states 7, 6, 5, 4, 3, and 2. The highest three bits of the digital encoded data (i.e., the MSB digital encoded data), is determined by "ANDing" the state with a csync output, which is low (i.e., "zero") during the horizontal synchronizing pulse. As a result, state machine "state 2" generates an MSB digital encoded data output of 2 for horizontal blanking, and an MSB digital encoded data output of 0 for horizontal synchronizing. State machine states 3 through state 7 generates a respective MSB digital encoded data output of 3 through 7. As indicated above, the digital encoded data (8 bits) is fed as an input to D/A converter 206. The output of D/A converter 206 is transmitted to receiver/decoder 302 via communications medium 190.

It should be appreciated that the state machine is suitably modified to have a different state corresponding to each and every type of encoded output information, rather than have state 2 correspond to both horizontal blanking and horizontal synchronizing. Moreover, it should be noted that state 3 (which generates an MSB digit encoded data output of 3) also corresponds to an idle condition, wherein the transfer of data has been paused.

Referring now to FIGS. 15A and 15B, there is shown a flow diagram 230 illustrating the EPLD control unit logic for encoding data. Flow diagram 230 describes the operations of the state machine in EPLD control unit 220 for encoding data. It should be kept in mind that the EPLD performs multiple logic operations simultaneously, and thus the flow diagram should not be interpreted as defining a series sequential operations, but rather as an aid to understanding the underlying logic operations performed by the EPLD.

Beginning with step 232, the encoding operations start by continuously generating the digital encoded data for the first four phases of the NTSC waveform (including vertical blanking pulses, vertical synchronizing pulses and equalizing pulses), as described above. Next, the raw data is sent to FIFO 208 (step 234). The term "raw data" refers to unencoded data, which in the illustrated embodiment is a bit pair. If it is time for a horizontal sync pulse the MSB digital encoded data is set to zero (step 238). If it is not time for a horizontal synchronizing pulse, we determine if we are in a horizontal blanking interval or approaching a horizontal blanking interval (step 240), If it is time for a horizontal blanking pulse the MSB digit encoded data is set to two (step 242). If it is not time for a horizontal blanking interval, then we are ready to encode "raw data." If the FIFO is empty (step 244), the MSB digital encoded data output remains unchanged (step 246), whereas if the FIFO is not empty, a byte of raw data is read from the FIFO for encoding (step 248). For each pair of bits in the 8-bit raw data byte it is determined what was the last MSB digital encoded data output (steps 250 and 254). Depending upon the last MSB digital encoded data output, one of steps 256, 258, 260, 262 or 264 is followed. The encoding of the current raw data bit pair is then performed by evaluating the bit pair with the logic of steps 256a-256d, 258a-258d, 260a-260d, 262a-262d, or 264a-264d. It should be appreciated that this encoding scheme is the same as encoding scheme described in detail above. Once a complete 8 bit raw data byte has been encoded the logic continues to step 252.

The foregoing system for encoding the raw data provides a substantially high data transfer rate. As discussed above, the NTSC television signal waveform has a scanning rate of 15,750 lines per second. Accordingly, there are 63.55 .mu.sec per line. At a clock speed of 25.175 Mhz, there are 1600 clock pulses (i.e., counts) per line. Only 1320 clock pulses are available for transferring data, when accounting for the horizontal blanking interval. 2 bits of raw data are encoded every 10 clock pulses, therefore 264 bits (i.e., 33 bytes) of raw data are encoded every scan line. As indicated above, there are 241.5 scan lines available per field, for transferring raw data (accounting for the vertical blanking period). Accordingly, 483 scan lines are available per frame for transferring raw data. It then follows that there are 15,939 bytes per frame and 478,170 bytes per second (i.e., 3,825,360 bits per second) It should be appreciated that the data transfer rate can be further increased by modifying the clock speed and/or encoding the raw data into a greater number of levels, as discussed above.

The decoding operations performed by EPLD control unit 320 of receiver/decoder 302 will now be described in detail with reference to FIGS.16A-19. FIGS. 16A and 16B show a flow diagram 330 which illustrates the logic of the decoding operations performed by EPLD control unit 320. First, the presence of an encoded signal is detected (step 332). In this regard, AID converter 306 converts analog encoded data to digital encoded input data. Next, it is determined what level the digital encoded input data is in. The evaluation of ranges is necessary due to noise, interference and converter tolerances, which effect the conversion of analog encoded data back to the original digital encoded data output by the transmitter/encoder 202. The range into which the digital encoded input data falls is used to determine the state of the encoder EPLD control unit 220 and the corresponding encoded input information. Each digital encoded input data range has a corresponding input pattern and encoded input information level.

If the digital encoded input data is at a level indicative of a vertical blanking interval or horizontal blanking interval, there is no data to decode (steps 336 and 338). In this regard, the data received by receiver/decoder 302 is ignored, since the signal corresponding to the vertical and horizontal blanking interval are generated merely to comply with the NTSC standard.

If the digital encoded input data is at a level above the level corresponding to the vertical and horizontal blanking intervals, then a decoding procedure is initiated. In this regard, counters are set for decoding, and the "last level" is set to A (steps 336, 340 and 342). The counters are used to sample consecutive encoded digital input data and establish a stable value. To this end, previous and current digital encoded input data samples are averaged and stored (step 346). The ranges of the last four averages are compared, and if the ranges are all the same and correspond to a level different from the level of the last set of four matches (step 348), then a four-bit counter is preset to 16. The counter is then subsequently decremented, while more comparisons are performed. When the counter has decremented to 12, it is determined that the input data has stabilized. This acceptable digital encoded input data is decoded according to steps 350-366. The decoding logic is repeated (step 368) to decode the bit pairs. Once a byte of data has been decoded, the byte is stored in the FIFO (step 370). It should be appreciated that the decoding scheme implemented in FIGS. 16A and 16B are the same as the decoding scheme described in detail above. It should be noted that step 348 determines a change in the digital encoded input data has occurred. Where no change occurs, no new encoded data has been received for decoding.

Referring now to FIG. 17, TABLE 2 shows the correspondence between the original digital encoded data, the encoded input information, the encoder state, the digital encoded input data range, and the input pattern.

It should be appreciated that A/ID converter 306 includes an automatic gain control circuit (AGC) in order properly convert (i.e., scale) the input analog data levels to the appropriate digital input data values. In this regard, A/D converter 306 receives gate A and gate B pulses from control unit 320. The decoded horizontal synchronizing pulse and horizontal blanking pulse are used by the AGC. In particular, the synchronizing pulse is used to set a zero reference, while the blanking pulse (following the synchronizing pulse) is used to adjust the gain. The foregoing procedure for setting the AGC is well known to those skilled in the art, and therefore will not be described in further detail herein.

The control logic of the decoder control unit will now be described in further detail with reference to the EPLD program code listing set forth below:

Referring first to SECTION 8, on a sample by sample basis (i.e., a 25.175 Mhz sampling rate), the sum of the current analog input ad[7..0] and the previous analog input nad[7..0] is computed and put into nnad[8..0] for later use. The current analog input ad[7..0] is clocked into nad[7..0] to set it up for the next cycle.

At SECTION 10 ad7, ad6, and ad5 (the three highest bits of the analog input) are watched. If any one is non-zero, set a10, the above level 0 (L0) flag. The current analog input ad[7..0] is compared with L1-1 (79), and if it is greater then set a11, the above level 1 (L1) flag. These flags are based on the raw ADC data, and are used to synchronize the counter cnt[11..0] as well as the gatea and gateb signals, which are fed back to the ADC for automatic gain and level control.

With reference to SECTION 14, the blnk signal is set when both a10 is false (i.e., NOT above L0) and cnt[11..0]>1023, which means that at least 40.675 us (1024 clocks at 25.175 Mhz) has passed since the last time it was reset. As the bink signal is set, cnt[ 11..0] is reset to 0 and begins to count upward again. With bink now true, the system waits until cnt[11..0] reaches 240, or 9.533 us, and then bink is reset and counter cnt[1..0] is set back to The system then waits again until counter cnt[11..0] has counted to at least 1024, and when a10 goes false, the bink signal is set again.

Turning now to SECTION 15, when cnt[11..0] reaches 4 and bink is true, gatea is set true. It remains this way until cnt[11..0] reaches 56, and then gatea is set false. Note that reset occurs both in and out of blanking. While the second reset is unnecessary, it reduces the logic. gatea is true for 52 counts (2.066 us) starting 4 counts (159 ns) after we reach the sync level (i.e., when al0 is false).

Similarly, in SECTION 16, when cnt[11..0] reaches 176 and a10 is true (not at sync level) and a11 is false (at blanking level), we set gateb true. When cnt[11..0] reaches 228 or when a10 goes false (at sync level), we set gateb false. This will produce a 52 count (2.066 us) signal starting 176 counts (6.991 us) after we reach the sync level (i.e., when a10 is false) or will truncate it in the case that we return to sync level (such as during the equalization pulses in the vertical sync).

Referring now to SECTION 11, every time the sum of the previous analog input (nad[7..0]) and the current analog input (ad[7..0]) is computed, the result of that sum is averaged (i.e., by dropping the low bit of the sum), and the average is range compared to determine which of 5 levels (L2, L3, L4, L5, and L6) it represents. The signal ala3 indicates that we are below L2, which would correspond to the encoder being in state 3 (or lower). Signal ala4 indicates that the encoder state was 4, while ala5, ala6, and ala7 mean states 5, 6, and 7 in the data stream. alb[7..3] is set to what ala[7..3] was last clock, and alc[7..3] was two clocks ago, and ald[7..3] was three ago in time. As a result, a history of levels (or encoder states) is generated.

Turning now to SECTION 12, if the current, last, 2nd last, and 3rd last levels (i.e., encoder states) all agree, the data is decoded into a bit pattern, where al[a..d]3 means 0 (000 binary), al[a..d]4 means 1 (001 binary), al[a..d]5 means 2 (010 binary), al[a..d]6 means 3 (011 binary) and al[a..d]7 means 4 (100 binary) into the input pattern in[2..0]. If four consecutive levels (i.e. encoder states) are not the same, the input pattern is prevented from changing. Also, when there is a change in the input pattern, ind[2..0] will have the previous pattern for 1 clock cycle.

SECTION 13 implements the decoder, which is best understood by reference to TABLE 3, set forth in FIG. 18. The labels *res0 and *res1 indicate what the "next" values should be. When the signal strobe is shown as "0" in the above table, a strobe is generated. As can be seen, there is no strobe when the input pattern in[2..0] and the delayed pattern ind[2..0] are the same (indicated with [no]). The signal strobe1 is the same as strobe, 1 clock delayed. It should be appreciated that if the previous pattern in ind[2..0] is looked up using the current output res[1..0] and the current pattern in[2..0], the next output *res[1..0] is obtained (which is the decoded data).

Referring now to SECTION 5, when strobe1 goes low, symto[3..0] counter is set to 14. On each successive clock, it counts down 1 count, toward 0.

With regard to SECTION 2 and SECTION 4, when symto[3..0] gets down to 12, the state machine clocks the current res1/res0 pair into the appropriate output pair based on the current state of the machine (sw/sw, sw/sw, sw/sw, sw/sw), and then trips to the next state. If, within states 3, 4, or 5, symto[3..0] gets down to 0 (timeout), the state machine is reset to state 2. Once state 6 has been reached, we have a valid byte ready to write to the FIFO, so on the next tick the fifo.sub.-- w line is signaled, and the state machine is reset to state 2. It should be appreciated that when symto[3..0] gets down to 12 and the encoder state remains the same (i.e., the same input level), then good data has been obtained.

SECTION 6 provides address decodes for fifo.sub.-- r, r02bc and w02bc, to give access to this device within the PC address space.

SECTION 9 is directed to data bus I/O functions where read produces status flags, and write can set modes.

SECTION 3 and SECTION 7 are directed to a raw mode, which is unimportant to normal operation.

SECTION 1 is directed to definitions, defaults, variables, global clock and reset signals.

Referring now to FIG. 19 there is shown a timing diagram showing the digital encoded input data (in analog form) and other decoder data, as will be described below. The analog data waveform is the waveform input to the analog-to-digital converter of the receiver/decoder. The analog data waveform shown in FIG. 19 includes the HSYNC (horizontal sync) and HBLANK (horizontal blanking) transitions, followed by noise. The transition from level A to level B marks the beginning of the encoded bit pairs. The level A to level B transition decodes to bit pair "00." The transition from level B to level A decodes to bit pair "00," and so on. As noted above in connection with the encoding procedure, the bit pairs are received in the order of least significant bit pair to most significant bit pair. Accordingly, the first byte of decoded data in the example shown in FIG. 19 is "00 00 00 00" (00hex/0 base ten) and the second byte of decoded data in the example shown in FIG. 19 is "00 00 00 01" (01hex/1 base ten). The subsequent bytes of data are 03hex and 04hex.

The corresponding decoder states are shown below the analog data waveform. State 2 is waiting for the first pair of data bits; transition from state 2 to 3 is clocking-in of the first pair of data bits to 8-bit temporary storage register SW (explained in detail below); state 3 is waiting for the second pair of data bits; transition from state 3 to state 4 is the clocking-in of the second pair of data bits to register SW; state 4 is waiting for the third pair of data bits; transition from state 4 to state 5 is the clocking-in of the third pair of data bits to register SW; state 5 is waiting for the fourth pair of data bits; and transition from state 5 to state 6 is the clocking-in of the fourth pair of data bits to register SW (thus completing a byte of data). Transition from state 6 to state 7 is a write pulse enable where the data stored in register SW is written to the FIFO. Transition from state 7 to state 2 is a write pulse disable.

FIG. 19 also shows the value stored in 8-bit register SW, which temporarily stores the decoded data bit pairs before they are written to the FIFO as a byte of data. The 8-bit register SW stores the bit pairs in their proper order as they are decoded. In this regard, the first decoded bit pair of a byte is stored as the least significant bit pair, while the last decoded bit pair of a byte is stored as the most significant bit pair. Once a full byte has been decoded and stored in register SW, the contents of register SW are written to the FIFO. Thereafter, new decoded bit pairs are written to register SW. However, it should be understood that the contents of register SW are not cleared, but rather, the new decoded data bit pairs will overwrite the old data bit pairs. Therefore, the value stored in register SW will not reflect the proper decoded data byte until all four bit pairs have been clocked-in to register SW. The hex values above the write pulses (FIG. 10) indicate the value stored in register SW at the time the data is written to the FIFO.

It should be appreciated from FIG. 19, that the decoder interprets any level below 116 as level A. In this regard, the decoder, according to a preferred embodiment does not generate decoded data during horizontal (and vertical) blanking intervals. The decoder only uses the horizontal synchronizing pulse and horizontal blanking pulse for calibrating the analog-to-digital converter (i.e., DC restoration). These and the other timing signal pulses are generated by the encoder to provide a "mock" NTSC-compatible signal. Therefore, it should be appreciated that the present invention can be modified to "skip" selected horizontal synchronizing and blanking pulses, and instead transmit (during the horizontal blanking interval) encoded data (i.e., encoded bit pairs). For example, if the horizontal synchronizing and blanking pulse are skipped every other scan line, then an additional 11 .mu.sec of time becomes available on each scan line to transmit encoded data. This provides an increased data transfer rate of approximately 400,000 bps (with 5 encoding levels). Moreover, the present invention can be modified to transmit encoded data (i.e. encoded bit pairs) during the period dedicated to the vertical blanking interval. Substituting encoded data for the equalization, vertical sync and vertical blanking pulses, will yield an additional 21 lines of data, 60 times a second. This allows for 1260 lines.times.34 bytes per line, or 41580 more bytes per second. Accordingly, a 332,640 bps increase is possible when using just 5 encoding levels. In addition, by starting to encode data earlier in the horizontal blanking interval period (at least 2 us of blanking is needed for the AGC) may net as high as a 20 more bits per scan line. This allows for a 315,000 bps increase maximum for a 5 level encoding scheme. It should be understood that the present invention is suitable for the foregoing modifications because it does not rely upon the timing signals of the horizontal and vertical blanking intervals for synchronization. Instead, the encoding scheme of the present invention has an inherent self-synchronizing characteristic, as discussed in detail above.

It should also be appreciated that the present invention allows for the transmission of video data encoded at approximately 1 million bits per second across the system at 4 million bits per second. Accordingly, video data can be sent "faster than real time." For instance, 2 hours of video data can be sent from point A to point B in 1/2 hour. By using a broadcasting medium, 2 hours of video data can be sent broadcast to points B1 through BN in a total of 1/2 hour. Moreover, it is contemplated that the present invention can be optimized to provide a data transfer rate in excess of 30 million bps, while complying with the NTSC standard.

As can be appreciated from the foregoing description the present invention dramatically shortens the time needed to transmit electronic data, including databases, digital video and digitized images. As indicated above, the data may be transmitted via wired or wireless transmission mediums. Since the encoding scheme of the present invention forms an integral part of the transmission medium itself, the transmission time is substantially reduced, just as if the data had first been farther compressed before transmission. It should be appreciated that the present invention may be implemented using a unidirectional transmission mode, or a bi-directional transmission mode with symmetrical or non-symmetrical data rates in the return path. Moreover, the return path may be via many means and is not limited to the same means as the initial transmission.

It should be appreciated that the present invention has myriad applications, including downloading of on-demand movies, Internet data transfer, tele-medicine (i.e., transfer of high-resolution medical images), and the like. Any application requiring the transfer of large quantities of data in a short period of time would be particularly well suited for use in connection with the present invention.

The foregoing description is a specific embodiment of the present invention. It should be appreciated that this embodiment is described for purposes of illustration only, and that numerous alterations and modifications may be practiced by those skilled in the art without departing from the spirit and scope of the invention. It is intended that all such modifications and alterations be included insofar as they come within the scope of the invention as claimed or the equivalents thereof.