Synchronization of Left/Right Channel Display and Vertical Refresh in Multi-Display Stereoscopic Computer Graphics Systems

This invention relates generally to multi-display computer graphics systems, and more particularly to methods and apparatus for synchronizing the display of left and right channels and for synchronizing vertical refresh cycles in stereoscopic multi-display computer graphics systems.

As the art of computer graphics has grown in sophistication, uses being made of computer graphics display systems have become increasingly various and creative. For example, in many modern applications, several display systems are employed at once to provide a larger viewing area than could be provided by a single display system operating alone. One such application is known popularly as a "virtual reality theater." In a typical virtual reality theater, multiple computer graphics display systems are used to project images on each of the walls of a room so that an observer within the room can see the images no matter in which direction he or she looks or moves. Often, the presentation of the images changes depending on the observer's position or orientation within the room as indicated by a tracking device. Other types of virtual reality theaters use multiple monitors oriented around a relatively stationary observer. The latter types of virtual reality theaters are frequently used, for example, in flight simulators.

Stereoscopic display techniques are also sometimes employed in computer graphics systems. In stereoscopic applications, left- and right-eye views or "channels" are sequentially and alternately displayed while special eyewear worn by the observer alternately occludes the observer's right and left channels of vision. When the eyewear and the display are synchronized properly, the observer's left eye always sees the left channel and the observer's right eye always sees the right channel. The effect for the observer is binocular stereopsis. In other words, the observer is given the experience of having depth perception while viewing the displayed scene.

If such a stereoscopic technique were to be employed in a multi-display system, then not only must all of the display devices in the system present the same channel (left or right) at the same time, but also the vertical refresh cycles should be synchronized so that all of the display devices in the system begin their vertical retrace at nearly the same time.

By way of background, a typical single-display computer graphics system 100 is shown in FIG. 1. CPU 102, system bus 104, system memory 106 and peripherals 108 represent any host computer system including a personal computer, workstation or mainframe. Display processor 110, frame buffer 112, video controller 114 and CRT monitor 116 represent a typical computer graphics "pipeline" 120 for displaying images generated by the host computer system. Pixel data representing an image are written into frame buffer 112 by display processor 110. (In lower-end systems, display processor 110 may not be present; in such lower-end systems, the host computer system writes pixel data into frame buffer 112 directly.) Video controller 114 reads pixel data from frame buffer 112, converts the pixel data into analog form, and drives CRT monitor 116 by generating appropriate horizontal and vertical timing signals and using the converted pixel data to determine R, G and B beam intensities. For stereoscopic applications, eyewear 118 is provided for alternately occluding the observer's eyes as previously described. Virtual reality theaters and other immersive environments are commonly constructed by using multiple instances of computer graphics pipelines like pipeline 120. Sometimes the multiple pipelines are coupled to a common system bus. For most modern applications, especially those involving stereoscopic computer graphics presentations, it is desirable for video controller 114 and CRT monitor 116 to comprise a progressive-scan rather than an interlaced-format system. Among the reasons for this are the flicker problems that are commonly associated with interlaced-format systems and the resolution reduction that is commonly inherent in stereoscopic interlaced-format applications.

FIG. 2 illustrates the logical organization of video controller 114. Video controller 114 cycles repeatedly through frame buffer 112 one scan line at a time. Raster scan generator 200 generates horizontal timing signals 202 and vertical timing signals 204, which in turn drive the raster scan in CRT monitor 116. Raster scan generator 200 also controls X address register 206 and Y address register 208, which together define what memory location will be specified by linear address generator 210. The memory addresses are generated in synchrony with the timing signals. Pixel data read from the accessed memory locations of frame buffer 112 are used as indices into look-up table 212. The contents of the corresponding locations within look-up table 212 are used to drive digital-to-analog converter ("DAC") 214. DAC 214 in turn produces the R, G and B beam intensity values used by CRT monitor 116.

It is known that raster scan generator 200 usually contains some form of video timing generator for producing horizontal timing signals 202 and vertical timing signals 204. Frequently, such video timing generators produce a V.sub.-- BLANK signal and a V.sub.-- SYNC signal as shown in FIG. 3, as well as an H.sub.-- BLANK signal and an H.sub.-- SYNC signal as shown in FIG. 4. CRT monitor 116 contains circuitry for generating the vertical and horizontal deflection signals shown in FIGS. 3 and 4, respectively, using the blank and sync signals as inputs. As can be seen in FIG. 3, the vertical deflection ramp signal retraces during VSYNC interval 300. In order to prevent the raster beam from being seen during vertical retrace, the R, G and B intensities are blanked during the retrace. Blanking actually begins at time 302 and ends at time 304. The interval between the beginning of blanking and the beginning of retrace is usually referred to as "vertical front porch" interval 306. The interval between the end of blanking and the beginning of active beam interval 310 is usually referred to as "vertical back porch" interval 308. For purposes of the discussion provided herein, the phrase "vertical refresh activity" will be used to denote any, all or some combination of the intervals 300, 306 and 308.

In the case of fully-programmable video timing generators, four counters might be used, one for each of the timing signals to be produced: V.sub.-- BLANK, V.sub.-- SYNC, H.sub.-- BLANK and H.sub.-- SYNC. In this manner, the relative lengths of all of the timing intervals may be controlled carefully by loading appropriate values into the counters and then decrementing the counters continuously. (In such an embodiment, a transition in a timing signal occurs whenever its corresponding counter reaches a zero count. The counter is then loaded with a second value corresponding to desired length of the next interval, and so on.) It is know that the intervals produced by such video timing generators may be altered by forcing a reset or load of the counter before the counter expires.

The horizontal timing of FIG. 4 is analogous to the vertical timing of FIG. 3. The horizontal deflection ramp signal retraces during HSYNC interval 400. In order to prevent the raster beam from being seen during horizontal retrace, the R, G and B intensities are blanked during the retrace. Blanking actually begins at time 402 and ends at time 404. The interval between the beginning of blanking and the beginning of retrace is usually referred to as "horizontal front porch" interval 406. The interval between the end of blanking and the beginning of active beam interval 410 is usually referred to as "horizontal back porch" interval 408. It should be noted, of course, that the horizontal cycle is much faster than the vertical cycle, commensurate with the number of lines in each frame. In fact, numerous horizontal retrace cycles may occur during one vertical front porch interval 306. Thus, to identify sub-intervals within vertical front porch interval 306, it is useful to speak in terms of the "first line of vertical front porch" and the "last line of vertical front porch."

For stereoscopic display systems, it is known to equip video controller 114 with left/right channel indicator 216. Left/right channel indicator 216 has a one-bit output for dictating which pixel data is to be used to drive CRT monitor 116 at any given moment. For example, in some stereoscopic implementations, left image data is stored in one memory area while right image data is stored in another memory area. In such implementations, the state of left/right channel indicator 216 is conventionally used by video controller 114 to determine which of the two memory areas should be displayed. The state of left/right channel indicator 216 is also typically used by eyewear 118 to determine which of the viewer's eyes is to be occluded at each moment. In prior art systems, left/right channel indicator 216 is a free-running oscillator; no automatic means is provided for synchronizing it with the left/right channel indicators of other computer graphics pipelines.

Moreover, in multi-display progressive-scan computer graphics systems, synchronization of vertical refresh cycles is complicated because no two crystals are the same. Therefore, no two video controllers have exactly the same clock frequency. The result for prior art progressive-scan multi-display systems is that, even if all video controllers were to begin a first vertical retrace at the same time, each would begin the next vertical retrace at a slightly different time. The systems would get further and further out of synchronization with each cycle.

By way of further background, it is known in interlaced-format environments to use a technique called "genlock." The genlock technique synchronizes vertical retrace, horizontal retrace and color burst phase and frequency among multiple interlaced-format display systems or sources such as those implementing the well-known NTSC composite video format. One by-product of using genlock in interlaced-format multi-display systems is that the timing of presentation for odd lines versus even lines is synchronized for all of the displays in the system. Thus, for stereoscopic multi-display systems that use an interlaced format in which the left channel is displayed on odd lines and the right channel is displayed on even lines, the genlock technique might be used to synchronize the display of left/right channels among the multiple displays, as well as to synchronize the vertical refresh cycles among the displays. As alluded to above, however, it is not desirable to use an interlaced format in stereoscopic applications because such a scheme inherently reduces image resolution by a factor of two. Moreover, the just-described form of genlock does not apply to progressive-scan systems.

It is therefore an object of the present invention to automatically synchronize the presentation of left and right channels by all of the computer graphics pipelines in a multi-display stereoscopic computer graphics system.

It is a further object of the present invention to automatically synchronize the vertical refresh cycles of each of the display devices in a multi-display stereoscopic computer graphics system.

In one aspect of the invention, a first computer graphics pipeline is coupled to a master synchronization system, and a second computer graphics pipeline is coupled to a slave synchronization system. The master synchronization system has a synchronization output which is coupled to a synchronization input of the slave synchronization system. The master synchronization system is operable to encode left/right channel information and video timing information (corresponding to activity occurring in the first computer graphics pipeline) onto the master synchronization output. The slave synchronization system is operable to manipulate the video timing and the left/right channel display within the second computer graphics pipeline responsive to its synchronization input. The result is to automatically cause the video timing and the left/right channel display in the second computer graphics pipeline to proceed substantially synchronously with the video timing and the left/right channel display in the first computer graphics pipeline. In a further embodiment, numerous slave synchronization systems are present, each coupled to its own computer graphics pipeline. Each slave has a synchronization input and a synchronization output. The synchronization inputs and outputs are coupled in series to form a daisy chain. In the latter configuration, the system is operable to cause all of the slaves to operate in synchrony with the master.

In another aspect, the invention includes a method for substantially synchronizing the vertical refresh cycles in, and the display of left and right channels by, first and second computer graphics display systems in a multi-display stereoscopic computer graphics system. The method includes the steps of: changing the state of a synchronization signal synchronously with vertical refresh activity in the first computer graphics display system; displaying a predetermined one of the left and right channels in the first computer graphics display system responsive to the state of the synchronization signal; communicating the synchronization signal from the first to the second computer graphics display systems; beginning vertical retrace in the second computer graphics display system when the synchronization signal changes states; and displaying a predetermined one of the left and right channels in the second computer graphics display system responsive to the state of the synchronization signal.

In yet another aspect, the invention includes a method of substantially synchronizing the vertical refresh cycles of first and second computer graphics display systems. The method includes the steps of: displaying a first frame in the first computer graphics display system; displaying a second frame in the second computer graphics display system; halting the video timing generator in the second computer graphics display system at a time during vertical front porch in the second computer graphics display system; causing a transition on a synchronization signal synchronously with the beginning of vertical front porch in the first computer graphics display system; waiting a predetermined time in the second computer graphics display system, after halting the video timing generator, for a transition of the synchronization signal; and, if a transition of the synchronization signal occurs during the predetermined time, causing the second computer graphics display system to immediately enter vertical sync. In a further embodiment, if a transition of the synchronization signal does not occur during the predetermined time, the method includes causing the second computer graphics display system to enter vertical sync at the end of the predetermined time.

The invention also includes synchronization logic for use in a multi-display computer graphics system. The inventive synchronization logic includes external sync input/output circuitry having an external sync input and an external sync output; a video timing generator having a vertical refresh status output; and a state machine. In an embodiment, the vertical refresh status output indicates when the video timing generator is in the last line of vertical front porch. The state machine is operable (1) to halt the video timing generator responsive to the vertical refresh status output, (2) to sense transitions on the external sync input, and (3) to cause the vertical timing generator to enter vertical sync responsive to transitions sensed on the external sync input. In a further embodiment, the synchronization logic also includes a programmable master/slave indicator. In such an embodiment, the external sync input/output circuitry is responsive to the programmable master/slave indicator and is operable as follows: (1) when in master mode, the external sync output will be toggled whenever the video timing generator begins vertical front porch; and (2) when in slave mode, the external sync output follows the external sync input. In yet a further embodiment, the synchronization logic includes a time-out counter. In the latter embodiment, the state machine is operable to cause the vertical timing generator to enter vertical sync responsive to the expiration of the time-out counter.

FIG. 1 is a block diagram illustrating a prior art single-display computer graphics system.

FIG. 2 is a block diagram illustrating the logical organization of the prior art video controller to FIG. 1.

FIG. 3 is a timing diagram illustrating the vertical timing of the prior art CRT monitor of FIG. 1.

FIG. 4 is a timing diagram illustrating the horizontal timing of the prior art CRT monitor of FIG. 1.

FIG. 5 is a block diagram illustrating a multi-display stereoscopic computer graphics system according to a preferred embodiment of the invention.

FIG. 6 is a block diagram illustrating the sync logic of FIG. 5 in more detail.

FIG. 7 is a state diagram illustrating the preferred operation of the external sync state machine of FIG. 6.

FIG. 5 illustrates a multi-display stereoscopic computer graphics system 500 according to a preferred embodiment of the invention. The system includes a master display system 502 and a plurality of slave display systems 504, 506. Master display system 502 contains a master computer graphics pipeline 508. Each of the slave display systems contains a slave computer graphics pipeline indicated in the drawing as slave pipelines 0 through n. Master pipeline 508 and each of slave pipelines 0 through n may be conventional and may be implemented, for example, according to the computer graphics pipeline shown in FIG. 1 with the exception that each of the pipelines in FIG. 5 takes its horizontal and vertical timing inputs, as well as its left/right state input, from a synchronization system 510 as shown. Moreover, a configuration bus should be provided between each pipeline and its synchronization system 510 as shown. The configuration bus may be any conventional set of address, data and control lines suitable for setting and resetting bits in the control registers of synchronization system 510 as will be discussed in more detail below. Each synchronization system 510 contains sync logic 512. Each sync logic 512 has an external sync input "ext.sub.-- sync.sub.-- in" and an external sync output "ext.sub.-- sync.sub.-- out." The external sync inputs and outputs are connected in series, via conventional differential drivers 516 and receivers 514, beginning with master display system 502 and ending with slave display system 506.

In operation, master display system 502 runs free as if it were the only graphics pipeline in the multi-display system. It causes a transition on its ext.sub.-- sync.sub.-- out line every time it enters its vertical blank interval (the beginning of vertical front porch). Each of the slave display systems passes this synchronization signal to the next slave in daisy chain fashion. The synchronization signal is used in each slave in two ways: transitions on the synchronization signal indicate when the next vertical retrace will occur in the slave, and the state of the synchronization signal indicates to the slave which channel (left or right) to display during the next frame. Using the synchronization signal for both of these purposes provides the added advantage that, whenever the display of left versus right channels is switched, the switch always occurs during a vertical retrace. Because of variations in crystal clock frequencies, the frame rate for each display system will be slightly different. To compensate for this, time is added or subtracted from the last horizontal line of vertical front porch in each slave so that all systems enter vertical sync at nearly the same time. Specifically, each slave will enter vertical sync whenever it sees a transition on its ext.sub.-- sync.sub.-- in input. If a slave has already finished vertical front porch and has not yet seen a transition, then it will wait a predetermined amount of time at the end of vertical front porch. If it sees the transition during the waiting period, then it will immediately enter vertical sync by forcing a reset or load of the vertical sync counter in the video timing generator. If it does not see a transition before the end of the waiting period, then it will enter vertical sync anyway at the end of the waiting period. (The latter functionality is described in more detail below in connection with the discussion of FIG. 7. In effect, it prevents the entire multi-display system from halting in the event the daisy chain is broken for some reason.)

FIG. 6 is a block diagram illustrating the contents of sync logic 512 in more detail. It should be noted that the suffix ".sub.-- n" appears in signal names to denote "asserted low." In a preferred embodiment, all clock inputs are driven at one-fourth the rate of the dot clock. Sync logic 512 contains external sync state machine 600, video timing generator 602, control bit register 604 and time-out counter 606. Control bit register 604 contains two control bits: time-out.sub.-- enable and vtg.sub.-- SCR.sub.-- master.sub.-- n. The purpose of the time-out.sub.-- enable bit is to enable or disable the time-out functionality just described. The purpose of the vtg.sub.-- SCR.sub.-- master.sub.-- n bit is to indicate whether sync logic 512 should act as a master or as a slave. Sync logic 512 is configured to operate in slave mode when this bit is set high, and to operate in master mode when this bit is set low.

Slave Mode: When sync logic 512 is in slave mode, the output of latch 612 will follow input D1. Thus, in slave mode, sync logic 512 will pass a latched version of ext.sub.-- sync.sub.-- in to its ext.sub.-- sync.sub.-- out output via latch 612. The state of the output of latch 612 is also used as the left/right indicator bit. Whichever graphics pipeline is coupled to sync logic 512 uses the state of this bit to determine which channel (left or right) to display in the upcoming frame.

Master Mode: When sync logic 512 is in master mode, the output of latch 612 will follow input D0. D0, in turn, is coupled to the output of exclusive OR gate 614. The first input of exclusive OR gate 614 is taken from the output of latch 612. The other input of exclusive OR gate 614 is provided by AND gate 616. The non-inverted input of AND gate 616 is coupled to the output of latch 618, which takes its input from V.sub.-- BLANK.sub.-- n. The inverted input of AND gate 616 is coupled directly to V.sub.-- BLANK.sub.-- n. The output of AND gate 616 will go high for one clock period every time a high-to-low transition occurs on the V.sub.-- BLANK.sub.-- n signal (indicating that video timing generator 602 is entering vertical blank). The output of exclusive OR gate 614 will follow the last state of latch 612 whenever the output of AND gate 616 is low, but will toggle the last state of latch 612 whenever the output of AND gate 616 is high. Thus, when sync logic 512 is in master mode, it will cause a transition on ext.sub.-- sync.sub.-- out every time it enters vertical front porch. In an alternative embodiment, the input of latch 618 and the inverting input of AND gate 616 may be couple to VSYNC.sub.-- n instead of VBLANK.sub.-- n. In such an alternative embodiment, sync logic 512 (when in master mode) will cause a transition on ext.sub.-- sync.sub.-- out every time it begins a vertical retrace.

Table A below provides descriptions of the signals in FIG. 6 that have not yet been discussed.

Video timing generator 602 may be conventional except that it should be operable to stop counting whenever SyncTimingHold is asserted and to enter vertical sync immediately whenever SyncLoadHField is asserted. Also, video timing generator 602 should assert LastLineOfVFP when video timing generator 602 has entered the last line of vertical front porch. Control bit register may be a two-bit register writeable via configuration bus 620. Time-out counter 606 may be a conventional decrementing counter configured to load a predetermined value on reset. In a preferred embodiment, the predetermined value corresponds to the number of clocks (at the rate of one-fourth dot clock) required to count for two horizontal line intervals. Time-out counter 606 should assert SyncTimeOut.sub.-- n whenever the counter expires. Time-out counter 606 only counts when it is enabled. In the embodiment shown, time-out counter 606 is only enabled when SyncTimingHold is asserted and TimeOutEnable is also asserted. (See AND gate 622.) Time-out counter 606 reloads whenever SyncTimingHold is unasserted. (See inverter 624.) Latches 608 and 610 are provided so that external sync state machine 600 can detect a transition on the ext.sub.-- sync.sub.-- in input.

The operation of external sync state machine 600 will now be described with reference to the state diagram of FIG. 7. Assume operation begins at state S0. If sync logic 512 is in master mode, then external sync state machine 600 will remain in state S0 indefinitely, during which state both SyncTimingHold and SyncLoadHField are unasserted. The result of this state is that external sync state machine 600 will not interfere with the normal free-running operation of video timing generator 602. If sync logic 512 is in slave mode (if vtg.sub.-- SCR.sub.-- master.sub.-- n is high), then external sync state machine 600 will transition from state S0 to state S1. In state S1, the state machine waits for LastLineOfVFP to become asserted. While it waits, it still does not interfere with the normal operation of video timing generator 602 because both SyncTimingHold and SyncLoadHField are still unasserted. Once video timing generator 602 has entered the last line of vertical front porch, as indicated by an assertion of LastLineOfVFP, the state machine transitions to state S2, where it waits for a transition on the ext.sub.-- sync.sub.-- in line. While it waits for this transition, it halts video timing generator 602 by asserting SyncTimingHold. If a transition occurs on ext.sub.-- sync.sub.-- in before time-out counter 606 expires, then the state machine transitions to state S3, at which time it unasserts SyncTimingHold and asserts SyncLoadHField. The result of state S3 is that video timing generator 602 enters vertical sync immediately. From state S3, operation always resumes at state S1. If, on the other hand, time-out counter 606 expires in state S2 before a transition is detected on ext.sub.-- sync.sub.-- in, then the state machine transitions from state S2 to state S0. The result is that video timing generator 602 is once again allowed to continue running normally. (If sync logic 512 is configured as a slave, then external sync state machine 600 will enter state S1 again immediately after state S0, where it will once again try to synchronize itself with the ext.sub.-- sync.sub.-- in signal. Alternatively, circuitry may be provided to automatically reset the master/slave bit in control bit register 604 whenever a time-out occurs in state S2 so that sync logic 512 will then begin operating as a master.) If sync logic 512 is reconfigured to act as a master at any time while the state machine is in states S1 or S2, then the state machine will transition immediately to state S0, where it will remain until sync logic 512 is once again configured as a slave.

Additional flexibility may be achieved by adding control bits and circuitry to optionally invert the state of the ext.sub.-- sync.sub.-- in input in each slave, or to determine in each slave which assertion level of the left/right stereo state bit corresponds to the left or right channels.

While the invention has been described in detail in relation to a particular embodiment, it will be obvious to those skilled in the art that many modifications can be made to the described embodiment without departing from the spirit and scope of the invention. For example, the invention may be used with fill-screen stereo applications as well as with stereo-in-a-window applications. Moreover, the signal assertion levels described herein, and the type of video timing signals described herein, are intended to be illustrative only and are not intended to limit the scope of the invention. Rather, obvious adaptations and modifications of all of the above are intended to remain within the scope of the following claims.