Highly Linear Transconductance Circuit and Filter Using Same

This invention relates generally to transconductance circuits and more particularly to highly linear transconductance circuits and filters using these transconductance circuits.

A transconductance circuit is a practical realization of a voltage-controlled current source. Transconductance circuits find application in active filters, gyrators, oscillators and impedance transformers. Linearity is one parameter affecting transconductance circuit utility, because nonlinearities give rise to undesirable effects such as distortion.

U.S. Pat. No. 5,576,646, entitled "Transconductance Circuit With High-Linearity Double Input And Active Filter Thereof", issued to F. Rezzi et al., describes one solution to many of these problems. FIG. 1 is a simplified schematic diagram of a linearized transconductance circuit 10 taught by Rezzi et al., in accordance with the prior art. The transconductance circuit 10 includes first and second MOS FETs 12 and 14, having their sources coupled together at a first node 16, their drains coupled together at a second node 18 and their gates each coupled to one of inputs 20 and 22. The voltage at the first node 16 is a constant voltage and may be ground. A bipolar transistor 24 has an emitter coupled to the second node 18, a base coupled to a low impedance voltage source V.sub.DC that provides a constant voltage and a collector coupled to a constant current source 26 and to an output 28.

The transconductance circuit 10 uses the fact that a forward-biased emitter-base junction manifests a voltage that is well approximated by a piecewise linear model that assumes zero conduction below a threshold base-emitter voltage V.sub.BE of 0.7 volts, and that assumes a constant base-emitter voltage V.sub.BE of 0.7 volts after the base begins to conduct current. When this approximation is applied to the transistor 24, the drain-source voltage V.sub.DS of the MOS FETs 12 and 14 is approximated as V.sub.DS =V.sub.DC -0.7 volts-V.sub.NODE 16, where V.sub.DC represents a voltage from the source V.sub.DC and V.sub.NODE 16 represents the voltage at the node 16. As a result, the drain-source voltage V.sub.DS of the MOS FETs 12 and 14 is relatively constant, even with changes in operating current, reducing distortion effects due to variation in characteristics of the MOS FETs 12 and 14 with changing drain-source voltage V.sub.DS.

However, the emitter-base junction voltage V.sub.BE of the transistor 24 corresponds to the voltage drop across a forward-biased diode and is actually given as:

where V.sub.TH represents a temperature-dependent variable, I.sub.o represents a constant that is a function of transistor (or diode) material and geometry and I.sub.C represents collector (or diode) current. Base-emitter voltage V.sub.BE variations, due to changes in collector current, give rise to drain-source voltage V.sub.DS variations for the FETs 12 and 14, and result in the dominant nonlinearities encountered with the transconductance circuit 10 of FIG. 1.

There is therefore a need for improved linearization in transimpedance circuits for use in active filters and other types of circuits. In one aspect, the present invention provides a transconductance building block that includes a terminal for providing a first constant voltage, a constant current source and an output coupled to one terminal of the constant current source. A first transistor has a collector coupled to the output, a base and an emitter. A diode has a cathode coupled to the constant voltage terminal and an anode coupled to the base of the first transistor. A bias current generator provides a current to the diode. A second transistor has a gate coupled to a signal input, a source coupled to a second constant voltage and a drain coupled to the emitter.

In one aspect, the bias current generator of the present invention provides a current to the diode to maintain a drain-source voltage of the second transistor at a constant value. In one aspect, the bias current generator is a constant current source. As a result of the constant drain-source voltage, nonlinearities associated with drain-source voltage variation in the second transistor are reduced, and the transconductance circuit has reduced nonlinearities and improved dynamic range.

In another aspect, the bias current generator of the present invention includes a current mirror circuit having an input and an output. A current associated with the current mirror output is proportional to, and may be equal to, a current at the current mirror input. A first transistor has a collector coupled to the output, a base and an emitter. A diode has a cathode coupled to the constant voltage terminal and an anode coupled to the base of the first transistor. A bias current generator provides a current to the diode. A second transistor has a gate coupled to a signal input, a source coupled to a second constant voltage and a drain coupled to the emitter. The current mirror input is coupled to another circuit including a third transistor that is analogous to the first transistor, but which may be scaled, i.e., be geometrically quite similar but with features having sizes that are proportional to sizes of comparable features in the first transistor. The third transistor has a base that is coupled to the base of the first transistor and to the anode of the diode. A fourth transistor has a drain that is coupled to an emitter of the third transistor, a gate that is coupled to the gate of the second transistor and a source that is coupled to the source of the second transistor. The current mirror and the third and fourth transistors collectively require greater area for implementation on an integrated circuit than a constant current source, but also provide further reduction in nonlinearities. The third and fourth transistors may be scaled versions of the first and second transistors, and the current mirror can be scaled to ratio the input and output currents appropriately.

FIG. 1 is a simplified schematic diagram of a linearized transconductance circuit, in accordance with the prior art.

FIG. 2 is a simplified schematic diagram of a linearized transconductance circuit, in accordance with an embodiment of the present invention.

FIG. 3 is a simplified schematic diagram of a linearized dual-input transconductance circuit, in accordance with an embodiment of the present invention.

FIGS. 4A, 4B and 4C are simplified schematic diagrams of a linearized transconductance circuit, in accordance with alternative embodiments of the present invention.

FIG. 5 is a simplified schematic diagram of a linearized transconductance circuit, in accordance with an embodiment of the present invention.

FIG. 6 is a simplified schematic diagram of a filter section using the transconductance circuit of FIGS. 2, 4 or 5, in accordance with an embodiment of the present invention.

FIG. 7 is a simplified schematic diagram of a filter section using the transconductance circuit of FIG. 3, in accordance with an embodiment of the present invention.

FIG. 2 is a simplified schematic diagram of a linearized transconductance circuit 30, in accordance with an embodiment of the present invention. The transconductance circuit 30 includes a NMOS FET 32 having a source coupled to a first node 34, a gate 32 coupled to an input 36 and a drain coupled to a second node 38. In one embodiment, the first node 34 is coupled to ground. A low impedance, constant voltage source V.sub.DC is coupled to a cathode of a diode. In one embodiment, the diode is realized as a diode-connected transistor 40, with the cathode corresponding to an emitter of the transistor 40. The transistor 40 has a base that is coupled a collector of the transistor 40, forming an anode of the diode, and both are coupled to a third node 42. A bias current element 44 is coupled to the third node 42, along with a control terminal of a transistor 46. The transistor 46 has a current-carrying electrode coupled to the second node 38. Another current-carrying electrode of the transistor 46 is coupled to an output 48 and to a constant current source 50. The bias current element 44 is a constant current source in one embodiment of the present invention. In one embodiment, the transistor 46 is a bipolar transistor having a base coupled to the third node 42, coupled to the second node 38 and a collector coupled to the output 48.

When input signals coupled to the gate of the NMOS FET 32 give rise to variations in a drain-source current IDS in the NMOS FET 32, variations in emitter current occur in the transistor 46, much as was the case for the transistor 24 of FIG. 1. However, in the circuit 30, V.sub.DC is coupled to the base of the transistor 46 through another forward-biased diode 40, such as the base-emitter junction associated with the diode-connected transistor 40.

Changing the emitter current through the transistor 46 by a small amount A causes the base-emitter voltage of the transistor 46 to change by some smaller amount, in accordance with Eq. 1. Since the base current through the transistor 46 is very small compared to the constant current from the constant-current source 44, and since V.sub.DC is fixed, the current through the emitter-base junction of the transistor 40 is relatively unchanged and the emitter-base voltage V.sub.BE of the transistor 46 has to remain constant. Further, process or temperature variations that affect one of the transistors 40 and 46 are likely to cause similar changes in the other of the transistors 40 and 46. As a result, the drain-source voltage V.sub.DS of the NMOS FET 32 is fixed, and any V.sub.BE variations due to currents in the transistors 40 and 46 cancel out.

FIG. 3 is a simplified schematic diagram of a linearized dual-input transconductance circuit 52, in accordance with an embodiment of the present invention. Many of the components used in the embodiment of FIG. 3 are identical to components used in the embodiment of the transconductance circuit 30 of FIG. 2. Therefore, in the interest of brevity, these components have been provided with the same reference numerals, and an explanation of them will not be repeated.

The circuit 52 is similar to the circuit 30 of FIG. 2, but includes an additional NMOS FET 54 having a source and drain coupled to the source and drain of the NMOS FET 32 and having a gate that is coupled to a second input 56. As a result, the circuit 52 can accept two input signals having a phase shift between them and provide a linearized transconductance function, in a fashion similar to that described for the circuit illustrated in FIG. 2 of U.S. Pat. No. 5,576,646.

In the circuits 30 and 52 of FIGS. 2 and 3, the current gain .beta. of the transistor 46 is high. In one embodiment, the current gain .beta. of the transistor 46 is greater than 100. As a result, almost all of the current from the constant current source 44 goes through the transistor 40, forcing the voltage at the node 42 to remain constant and thereby keeping the voltage at the node 38 constant.

FIG. 4A is a simplified schematic diagram of a linearized transconductance circuit 60, in accordance with an embodiment of the present invention. Instead of the bias current element 44 of FIGS. 2 and 3, a bias generator 64 is used.

In one embodiment, the bias generator 64 includes a transistor 66 having a source coupled to the node 34, a gate coupled to the input 36 and a drain that is coupled to an emitter of a transistor 68. The transistor 68 has a base that is coupled to the node 42 and a collector that is coupled to an input of a current mirror 70. An output of the current mirror 70 is coupled to the node 42.

In one embodiment, the current mirror 70 includes a PMOS FET 72 having a drain and gate coupled to the input of the current mirror 70 and a source coupled to a positive voltage supply V+. A PMOS FET 74 has a source and a gate that are coupled to the source and gate of the PMOS FET 72 and has a drain that is coupled to the node 42. It will be appreciated that the current mirror circuit 70 may be formed using other types of transistors, including other types of FETs or bipolar transistors, and other types of known transistors or transistors that may be developed later.

In one embodiment, the transistors 32 and 66 match each other, the transistors 40, 46 and 68 match each other and the transistor 74 has a size that is equal to that of the transistor 72. In other words, a current at the output of the current mirror 70 is equal to the current that is present at the input. The base currents to the transistors 68 and 46 are negligibly small compared to the emitter current of the transistor 40. In part, this is due to the high current gain of the transistors 68 and 46. This allows the current mirror circuit 64 to supply base currents to all three transistors 46, 40 and 68, based on the collector current of the transistor 68. In this embodiment, current through the transistor 68 matches current through the transistor 46, and this is mirrored through the current mirror 70. As a result, current through the transistor 40 matches current through the transistor 46, resulting in matching base-emitter voltages for the transistors 40 and 46, and the drain-source voltage of the NMOS FET 32 is maintained at the voltage of the constant voltage supply V.sub.DC.

In another embodiment, various transistors in the circuit 60 are scaled to reduce total current drain and thereby reduce power consumption. Reduced power consumption is of particular concern for handheld or portable equipment, such as cellular telephones, that may use the circuits 30 or 60. In this embodiment, the transistors 66, 72 or 74 may be reduced in scale by a factor of ten or more. Alternatively, the transistors 40 or 74, or both, could be reduced in scale by a factor "m" of ten or more. These embodiments may result in DC errors that may be largely ignored with respect to the AC or high frequency performance of the circuit 60. Transistors in the circuits 30 and 52 may be similarly scaled.

In another embodiment, the transistors 66, 68 and 40 could be reduced in scale by some factor "m" to save power. The factor "m" may be ten or more. As a result, the base-emitter voltage of the transistor 40 tracks the base-emitter voltage of the transistor 46, and the voltage at the second node 38 remains essentially constant at the value V.sub.DC. This embodiment reduces the current through the circuit 60 by almost two-thirds compared to the embodiment that employs no device scaling. Because the voltage at node 42 is V.sub.BE greater than V.sub.DC, if the area and the current of the diode 40 are both reduced by a factor "m," the voltage at the node 42 will be the same as without scaling.

It will be appreciated that the circuit 52 of FIG. 3 may employ the bias generator 64 of FIG. 4A in the place of the constant current source 44. In general, the circuits 30 and 52 may not provide as great a linearity as the circuit 60 of FIG. 4A, however, the constant current source 44 of FIGS. 2 and 3 may be realized in much more compact form than is the case for the bias generator 64 of FIG. 4A. FIG. 4B is similar in structure and operation of 4A, but MOS transistors are used throughout the circuit.

FIG. 4C is similar to 4A and 4B with the use of an additional transistor 57 having one terminal coupled to the voltage supply and another terminal connected to the base of transistor 46, node 42. The transistor 57 has its gate coupled also to the collector of transistor 49. Transistor 49 has its base coupled in common with the base of 46 and 68.

A circuit using transistor 57 has the advantage that it will reduce any error associated with the finite control terminal current of transistors 46 and 68. A diode or diode connected device, 40 is not required. Of course, the transistor 57, or its equivalent could also be used in the all MOS embodiment of FIG. 4B.

FIG. 5 is a simplified schematic diagram of a linearized transconductance circuit 80, in accordance with an embodiment of the present invention. The circuit 80 uses the constant current source 44 of FIGS. 2 and 3 or the bias generator 64 of FIG. 4A as a bias source 81, but the transistor 46 of FIGS. 2-4 is replaced by a modified Darlington pair 82 and the transistor 40 may similarly be a modified Darlington pair 83.

The modified Darlington pair 82 includes one transistor 84 having an emitter coupled to the node 38 and a base coupled to an emitter of another transistor 86 and to a current source 91. A base of the transistor 86 is coupled to the node 42, and collectors of both the transistors 84 and 86 are coupled to the output 48 and to the constant current source 50. The pair 83 includes a first transistor 87, a current source 89 and a second transistor 85 connected as shown in FIG. 5.

In one embodiment, the Darlington pair 82 has a current gain .beta. of 10,000 or more. As a result, the assumption that the base current of the transistor 46 of FIGS. 2 through 4A, corresponding to the modified Darlington pair 82, is negligible compared to the current through the transistor 40, is improved, and the drain-source voltage V.sub.DS on the MOS FET 32 is held constant. The circuit 80 optionally includes the FET 56 of FIG. 3. The circuit 80 also allows scaling of elements, as discussed above with reference to FIG. 4A.

The circuits 30, 52, 60 and 80 of FIGS. 2, 3, 4A-4C and 5 may be realized as monolithic integrated circuits. In some embodiments, the circuits 30, 52, 60 and 80 may be realized as BiCMOS integrated circuits. It will be appreciated that while the circuits 30, 52, 60 and 80 have been described as employing specific transistor types (e.g., NMOS FETs, PMOS FETs and bipolar junction transistors), other types of transistors may be substituted for those shown as is known in the art or as may be developed in the art.

FIG. 6 is a simplified schematic diagram of a first order active filter 90 using two of the transconductance circuits 30, 60 or 80 of FIGS. 2, 4 or 5, respectively, coupled in series, in accordance with an embodiment of the present invention. That is, an output 92 of a first transconductance circuit 94 is coupled to an input 95 of a second transconductance circuit 96. A capacitor 97 is coupled from the output 92 of the first transconductance circuit 94 to ground and a feedback network 98 is coupled from an output 99 of the filter 90 to the input 95 of the second transconductance circuit 96.

The outputs 92 and 99 correspond to the output 48 of the circuits of FIGS. 2, 4 and 5, and the input 95 corresponds to the input 36. The circuits 94 and 96 each correspond to any of the circuits 30, 60 or 80.

FIG. 7 is a simplified schematic diagram of a filter 100 using the transconductance circuit 52 of FIG. 3, in accordance with an embodiment of the present invention. The filter 100 includes a first input 102 that acts as an input, a second input 104 that is coupled to a feedback network 105 and an output 106 that is coupled to a capacitor 108 and to the feedback network. The first input 102 corresponds to the input 36, the second input corresponds to the second input 56 and the output 106 corresponds to the output 48 of FIG. 3. It will be appreciated that the filter 100 may be embodied with the Darlington pair 82 of FIG. 5 substituted for the transistor 46, and that the bias generator 64 of FIG. 4A maybe substituted for the bias current element 44 of FIG. 3.

The circuits 90 and 100 of FIGS. 6 and 7 realize transconductance building blocks that are used to provide filtering functions as described in U.S. Pat. No. 5,576,646. The circuits 90 and 100 also can be formed using a conventional BiCMOS process.

It will be further appreciated that a composite filter function may be realized by combining multiple examples of the filters 90 and 100 of FIGS. 6 and 7 in cascade together with feedback loops as appropriate. Such filters find application as monolithic frequency selection components in a variety of host devices for applications such as portable telephones. These filters provide size and weight advantages in such applications, especially when combined with other components used in the host device to form a single integrated circuit.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.