System and Method for Bit Interleaving of Full-Rate Speech Data

1. Field of the Invention

The present invention relates to methods of interleaving bits for coding, transmission, or storage, and more specifically to implementations of the bit re-ordering table for full-rate speech, Table 1 in GSM 05.03.

2. Description of Related Art

A method for encoding full rate speech is specified in the Global System for Mobile Communications' technical specification 05.03 (GSM 05.03) "Digital cellular telecommunications system (Phase 2+); Channel coding" version 5.1.0, May 1996. This publication is hereby incorporated by reference as though completely set forth herein.

The encoding method includes an interleaving process which is carried out in order to combat the burst errors that occur due to the mobile channel. Interleaving helps to separate out the individual errors within any error bursts and thereby effectively randomize the bit errors that are present. Then it is the job of a random error correcting code such as a convolutional code to correct as many of the errors as possible. The interleaver operates to reorder and spread bits from forward error correction (FEC) coded frames into data blocks for time division multiple access (TDMA) data bursts.

Prior art interleaving is performed by taking a single, current speech frame and distributing the bits throughout eight data blocks. Consequently, this prior art method requires that eight data blocks be simultaneously maintained in memory while speech frame bits are distributed among them.

The present invention provides a memory-efficient system and method for generating data blocks "on demand" for TDMA data bursts. This system and method feature a novel approach which treats the problem not as one of having one speech frame comprising a plurality of bits to encode and then for each bit finding the destination in one of a plurality of data blocks for TDMA data bursts, but rather the reverse, i.e. to consider each TDMA burst individially and then to find in each of a plurality of speech frames the source bits to be used. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.

In a preferred embodiment, the present invention comprises a method for bit reordering and frame interleaving for full rate speech in a GSM system. The method includes receiving two frames of forward error correction coded speech data and storing each frame in a separate buffer. The method also includes transferring bits from the buffers to a TDMA block. Each bit transfer includes determining the base address of one of the buffers, calculating a word offset within the selected buffer, calculating a bit offset within the selected word, and transferring the selected bit to a bit position in the TDMA block.

Objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

FIG. 1 is a GSM handset having a transmitter module according to present invention;

FIG. 2 is a functional block diagram of the transmitter module;

FIG. 3 is a method for bit interleaving;

FIG. 4 is a data block illustrating the bit distribution from FEC coded frames (N-1) and N;

FIG. 5 is a data block illustrating the bit distribution from FEC coded frames N and (N+1);

FIG. 6 is a table summarizing how the frame bits from the FEC coded frames are distributed according to burst number;

FIG. 7 is a tabulation of the source bit position as a function of burst number and destination bit position;

FIG. 8 is a table summarizing initial values for the source bit position function;

FIG. 9 is a flowchart of a method for implementing the bit position generation function;

FIG. 10 is a figure illustrating the evolution of the current frame buffer and previous frame buffer locations;

FIG. 11 is a schematic illustration of a method for generating word addresses in the frame buffers according to the present invention;

FIG. 12 is a schematic illustration of a method for generating bit position information in the frame buffers according to the present invention;

FIG. 13 illustrates a frame buffer;

FIG. 14 illustrates a method for obtaining a word offset and a bit offset from the binary representation of the bit position;

FIG. 15 is a schematic illustration of a module for generating data blocks of reordered bits from FEC coded frames according to the present invention;

FIG. 16 is a primitive state transition diagram illustrating the initiation and conclusion of the hardware based reordering and interleaving operations;

FIG. 17 illustrates the desired initialization of the bit position counter; and

FIG. 18 is a primitive state transition diagram illustrating a method for generating the initialization of the bit position counter and the initialization of the base address switch.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

Turning now to FIG. 1, a GSM handset 10 is shown. Handset 10 has a transmitter module for converting information bits, e.g. compressed speech data, into a transmitted signal. FIG. 2 shows a functional block diagram of the transmitter module. The stream of information bits is error correction encoded into frames in block 22. The frames are sent to an interleaver module 24, which operates to reorder the bits and interleave the frames into data blocks for TDMA data bursts. The data blocks are encrypted in block 26, then in block 28 the encrypted blocks are incorporated into TDMA bursts. The TDMA bursts are multiplexed, then forwarded to block 30 for modulation. Finally, the modulated signal is transmitted in block 32.

The interleaver module 24 receives a sequence of forward error correction (FEC) coded frames of full-rate speech data. Each frame has 456 bits which are to be reordered and spread out over eight data blocks for transmission. The data blocks each have 114 bits which are provided by the current and previous frames. Hence the mapping from frames to blocks occurs on two levels, a bit level and a frame level.

According to the present invention, the bit interleaving is called "bit reordering" in the GSM specification, however it is, nonetheless, interleaving on a bit level. The frame interleaving involves the interleaving of speech data from consecutive speech frames. This helps to spread out any burst errors over two independently FEC coded speech frames, which is better than spreading the same number of bit errors out over one FEC coded speech frame as would be the case if frame interleaving did not occur.

The interleaving scheme may be described using the equation shown below:

where i(B,j) is the j.sup.th bit in the B.sup.th block and the source bit, c(n(B,j), k(B,j)), is the k(B,j).sup.th bit in the n(B,j).sup.th FEC coded speech frame. The variables k and n are stated as functions of B and j because it is intended that B and j be the independent variables in the iteration of this interleaving scheme. This is to be contrasted with the method described in the GSM specification, where n and k are the independent variables. The advantages of this approach will be described further below. The function n(B,j) is used because the source bit can be from either the (N-1)th or the Nth FEC coded speech frame, depending on B and j. The position of the actual source bit is denoted by k(B,j) and is also a function of B and j.

FIG. 3 illustrates the new method for interleaving. In steps 40 and 42, two speech frames are received, each having bits to be intereleaved to form a data block. In step 43, the TDMA burst number is determined, and in step 44, an initial location in the speech frames is determined accordingly. In step 46, a bit is transferred from this location to the first bit position in the data block. A test in step 48 checks to determine if a new speech frame is needed, and if not, in step 50 a source location is determined for the subsequent bit position in the data block, and a loop occurs until all the bit positions in the data block have had source locations determined and a bit transferred from the source location to the associated bit positions in the data block. If a new frame is required, step 42 is performed to receive a new speech frame.

This reordering/interleaving process is different from that given in the GSM specification, although the result is not. In the GSM specification, a sequential, step-by-step approach is taken to distribute the source bits of a given frame throughout eight data blocks. In the current approach, the reordering and interleaving algorithm or method is considered by taking the final result, i.e. the interleaved bits which form a given data block, and looking backwards to determine the source, i.e. the uninterleaved FEC coded bits. This results in the algorithmic relationship shown above.

The following two sections better explain the functions n(B,j) and k(B,j). Each section describes the various factors that contribute to the nature of the two functions. The final section presents a hardware model implementation of the reordering/interleaving algorithm.

Explanation of n(B,j)

The function n(B,j) determines which FEC coded speech frame to use as the source of the bit to be interleaved, and it depends on the data block number B and the bit position, j, in the data block. The transmission of FEC coded speech frames is spread out over eight consecutive TDMA bursts (one data block per burst). This means that if the transmission of the N.sup.th FEC coded speech frame begins at burst B=B.sub.0 then the bursts B=B.sub.0, B.sub.0 +1, B.sub.0 +2, B.sub.0 +3, B.sub.0 +4, B.sub.0 +5, B.sub.0 +6 and B.sub.0 +7 will all contain some bits from the N.sup.th FEC coded speech frame. Further, due to the frame level interleaving, the first four data blocks, B.sub.0, B.sub.0 +1, B.sub.0 +2 and B.sub.0 +3, contain bits from the (N-1).sup.th and the N.sup.th FEC coded speech frames while the last four data blocks, B.sub.0 +4, B.sub.0 +5, B.sub.0 +6 and B.sub.0 +7, will contain bits from the N.sup.th and the (N+1) FEC coded speech frames.

After deciding upon which two FEC coded speech frames are to be used in a particular data block, it remains to be determined which of the two frames are to be used as the source for a particular bit within the data block. There is an underlying rule that may be inferred from the GSM interleaving specification--the most recent FEC coded speech frame is used as the source for the even bits of the TDMA burst. This is why there is a j dependency in n(B,j).

FIGS. 4 and 5 illustrate how bits from two speech frames are interleaved in a data block for a TDMA data burst. With the above rule in mind it is clear that the first four data blocks will use bits from frame N for even values of the bit position j and bits from frame (N-1) for odd values of the bit position j. FIG. 4 shows a data block 200 whose even bit positions (e.g. positions 0, 2, 4) have values drawn from frame N and whose odd bit positions (e.g. positions 7, 9, 11) have values drawn from frame (N-1). After the first four data blocks, the frame (N-1) has been transmitted in full and new FEC coded speech frame (N+1) becomes available for interleaving. As the (N+1).sup.th frame is newer than the N.sup.th frame, bits from the (N+1)th frames are now mapped to the even position of the next four data blocks and bits from the Nth frame are now mapped into the odd positions. FIG. 5 shows a data block 202 whose even bit positions have values drawn from frame (N+1) and whose odd bit positions have values drawn from frame N.

This explains the dependence of n(B,j) on B and j. The table shown in FIG. 6 summarizes the dependence. The left column holds the burst number, the assumption is that the transmission of the N.sup.th FEC coded speech frame begins at the Both TDMA burst. The table shows which FEC coded speech frame to use as the source of the bit to be interleaved depending on the burst number B and the bit position j.

From the table it can be seen that for the first four TDMA bursts, frame N is used as the source for the even bits and frame (N-1) for the odd bits. Then for the next four TDMA bursts, frame (N+1) is used as the source for the even bits and frame N for the odd bits. Once the source frame has been established it remains to be determined which bit within that frame to select. This is where k(B,j) is used.

Explanation of k(B,j)

The function k(B,j) determines the position of the bit that is drawn from the n(B,j).sup.th FEC coded speech frame. This bit will then be interleaved to the j.sup.th position in the B.sup.th data block. k(B,j) depends on the TDMA burst number B and the bit position, j. The equation below shows a method that may be used to compute k(B,j)

The initial values of k(B,0) and k(B,1) are initialized depending on the value of B. The table in FIG. 7 shows the values of k(B,j). The values of bit position j and burst number B determine the entry in the table for a given k(B,j). As each FEC coded speech frame is spread out over eight TDMA bursts, there are eight columns of k(B,j) values. These eight columns are grouped into two groups, each group with four columns. The entries for the first four columns correspond to the even bit positions of a data block and those for the last four columns, the odd bit positions. The j values placed at the side of each group of four columns reflect this.

The initialization of k(B,0) and k(B,1) depends upon B, the TDMA burst for which the data is being interleaved. The initialization values are taken from the first row in of the table of FIG. 7, and are shown explicitly in the table of FIG. 8. Returning to FIG. 7, the jumble of values in the columns represents the bit reordering (equivalently bit interleaving) that is specified by the GSM specification. The frame interleaving occurs when, for example, the even positioned bits from the first column (column 0) for frame N are interspersed with the odd positioned bits from the fifth column (column 4) for frame (N-1). Although the bit reordering and the frame interleaving are defined separately in the GSM standard, they may be combined into one process. This is done in this implementation.

FIG. 9 shows a flowchart 600 illustrating a method for computing destination positions for a data reordering/interleaving process. It is a method that may be used to compute the source position of the next sample within a particular data block. As there is data from two speech frames in each data block, there are two pointers, one for each frame buffer. These pointers are actually offset from each other by 228. Both of the pointers may use the method shown in the flowchart to compute their next position.

The method begins with step 602 wherein k(B,j) is set to an initial value k which depends on the burst number B and first position j (which is 0 or 1). In step 604, the frame data located at this initial value is placed in the data block at position j, and j is incremented by 2. In step 606, k is incremented by 64. In steps 608 and 610, a modulo 456 operation is performed. In step 612, the frame data located at k is placed in the data block at position j and j is incremented by 2. If j is greater than 113, the method restarts with a new combination of burst number B and first position j. Otherwise, the method returns to step 606.

The use of circular buffers would allow this method to be performed without the expense of any overhead cycles. This may be achieved by virtue of an automatic post modify and modulo arithmetic that is carried out in the address generators. Careful initialization of all the address generation registers allows correct address generation with zero overhead.

However, the data retrieval from memory is complicated slightly because of the bit manipulations that are involved. The values generated by the method are bit positions and the bits that they address are packed in 16-bit words.

To summarize, the issues which must be addressed by a hardware implementation are: 1) generating the correct values of n(B,j), 2) generating the correct values of k(B,j), 3) fetching the bit determined by k(B,j), and 4) providing a hardware control function. These issues are addressed in the following sections.

Implementing n(B,j)

The function n(B,j) is used to determine which FEC speech frame is used as the source for the j.sup.th bit. The initialization of n(B,0) is the most important issue here. Since the source bits come from two consecutive FEC speech frames that are stored in separate buffers, it is important to determine which buffer to use as the source for the very first bit. After the source of the first bit has been established, the remaining bits are obtained by alternating between the two buffers.

The initialization of n(B,0) is determined from FIG. 6. In a hardware implementation with two buffers, an incoming FEC speech frame is placed into the "elder" of the two buffers. This is shown in FIG. 10. Buffers 702 and 704 alternate roles as the elder of the two buffers. Reading the diagram from the left, frame (N-1) is overwritten by frame (N+1) when it becomes available. Then frame N is replaced with frame (N+2) and so on. The blocks with thicker borders indicate the buffers that are the initial "values" of n(B,0). The TDMA burst number is used as a time index at the bottom of the diagram.

It can be seen that every four TDMA bursts a new FEC coded speech frame arrives. This means that every four TDMA bursts the initialization of n(B,0) will change. This "initialization" may be reduced to making sure that the buffer to be used as the source of the very first bit in the TDMA burst is the newest one. The circuit of FIG. 11 shows how this may be done. In address generator 800, switch 802 is toggled 804 between frame buffer base addresses 806 and 808 by bit clock 810. To the chosen base address, an offset 812 is added 814 to produce a word address 816 in the frame buffer.

By the nature of the interleaving process, once the last bit in a data block has been interleaved, switch 802 will point to the initial buffer. This is because an even number of bits are being interleaved. For the first four data blocks there need not be any modification to the switch position because the first bit in each of the four data blocks will come from the same initial FEC coded speech frame buffer. However, after a group of four data blocks has been completed it will become necessary to toggle switch 802 an extra time so that it points to the appropriate data buffer. This may be accounted for as part of a state-machine-based control function that controls the initialization of the hardware. This will be discussed further below.

As was described, the circuit shown in FIG. 11 is used to generate the address in data memory of the word that contains the desired bit to be interleaved. The address should be generated in advance of the actual fetch in order to avoid uncertainties in timing. Every time TDMA bit clock 810 makes a transition, a word will be fetched from the frame buffer memory based on an address that was calculated at the previous clock cycle. At the same time, switch 802 shown above will toggle from one position to the other so that the base address for the other buffer may be added to offset 812 which is the upper five bits from the new k(B,j) that is computed. This process creates the address in data memory that will be ready for the next clock cycle. Then the word will be fetched from memory and at the same time the next address will be computed. Implementing k(B,j) For the reordering/interleaving of full rate speech two counter-based registers are used to generate values for k(B,j). These are called "counter-based registers" because they have as their source a counter. FIG. 12 shows a a bit position generator 900 for generating two k values, k.sub.e (B,j') for even values of j and k.sub.o (B,j') for odd values of j. The definition of j' is [j/2], since now two bit position values will be generated for each value of j. In FIG. 12, counter 902 is initially provided with a value from the center column of the table in FIG. 8. Counter 902 then generates the source addresses of the bits for one block by latching the input value once every two cycles of TDMA bit clock 810. This is facilitated by clock signal 904, which is derived from TDMA bit clock 810. The output of counter 902 provides the k.sub.e (B,j') value, and it is also forwarded to modulo-456 adders 906 and 908. Adder 906 adds 228 modulo 456 to the output of counter 902, thereby determining the k.sub.o (B,j') value. Adder 908 adds 64 modulo 456 to the output of counter 902, thereby determining the next value of k.sub.e (B,j') to be latched by counter 902. The k.sub.e (B,j') register value is used to address words that are destined for the even bit positions and the k.sub.o (B,j') register value is used to address words that are destined for odd bit positions. Address generator 800 switches between each of these registers values as it fetches words from the two buffers. The switching between the two registers is controlled by the value of j.

Every time the counter is clocked the value k.sub.e (B,j'+1)=k.sub.e (B,j')+64 (mod 456) appears at the output. This new value may then be used to fetch the bit that will be placed into the even bit position in the interleaved bit stream. Since the source of the bit that will be placed into the next odd bit position differs from k.sub.e (B,j') by 228 the output of the k.sub.e (B,j) latch is also input to a combinational logic circuit that computes the desired bit position k.sub.o (B,j')=k.sub.e (B,j)+228 mod 456.

To avoid possible timing conflicts, care must be taken in integrating the k(B,j) generation block with the data memory address generation block. In order to compute the correct data memory address, it is important to have the appropriate value of k(B,j), i.e. k.sub.o (B,j') or k.sub.e (B,j'), prior to the fetch cycle.

Implementing the fetch circuitry

In a preferred embodiment, the input FEC coded speech frames are stored in a memory mapped space. The 456-bit frames are stored in buffers that are 29 words long, as illustrated by buffer 1000 in FIG. 13. Two of these buffers are used because the reordering/interleaving process requires data from two consecutive FEC coded speech frames. The bit position k(B,j), which is a number between 0 and 455, must therefore be converted to a word address and an intra-word bit position. The bit position k(B,j) may be represented using 9 bits as shown in FIG. 14. The word offset and bit offset (i.e. the intra-word bit position) can then be obtained by simply partitioning the binary representation of k(B,j) into two parts. The upper five bits are used as an index to the appropriate word in which the desired bit is located. This is why only the upper five bits of k(B,j) are used in the data memory address generation block 800. The lower four bits are used to select the desired bit within the word that is fetched. This bit is then placed in the j.sup.th position of the interleaved output buffer.

It should be noted here that if an encryption mask is to be used on the data block, the source bit may be XOR'd with the corresponding bit in the encryption mask as soon as it is fetched. This advantageously parallelizes the encryption and fetch operations to thereby gain a reduction in the data processing delay.

FIG. 15 shows a circuit to demonstrate how the described circuits may be integrated and the correct bit from data memory extracted for a given value of k(B,j). The upper five bits of the binary representation of k(B,j) provided by bit position generator 900 are used by a address generator 800 to generate the address in data memory of the desired word. The desired word will be in one of two frame buffers 1000. The lower four bits are used as input to a 16-to-1 MIX 1202. Thus, once the word has been fetched the desired bit is selected using the lower four bits of k(B,j).

In a preferred embodiment, the data memory is common with the rest of the system, and provisions must be made to ensure that there are no conflicts during the read from memory. This is preferably accomplished by configuring the data storage space so that it is write-only from the DSP or microcontroller host and read-only by this hardware.

Control Implementation

The registers and counters must be properly initialized and the various tasks, like address computation and word fetching, must be performed in a correct sequence. There are several tasks that must be performed by the control function, the most primitive of which is to know when to be in the processing state and when to be in idle.

This may be accomplished using a memory-mapped hardware register that may be accessed by a DSP or microcontroller host. This memory location will not only serve as the start-up indication but also as a valuable port through which modes of operation may be passed to the hardware. For example, the hardware system may be modified to support both full and half rate FEC speech reordering/interleaving. In this case, the start-up register will serve to pass the appropriate rate of operation to the hardware. FIG. 16 shows a state machine to illustrate. The bit interleaving hardware is initially in idle state 1302. Once a non-zero value has been detected, the hardware will enter processing state 1304 and perform the appropriate function and then reset the start-up register to zero as it returns to idle state 1302. This zeroing of the memory mapped register will be an indication to the host processor that the desired function has been completed.

Another important function of the controller is that of initialization. There are two hardware elements that must be initialized - the contents of the k(B,j) generator latch and the n(B,j) switch. The latch that is used to generate values for k(B,j) must be properly initialized in order to produce the correct output sequence. Every time a new data block is to be built the latch must be initialized according to k(B,0) column in the table of FIG. 8. This initialization will ensure that the correct sequence of bit positions is generated and hence the correct bits will be reordered and interleaved. FIG. 17 shows how the four initialization values may be used.

The initialization process may be accomplished by maintaining a two-bit counter that is incremented every time the hardware constructs a data block. FIG. 18 shows the state transition diagram of a two-bit counter. This counter may be used to index the four initialization values. Thus the next time the hardware is to be used, the correct initial value may be loaded into the k(B,j) latch.

This same two-bit counter may also be used to determine when to toggle the data memory base address (i.e. to toggle the n(B,j) switch 802). When incrementing the two-bit counter at the end of the hardware operation it is possible to note the 11 to 00 transition (i.e. the transition from state 3 to state 0) and to toggle the data memory base address, as shown in FIG. 18. This ensures that the correct base address will be used when fetching the very first bit in the next data block.

Conclusion

This document has described the implementation of a hardware based reordering/interleaving scheme for full rate speech traffic. This implementation may also be used for the interleaving of FACCH data without modification.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the method described herein may be entirely implemented by a DSP or microprocessor. It is intended that the following claims be interpreted to embrace all such variations and modifications.