Manufacturing Method of Semiconductor Device

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 7-168821 filed on Jul. 4, 1995, the contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention generally relates to a manufacturing method for a semiconductor device. More particularly, the present invention relates to a manufacturing method for a semiconductor device used as a power semiconductor device, e.g., a vertical MOSFET (metal oxide semiconductor field effect transistor) and an IGBT (insulated gate bipolar transistor), and can suitably be employed for a single unit power semiconductor device or a MOS-IC including such power semiconductor device.

2. Related Arts

As for a conventional semiconductor device which remarkably reduces the ON-resistance per area, a vertical type MOSFET having a concavity on the surface thereof and a channel region disposed at the sidewall surface of the concavity has been disclosed in the International Publication No. PCT

The concavity of the proposed device is fabricated by a combination of local oxidation of silicon (LOCOS) technique and chemically etching off the formed thick oxide film using wet etching. That is to say, before removing the thick oxide film, a body region and a source region for each cell are formed by using the thick oxide film as a double diffusion mask so as to self-align with the side of the thick oxide film, and then a gate insulating film and a gate electrode are formed in the concavity after removing the thick oxide film.

However, when actually manufacturing such vertical type MOSFET, following problems are raised. Unlike the conventional planar type MOS structure whose channel region is positioned after oxidizing and arranging the gate, as mentioned above, the channel region of the proposed vertical type device is firstly defined by the double diffusion, and secondly wet etching of the thick oxide film is performed to form the concavity, and then the surface of the concavity is oxidized to form the gate insulating film.

Accordingly, the by-product oxide layer, formed at the back surface side of the substrate simultaneously with forming oxide film such as LOCOS oxide film etc. on the substrate, is removed at the same time of wet etching the above-mentioned thick oxide film (LOCOS oxide film) so that the back surface of the substrate is exposed. At this point, since the back surface of the power semiconductor element substrate is highly doped regardless of the type of semiconductor element, during the subsequent gate oxidation step, impurities are vaporized and then scattered from the exposed back surface of the substrate and reintroduced to the substrate main surface where the channel region has been defined. This results in a fluctuation, or a drop, for example, of the carrier density of the channel region, affecting the electric characteristics of the element. More concretely, this problem causes the threshold voltage to be out of the design value, degrading the wafer uniformity in the threshold value, and causing withstand voltage failure between drain and source.

This kind of problems occurs not only to the vertical type MOSFET disclosed in the above-mentioned PCT WO93/03502, but also to the trench gate type vertical MOSFET having a trench formed by means of R.I.E. (reactive ion etching) technique. Namely, when trench forming, SiO.sub.2 is generally deposited as a trench mask on the substrate surface, and simultaneously by-product oxide film is deposited on the back surface of the substrate. Since this SiO.sub.2 of the back surface of the substrate is removed at the same time when removing the SiO.sub.2 as a trench mask after the trench is formed, the same problems as mentioned above is assumed to occur to the trench gate type vertical MOSFET.

In view of the above problems, it is a primary object of the present invention to provide a manufacturing method for a semiconductor device which can solve the problems of carrier density fluctuation due to the scattering of impurities from the back surface of the substrate in the step of heat treatment applied to the substrate after defining the channel region.

The manufacturing method according to the present invention comprises: defining a channel region by disposing, on a semiconductor substrate having a first conductivity type semiconductor layer of low impurity concentration on a main surface thereof, a second conductivity type body region and a first conductivity type source region; covering a back surface of the semiconductor substrate with masking material; forming a gate insulating film by oxidizing the surface of the channel region; and arranging a gate electrode in correspondence with the channel region with the gate insulating film interposed therebetween.

According to the above-mentioned manufacturing method, although the channel region is exposed during the gate oxidation, the high concentrated region of the back surface of the substrate is still covered by the masking material.

Therefore, by means of the masking material, the vaporization and scattering of the impurities from the back surface of the semiconductor substrate can be prevented, and the undesired fluctuation of the carrier density at the channel region due to the vaporization and scattering of the impurities can be also prevented. Hence the element characteristics can be prevented from being varied.

These and other objects, features and characteristics of the present invention will be appreciated from a study of the following detailed description, the appended claims, and drawings, all of which form a part of this application. In the drawings:

FIG. 1A is a plane view illustrating a part of the vertical type power MOSFET according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line 1B--1B of FIG. 1A;

FIGS. 2 through 9 are cross-sectional views illustrating the manufacturing processes of the important parts of the vertical type power MOSFET according to the embodiment of the present invention;

FIG. 10 is a cross-sectional view illustrating the gate oxidizing step consequent to the step illustrating in FIG. 9 based on the conventional manufacturing process of the vertical type power MOSFET; and

FIGS. 11 to 18 are a cross-sectional views illustrating the manufacturing processes of the important parts of the vertical type power MOSFET consequent to the step illustrating in FIG. 9 according to the embodiment of the present invention.

An embodiment according to the present invention will now be described referring to the appended drawings.

FIG. 1A is a plane view of a vertical type power MOSFET according to the embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line 1B--1B of FIG. 1A.

The main part (unit cell part) of the vertical type power MOSFET according to this embodiment is so constructed as illustrated in FIGS. 1A and 1B in which numerous unit cells 15 are laid out lengthwise and breadthwise at a pitch (unit cell dimension) of a.

In FIGS. 1A and 1B, a wafer 21 is composed of a semiconductor substrate 1 consisting of n.sup.+ -type silicon having an impurity concentration of approximately 10.sup.20 cm.sup.-3 and a thickness of 100-300 .mu.m, and an n.sup.- -type epitaxial layer 2 having an impurity concentration of approximately 10.sup.16 cm.sup.-3 and a thickness of approximately 7 .mu.m formed on semiconductor substrate 1, and as described above, numerous unit cells 15 are regularly laid out on the main surface of wafer 21.

On the main surface of wafer 21 is formed a local oxide film to a thickness of approximately 3 .mu.m to form a U-groove (i.e., concave structure) 50 at a pitch of the unit cell dimension a (=approximately 12 .mu.m) and by diffusion self-alignment using this oxide film as a double diffusion mask are formed a p-type body region 16 to a junction depth of approximately 3 .mu.m and an n.sup.+ -type source region 4 to a junction depth of approximately 1 .mu.m, whereby a channel 5 is defined on a sidewall part 51 of U-groove 50.

Incidentally, p-type body region 16 is set to a junction depth which does not permit p-type region 16 to be fractured due to breakdown at an edge part 12 on the bottom of U-groove 50. Furthermore, boron ions have been diffused into the central part of p-type body region 16 beforehand to deepen the junction depth in the central part of p-type region 16 down from the circumference, so that a breakdown can be caused when a high voltage is applied between the drain electrode and the source electrode.

After the double diffusion, the local oxide film, which is used for forming U-groove 50 as well as for the diffusion mask, is removed, a gate oxide film 8 is formed to a thickness of approximately 60 nm on the inner wall of U-groove 50 and on gate oxide film 8 are formed a gate electrode 9 with polysilicon to a thickness of approximately 400 nm and an interlayer insulating film 18 with borophosphosilicate glass (BPSG) to a thickness of approximately 1 .mu.m.

Furthermore, a p.sup.+ -type body contact region 17 is formed to a junction depth of approximately 0.5 .mu.m in the central part surface of p-type body region 16 and ohmic contact is made between a source electrode 19 formed on interlayer insulating film 18 and n.sup.+ -type source region 4 and p.sup.+ -type body contact region 17 through a contact hole. On the other hand, a drain electrode 20 is formed commonly on the back surface of semiconductor substrate 1 to make ohmic contact therewith.

Reference numeral 6 denotes an n.sup.- -type drain layer, and reference numeral 7 denotes JFET portion.

An example of the manufacturing method according to the present embodiment will now be described.

A wafer 21 is prepared in which, as illustrated in FIG. 2, an n.sup.- -type epitaxial layer 2 is formed by means of homo-epitaxial growth on the main surface of n.sup.+ -type silicon substrate 1. The thickness of epitaxial layer 2 is approximately 7 .mu.m and the impurity concentration thereof is approximately 10.sup.16 cm.sup.-3. A pad oxide film 60 is formed to a thickness of approximately 60 nm by thermally oxidizing the main surface of wafer 21 and simultaneously, an oxide film 601 is also formed on the back surface of semiconductor substrate 1.

Subsequently, a photoresist film 61 is deposited on pad oxide film 60 and photoresist film 61 is patterned to form a pattern opened in the central part of a region where a cell is to be formed by means of well-known photolithographic techniques. Then, boron ions (B.sup.+) are implanted into epitaxial layer 2 by using photoresist film 61 as a mask.

As illustrated in FIG. 3, after removing photoresist film 61, a p-type diffusion region 62 is formed to a junction depth of approximately 3 .mu.m by means of thermal diffusion. This p-type diffusion region 62 ultimately constitutes a part (deep well region) of p-type body region (described later) and plays a role of improving the surge resistance of the device by stably causing a breakdown at the bottom part of p-type diffusion region when a high voltage is applied to between the drain electrode and the source electrode.

A silicon nitride film 63 is deposited to a thickness of approximately 200 nm on the main surface of wafer 21 by means of CVD (Chemical Vapor Deposition) method, while a silicon nitride film 631 is formed on the back surface of semiconductor substrate. Then, silicon nitride film 63 is patterned to form a lattice-like open pattern opening at a pitch of a (dimension of unit cell 15). During the formation of this open pattern, mask-alignment is conducted so that the above p-type diffusion region 62 can be positioned in the central part of the pitch.

As illustrated in FIG. 4, pad oxide film 60 is then etched using silicon nitride film 63 as a mask. Following this, an initial groove 64 is formed by etching n.sup.- -type epitaxial layer 2 to a depth of 1.5 .mu.m. In the present embodiment, initial groove 64 is isotropically formed by means of chemical dry etching method.

Next, as illustrated in FIG. 5, the part of groove 64 is thermally oxidized using silicon nitride film 63 as an oxidation mask. This is an oxidation method applying the well known LOCOS (local oxidation of silicon) method. By this oxidation, a LOCOS oxide film 65 is formed on the surface of wafer 21, and concurrently the shape of a U-groove 50 (concave structure) is defined by erosion of the surface of n.sup.- -type epitaxial layer 2 due to the growth of LOCOS oxide film 65.

As shown in FIG. 6, silicon nitride film 63 is immersed in heated phosphoric acid solution or the like for wet-etching. Accordingly, silicon nitride film 631 on the back surface of semiconductor substrate is simultaneously removed. Then, boron ions are implanted through the thin pad oxide film 60 using LOCOS oxide film 65 as a diffusion mask. At this time, the boundary part between LOCOS oxide film 65 and pad oxide film 60 constitutes a self-alignment position to exactly define a region into which boron ions are implanted.

Then, as illustrated in FIG. 7, thermal diffusion is applied to diffuse the implanted boron ions into epitaxial layer 2 to a junction depth of approximately 3 .mu.m. As a result of this thermal diffusion, p-type diffusion region 62 previously formed in the process illustrated in FIG. 3 and the boron diffusion region (channel well region) into which boron ions have been implanted in the process illustrated in FIG. 6 are integrated into p-type body region 16, both ends of which are self-aligned and defined by the positions of the sidewalls of the U-groove 50.

Subsequently, as illustrated in FIG. 8, after forming a photoresist film 66 which is patterned so as to cover the central part of the surface of p-type body region 16 surrounded by LOCOS oxide film 65, phosphorous ions are implanted through thin pad oxide film 60 using photoresist film 66 and LOCOS oxide film 65 as a diffusion mask to form an n.sup.+ -type source region 4. In this process, like the process illustrated in FIG. 6 in which boron ions have been implanted, the boundary part between LOCOS oxide film 65 and pad oxide film 60 constitutes a self-alignment position, whereby the ion implantation region can exactly be defined.

The next process is, as illustrated in FIG. 9, to apply thermal diffusion to form n.sup.+ -type source region 4 of approximately 0.5.about.1 .mu.m in junction depth and define a channel 5 as well. The end surface being in contact with U-groove 50 in the region of n.sup.+ -type source region 4 is self-aligned and defined in the position of the sidewall of U-groove 50.

The processes illustrated in FIGS. 6 to 9 fix the junction depths and shapes of p-type body region 16 and n.sup.+ -type source region 4 and define the channel region.

According to the conventional manufacturing methods disclosed in the above International Publication No. PCT WO93/03502, LOCOS oxide film 65 is then removed by wet-etching so that inner wall 51 of U-groove 50 is exposed, whereupon as illustrated in FIG. 10, gate oxide film 8 is formed to a thickness of approximately 60 nm by thermal oxidation.

As mentioned above, when LOCOS oxide film 65 is removed by wet-etching, the oxide film 601 on the other main surface of semiconductor substrate 1, or on the back surface of the substrate, is simultaneously removed by etching so that the back surface of semiconductor substrate 1 is exposed. Therefore, there is a problem that the impurities which are vaporized from the exposed back surface of the semiconductor substrate 1 is introduced into the surface of semiconductor layer. Accordingly, when the vaporized impurities are introduced into channel 5 which is exposed after the removal of LOCOS oxide film 65, the acceptor density of channel 5 is compensated, resulting in a drop in carrier density of channel 5. This causes problems as influences on the electric characteristics of the element such as lowering of the threshold voltage unexpectedly lower than the predetermined value, degrading the wafer uniformity in the threshold voltage, and causing poor withstand voltage between the drain electrode and the source electrode. It is to be noted that reference numeral 671 in FIG. 10 denotes an oxide film grown at the same time of forming gate oxide film 8.

On the other hand, according to the manufacturing method of the invented embodiment, after the ion implantation using LOCOS oxide film 65 as a mask and thermal diffusion to form n.sup.+ -type source region 4 as illustrated in FIG. 9, polycrystalline silicon films 40 and 41 are intentionally formed to a thickness of 400 nm by means of CVD method as illustrated in FIG. 11, then polycrystalline silicon film 40 on the surface side of semiconductor layer 2 is selectively removed by R.I.E. (Reactive Ion Etching) method as illustrated in FIG. 12.

Next, as illustrated in FIG. 13, an inside wall 51 of U-groove 50 is exposed by removing LOCOS oxide film 65 by way of terminating the silicon surface with hydrogen within an aqueous solution 700 containing hydrofluoric acid and adjusted to an acidity/alkalinity of around pH5 with ammonium fluoride. At this point, since the back surface of wafer 21 is covered with polycrystalline silicon film 41, oxide film 601 remains unremoved.

After the completion of the above process, the wafer 21 is taken out of the aqueous solution and dries in a clean air.

Then, as illustrated in FIG. 14, a temporary oxide film 600 is formed on a side surface 51 of U-groove 50 of p-type body region 16 on which channel 5 is to be formed. By this thermal oxidation process, the flatness of the surface on which channel 5 is to be formed is improved in terms of atomic order. This thermal oxidation process is performed by slowly inserting a wafer boat holding a plural number of wafers 21 into an oxidation furnace which is maintained within the oxygen atmosphere at a temperature of approximately 1,000.degree. C.

Since the back surface of wafer 21 is covered with oxide film 601 and polycrystalline silicon film 41, the scattering of impurities within semiconductor substrate 1 of high impurity concentration to the outside of wafer 21 during the thermal oxidation process can be controlled. Therefore, channel 5 of any wafer in the oxidation furnace is prevented from being doped with impurities. Further, in the thermal oxidation process illustrated in FIG. 14, the surface of polycrystalline silicon film 41 is simultaneously oxidized to form an oxide film 602.

Then, temporary oxide film 600 is removed. The removal of this temporary oxide film 600 is also performed while terminating the exposed silicon surface with hydrogen within an aqueous solution containing hydrofluoric acid and adjusted to an acidity/alkalinity of around pH5 with ammonium fluoride. Inside wall 51 of U-groove 50 formed by this method is a good silicon surface with a high flatness and a few defects. In this process, oxide film 602 at the back surface of the wafer is also removed by etching, while oxide film 601 remains unremoved because oxide film 601 is covered by polycrystalline silicon film 41.

As illustrated in FIG. 15, a gate oxide film 8 is then formed to a thickness of approximately 60 nm on the side surface and bottom surface of U-groove 50 by thermal oxidation. This thermal oxidation process is performed similarly to the above described thermal oxidation process illustrated in FIG. 14.

In this thermal oxidation process, since the back surface of wafer 21 is covered with oxide film 601 and polycrystalline silicon film 41, the scattering of impurities within semiconductor substrate 1 to the outside of wafer 21 can be prevented, with the result that channel 5 of any wafer 21 in an oxidation furnace is prevented from being doped with impurities. Further, by this process, the surface of polycrystalline silicon film 41 is oxidized and an oxide film 671 is formed thereon. The reference numeral 67 denotes an oxide film grown at the wafer surface.

Now, as illustrated in FIG. 16, a polycrystalline silicon film is deposited on the main surface of wafer 21 to a thickness of approximately 400 nm. In the same way, a polycrystalline silicon film 91 is deposited on the back surface of wafer 21. Further, the polycrystalline silicon film on the main surface of wafer 21 is patterned so that a gate electrode 9 is formed.

As illustrated in FIG. 17, boron ions are implanted through oxide film 67 by using a patterned photoresist film 68 as a mask to form a p.sup.+ -type body contact region 17.

Following the above, as illustrated in FIG. 18, p.sup.+ -type body contact region 17 is formed to a junction depth of approximately 0.5 .mu.m by thermal diffusion.

Then, as illustrated in FIG. 1B, an interlayer insulating film 18 is formed with BPSG on the main surface of wafer 21 and contact holes a re made in parts of interlayer insulating film 18 to expose p.sup.+ -type body contact region 17 and n.sup.+ -type source region 4.

Furthermore, a source electrode 19 is formed with an aluminum film and ohmic contact is made between source electrode 19 and p.sup.+ -type body contact region 17 and n.sup.+ -type source region 4 through the contact hole. Subsequently, a passivation film (not illustrated) is formed with silicon nitride, etc. for protecting the aluminum film by a plasma enhanced CVD (chemical vapor deposition) technique or the like. The back surface of wafer 21 are ground by means of surface-grinding method or lapping method to remove the by-product layers, i.e., oxide film 601, polycrystalline silicon film 41, oxide film 671 and polycrystalline silicon film 9 1 so that semiconductor substrate 1 is exposed. Then, a drain electrode 20 with three layers of a Ti film, a Ni film and a Au film is formed on the as-ground back surface of semiconductor substrate 1, and an ohmic contact is made between drain electrode 20 and n.sup.+ -type semiconductor substrate 1 to obtain a structure illustrated in FIGS. 1A and 1B.

According to the present embodiment, since the back surface of semiconductor substrate 1 is covered with oxide film 601 and polycrystalline silicon film 41, the scattering of impurities within semiconductor substrate 1 to the outside can be suppressed in the thermal oxidation process.

In the present embodiment, polycrystalline silicon film 41 is used as a material film which is hardly removed when LOCOS oxide film 65 is removed. Silicon nitride may be used instead of polycrystalline silicon.

According to the present embodiment, phosphorous ions are implanted to form the n.sup.+ -type source region. In place of the phosphorous ions, antimony having lower vapor pressure can be used. In that case, during the thermal oxidation processes of FIGS. 14 and 15, the vaporization of the impurities from source region 4 can be restrained, and thus undesired introduction of impurities into channel 5 can be suppressed.

According to the above embodiment, the lattice-like pattern is used; however, a stripe-like pattern or the like may also be applied to the present invention.

In addition, the present invention may be applied to a so-called trench gate type vertical MOSFET. More specifically, the present invention may be applied to a MOSFET structure which is formed on a wafer composed of an n.sup.+ -type semiconductor substrate, an n.sup.- -type epitaxial layer, and p-type and n.sup.+ -type layers formed on the n.sup.- -type epitaxial layer by means of epitaxial growth or diffusion and which has a trench formed by means of R.I.E. technique for disposing a gate electrode therein. Namely, an SiO.sub.2 film is deposited by CVD method on the n.sup.+ -type layer surface of the above-mentioned wafer as a mask for forming the trench. At this time, on the back surface of the wafer is deposited an SiO.sub.2 film. Subsequently, the trench is formed by means of the well-known R.I.E. technique; however, when the remaining SiO.sub.2 mask on the substrate surface is removed after forming the trench, the SiO.sub.2 on the back surface of the substrate is concurrently removed. This causes the above-mentioned vaporization and scattering of impurities from the n.sup.+ layer (substrate) at the back surface of the wafer during the subsequent gate oxidation process, resulting in undesirable carrier density fluctuation in the channel region. Therefore, a film for preventing the impurity vaporization should be formed at the back surface side of the substrate before removing the SiO.sub.2 mask by etching. The present embodiment can solve the problem by depositing a polysilicon film or silicon nitride film before depositing SiO.sub.2 which is to be the above-mentioned mask. Accordingly, even if the SiO.sub.2 film as a trench mask is removed, or even if the SiO.sub.2 film at the back surface is removed simultaneously, by means of the aforementioned polysilicon film or silicon nitride film, the back surface of the substrate is hardly exposed, thereby preventing such problem as above. Further, if the silicon nitride film is employed as such film, the silicon nitride film can be applied to a mask material for the gate oxidation.

Further, the present invention should not be limited to a vertical type power MOSFET, but the present invention may also be applied to a power MOS-IC which includes a vertical type power MOSFET, an IGBT (insulating gate type bipolar transistor) or the like.

Furthermore, in the above embodiments, description has been given only to the n-channel type, it is needless to say that the p-channel type can obtain the same effect as the n-channel type.

Furthermore, in the above embodiments, description has been given in the vertical power element structure, but the present invention may also be applied to the lateral type power element structure, which can also obtain the same effect as the vertical power element structure. In this case, the back surface thereof is highly doped, though the drain electrode thereof is disposed on the main surface of the semiconductor substrate.

While the present invention has been shown and described with reference to the foregoing preferred embodiments, it will be apparent to those skilled in the art that changes in form and detail may be made therein without departing from the scope of the invention as defined in the appended claims.