Converter System With Power Factor and DC Ripple Control

The present invention relates generally to a converter system and, more particularly, to a converter system which converts AC to DC and which incorporates power factor and DC ripple control.

Converters, such as those which convert input AC power into output DC power for supply to one or more loads, have many applications. For example, converters are used to convert three or more phase input AC power into output DC power for onboard DC loads of an aircraft. While the aircraft is on the ground, the input AC power is typically supplied by a ground power cart; on the other hand, while the aircraft is in the air, the input AC power is supplied by generators driven by the engines of the aircraft. Thus, the converter converts the input AC power into DC power for onboard DC loads while the aircraft is on the ground or in the air.

A typical AC to DC converter includes multiple rectifiers connected together in a bridge configuration. The rectifiers are controlled so as to convert the input AC power into output DC power. A rectifier bridge, however, typically presents a non-unity power factor to the input AC source. Hence, the input AC source must have a greater capacity than if the rectifier bridge were to present a unity power factor load to the input AC source. Moreover, the output DC of a rectifier bridge typically exhibits a substantial amount of harmonic ripple.

The present invention is directed to an arrangement which controls the rectifiers of a rectifier bridge so that the rectifier bridge presents a unity power factor load to the input AC source and so that the harmonic ripple in the output DC of the rectifier bridge is suppressed, minimized, reduced, and/or eliminated.

In accordance with one aspect of the present invention, a system comprises an AC to DC converter and a controller. The AC to DC converter receives an input AC and converts the input AC to an output DC. The input AC has a voltage, a current, and a power factor based upon the voltage and current. The controller is arranged to receive the output DC and the voltage and current of the input AC, the controller is arranged to control the AC to DC converter so that the power factor is controlled, and the controller has an integrator arranged to control ripple in the output DC.

In accordance with another aspect of the present invention, a system comprises AC to DC converting means and controlling means. The AC to DC converting means converts an input AC to an output DC, wherein the input AC has a voltage, a current, and a power factor between the voltage and current. The controlling means controls the AC to DC converting means in response to the voltage and current of the input AC and in response to the output DC so that the power factor is controlled and so that ripple in the output DC is controlled.

In accordance with still another aspect of the present invention, a method comprises the following steps: a) converting an input AC to an output DC, wherein the input AC has a voltage, a current, and a power factor between the voltage and current; b) responding to the voltage and current of the input AC so that the power factor is a substantially unity power factor; and c) responding to the output DC so that ripple in the output DC is suppressed.

These and other features and advantages of the present invention will become more apparent from a detailed consideration of the invention when taken in conjunction with the drawings in which:

FIG. 1 illustrates a converter system incorporating a current regulator and an integrator for providing power factor and DC ripple control according to an analog embodiment of the present invention;

FIG. 2 illustrates in more detail the current regulator of the converter system illustrated in FIG. 1;

FIG. 3 illustrates an alternative embodiment of the integrator illustrated in FIG. 1;

FIG. 4 illustrates a further alternative embodiment for the integrator illustrated in FIG. 1; and,

FIG. 5 illustrates a converter system incorporating power factor and DC ripple control according to a digital embodiment of the present invention.

As shown in FIG. 1, a converter system 10, which is implemented as an analog converter system, includes an AC to DC converter 12 that receives input AC power from an input AC source 14. The AC to DC converter 12 converts the input AC power to output DC power, and supplies the output DC power over a DC link 16. A controller 18 controls the AC to DC converter 12.

The AC to DC converter 12 includes rectifiers 20, 22, 24, 26, 28, and 30, and inductors 32, 34, and 36. Each of the rectifiers 20, 22, 24, 26, 28, and 30 includes, for example, a corresponding power transistor having a base, a collector, and an emitter. Each of the rectifiers 20, 22, 24, 26, 28, and 30 also includes a fly back diode connected from the emitter to the collector of its corresponding power transistor. A converter line 38 connects the inductor 32 to a junction formed by the emitter of the power transistor of the rectifier 20 and the collector of the power transistor of the rectifier 22. A converter line 40 connects the inductor 34 to a junction formed by the emitter of the power transistor of the rectifier 24 and the collector of the power transistor of the rectifier 26. A converter line 42 connects the inductor 36 to a junction formed by the emitter of the power transistor of the rectifier 28 and the collector of the power transistor of the rectifier 30.

The input AC source 14 provides, for example, three-phase power to the AC to DC converter 12 over converter input lines 44, 46, and 48. A capacitor 50 is connected from a junction 52, which is between the inductor 32 and the converter input line 44, to a neutral N of an AC input 54. A capacitor 56 is connected from a junction 58, which is between the inductor 34 and the converter input line 46, to the neutral N of the AC input 54. A capacitor 60 is connected from a junction 62, which is between the inductor 36 and the converter input line 48, to the neutral N of the AC input 54.

The collectors of the power transistors of the rectifiers 20, 24, and 28 are connected to one polarity of the DC link 16, and the emitters of the power transistors of the rectifiers 22, 26, and 30 are connected to the other polarity of the DC link 16. The DC link 16 includes a DC link capacitor 66 and a DC load 68 connected in parallel between the two polarities of the output DC.

The controller 18 includes a comparator block 80 which compares a DC reference V.sub.DCREF to a DC feedback V.sub.DCFDBK. The DC feedback V.sub.DCFDBK is derived by sensing the DC voltage across the DC link capacitor 66. The comparator block 80, for example, may be a summer that subtracts the DC feedback V.sub.DCFDBK from the DC reference V.sub.DCREF to generate an error. Alternatively, the comparator block 80 may be any other device which is suitable for generating an error between the DC feedback V.sub.DCFDBK and the DC reference V.sub.DCREF.

The error generated by the comparator block 80 is integrated by an integration block 82, and the integrated error is supplied by the integration block 82 to multiplier blocks 84, 86, and 88. The multiplier block 84 multiplies the integrated error from the integration block 82 by an input AC phase voltage at the junction 52.

The multiplier block 84 provides the result of its multiplication to a current regulator 90. Similarly, the multiplier block 86 multiplies the integrated error from the integration block 82 by an input AC phase voltage at the junction 58. The multiplier block 86 provides the result of its multiplication to the current regulator 90. Likewise, the multiplier block 88 multiplies the integrated error from the integration block 82 by an input AC phase voltage at the junction 62. The multiplier block 88 provides the result of its multiplication to the current regulator 90. Accordingly, the input AC phase voltage for each phase of the AC input 54 is multiplied by the integrated error between the DC reference V.sub.DCREF and the DC feedback V.sub.DCFDBK, and the multiplication results are supplied to the current regulator 90.

In addition to receiving the multiplication results from the multiplier blocks 84, 86, and 88, the current regulator 90 receives representations of the input AC phase currents carried by the converter lines 38, 40, and 42. Accordingly, a current transformer 100 senses the input AC phase current in the converter line 38, a current transformer 102 senses the input AC phase current in the converter line 40, and a current transformer 104 senses the input AC phase current in the converter line 42. Representations of the input AC phase currents sensed by the current transformers 100, 102, and 104 are provided by the current transformers 100, 102, and 104 to the current regulator 90 as feedback currents, whereas the multiplication results from the multiplier blocks 84, 86, and 88 are provided to the current regulator 90 as reference currents.

FIG. 2 illustrates the portion of the current regulator 90 which controls the power transistors of the rectifiers 20 and 22 of the AC to DC converter 12. The current transformer 100 provides a feedback current I.sub.FDBKa, which corresponds to the input AC phase current in the converter line 38, to one input of a comparator block 114 of the current regulator 90. The multiplier block 84 provides the reference current I.sub.REFa, which is based upon the multiplication of the integrated error supplied by the integration block 82 and the input AC phase voltage at the junction 52, to another input of the comparator block 114 of the current regulator 90. The comparator block 114 compares the reference current I.sub.REFa to the feedback current I.sub.FDBKa in order to generate an error output. The comparator block 114, for example, may be a summer that subtracts the feedback current I.sub.FDBKa from the reference current I.sub.REFa in order to produce this error output.

Gain is applied to the error output from the comparator block 114 at a gain block 116. Alternatively, gain and integration may be applied to the error output from the comparator block 114. The error output from the gain block 116 is limited by a limit block 118 which limits the error output from the gain block 116 between maximum and minimum values. The limited error output is then supplied as one input to a pulse width modulation block 120 which modulates a carrier in response to the limited error output from the limit block 118. The carrier, for example, may be a triangular wave carrier. The modulated carrier is provided to a gate drive block 122 in order to drive the bases of the power transistors of the rectifiers 20 and 22.

It should be understood that another portion of the current regulator 90, similar to the portion illustrated in FIG. 2, controls the power transistors of the rectifiers 24 and 26 of the AC to DC converter 12 in response to a feedback current I.sub.FDBKb, which corresponds to the input AC phase current in the converter line 40 as sensed by the current transformer 102, and the reference current I.sub.REFb, which is based upon the multiplication of the integrated error supplied by the integration block 82 and the input AC phase voltage at the junction 58. Like-wise, still another portion of the current regulator 90, similar to the portion illustrated in FIG. 2, controls the power transistors of the rectifiers 28 and 30 of the AC to DC converter 12 in response to a feedback current I.sub.FDBKc. which corresponds to the input AC phase current in the converter line 42 as sensed by the current transformer 104, and the reference current I.sub.REFc, which is based upon the multiplication of the integrated error supplied by the integration block 82 and the input AC phase voltage at the junction 62. Additional portions of the current regulator may be necessary if there are more input phases.

Because the current regulator 90 is driven by both the input AC phase currents as sensed by the current transformers 100, 102, and 104, and the input AC phase voltages as sensed at the junctions 52, 58, and 62, the input AC phase currents in the converter lines 38, 40, and 42 are made to track the input AC phase voltages so that the power factor of the input AC source is substantially unity.

Moreover, the integration block 82 provides an input to the current regulator 90 through the multiplier blocks 84, 86, and 88. This input is based upon the DC voltage across the DC link capacitor 66. Accordingly, the rectifiers 20, 22, 24, 26, 28, and 30 of the AC to DC converter 12 are controlled so as to reduce ripple on the DC link 16. In effect, the integration block 82 makes the AC to DC converter 12 less sensitive to imbalances on the source side of the AC to DC converter 12, thereby reducing the ripple content in the output DC power on the DC link 16.

Furthermore, the level of the DC voltage on the DC link 16 is determined by the DC reference V.sub.DCRFF provided to the comparator block 80. That is, the DC reference V.sub.DCREF as provided to the comparator block 80 ensures that the current controller 90 controls the rectifiers 20, 22, 24, 26, 28, and 30 so that the DC voltage on the DC link 16 is at the DC reference V.sub.DCREF.

The integration block 82 may be reset upon power up, for example, in order to guard against a condition where the AC to DC converter 12 is called upon to generate full output DC power at a level specified by V.sub.DCREF even though the AC input 54 is just winding up. Thus, at power up, the output of the integration block 82 may be reset to some minimum level, such as zero, in order to soft start the AC to DC converter 12.

The integration block 82 as shown in FIG. 1 works well in substantially steady state conditions, but may be slow to respond to transient conditions. Accordingly, an integration block 130 may be substituted for the comparator block 80 and the integration block 82 in the control arrangement shown in FIG. 1. The integration block 130 includes a comparator block 132 which compares the DC reference V.sub.DCREF to a modified DC feedback V*.sub.DCFDBK in order to produce an error output. The comparator block 132, for example, may be a summer that subtracts the modified DC feedback V*.sub.DCFDBK, which is derived from the DC link capacitor 66, from the DC reference V.sub.DCREF to produce the error output.

This error output is provided to an absolute value block 138. A multiplier block 140 multiplies the absolute value of the error output by the error output itself. In essence, the absolute value block 138 and the multiplier block 140 square the error output, but preserve the sign of the error output from the comparator block 132. The output of the multiplier block 140 is supplied to a gain block 142 and the output of the gain block 142 is supplied to one input of a summing block 144, another input of which receives the error output from the comparator block 132. The summing block 144 sums the error output of the comparator block 132 with the sign preserved square of the error output. The output of the summing block 144 is then integrated by an integration function 146.

The integration block 130 has an upper path 150 and a lower path 152. The upper path 150 is a low gain path that works well in steady state conditions. The lower path 152 (including the absolute value block 138, the multiplier block 140, and the gain block 142) is a high gain path that works well in transient conditions because it boosts the error output from the comparator block 132 so that the boosted error output results in a faster response from the integration function 146.

As shown in FIG. 3, the DC feedback V.sub.DCFDBK from the DC link capacitor 66 is not applied directly to the comparator block 132. Instead, the DC feedback V.sub.DCFDBK from the DC link capacitor 66 is provided to one input of a summing block 154, the other input of which receives DC link current I.sub.c through a gain block 156. The DC link current I.sub.c is the current that flows through the DC link capacitor 66. The summing block 154 adds the output of the gain block 156 and the DC feedback V.sub.DCFDBK in order to produce the modified the DC feedback V*.sub.DCFDBK. Accordingly, by using the DC link current I.sub.c, which is representative of the derivative of the DC link voltage across the DC link capacitor 66, response to transient conditions is faster. That is, when a transient condition occurs which causes the DC link voltage to change, the DC link current I.sub.c, which is a reflection of the derivative of the DC link voltage, causes the integration block 130 to react more quickly than otherwise would be the case.

The DC feedback V.sub.DCFDBK is also supplied to a comparator block 158 which compares the DC feedback V.sub.DCFDBK to a predetermined threshold, such that the integration function 146 is reset until the DC feedback V.sub.DCFDBK attains the pre-determined threshold, after which the integration function 146 is not reset. For example, if V.sub.DCREF is 400 volts so that the DC link voltage is to be controlled at 400 volts, the predetermined threshold imposed by the comparator block 158 may be 270 volts. Accordingly, the integration function 146 does not perform its integration function until the DC feedback VDCFDBK reaches 270 volts.

FIG. 4 shows an integration block 170 which alternatively may be used in place of the integration block 82 in FIG. 1. The integration block 170 includes a comparator block 172 which compares the DC reference V.sub.DCREF to the modified DC feedback V*.sub.DCFDBK in order to produce an error output. The comparator block 172, for example, may be a summer that subtracts the modified DC feedback V.sub.DCFDBK from the DC reference V.sub.DCREF to produce the error output.

The error output is provided to a high gain block 176 that has a two-level output. A first output of the high gain block 176 has one extreme value if the magnitude of the error output from the comparator block 172 is above a predetermined threshold, and a second output of the high gain block 176 has another extreme value if the magnitude of the error output from the comparator block 172 is below the predetermined threshold. Thus, the high gain block 176 in effect imposes a bang-bang operation on the error output of the comparator block 172.

The error output produced by the comparator block 172 is also provided to a low gain integration function 178. The initial conditions for the low gain integration function 178 are provided from a table stored in a table block 182. The table block 182 stores sets of initial conditions, and provides a set of initial conditions to the low gain integration function 178 depending upon the current IDC flowing through the DC load. These initial conditions may be selected to permit the AC to DC converter 12 to soft start, particularly at start up of the input AC source 14.

A selector block 184 selects whether the output of the high gain block 176 or the output of the low gain integration function 178 is provided to the multiplier blocks 84, 86, and 88. The selector block 184 is controlled by a comparator block 186 which compares the error output from the comparator block 172 to a set of conditions defining the diamond 188 and the band 190. The horizontal axis of the diamond 188 and the band 190 is the error output (e) from the comparator block 172, and the vertical axis of the diamond 188 and the band 190 is the derivative of the error output (de/dt) from the comparator block 172 which is proportional to the DC link current I.sub.c. If the error output and its derivative are within the diamond 188, the selector block 184 is controlled to select the output of the low gain integration function 178. If the error output and its derivative are outside the diamond 188, which occurs during transient conditions, the band 190 becomes active, the selector block 184 is controlled to select the output of the high gain block 176, and the low gain integration function 178 is reset to conditions selected by the table block 182. When the error output and its derivative return to within the band 190, the diamond 188 becomes active, and the selector block 184 is controlled to select the output of the low gain integration function 178. Accordingly, the integration block 170 is arranged to respond faster to transient conditions.

A converter system 200 shown in FIG. 5 may be implemented as a digital converter system. The converter system 200 includes an AC to DC converter 202 which converts input AC from an input AC source 204 to DC for supply over a DC link 206. The AC to DC converter 202 is controlled by a controller 208.

The controller 208 includes a coordinate transformation block 210. The coordinate transformation block 210 transforms the three-phase feedback currents I.sub.a, I.sub.b, and I.sub.c provided by a three-phase current transformer CT into a direct component I.sub.d and a quadrature component I.sub.q. The three-phase feedback currents I.sub.a, I.sub.b, and I.sub.c represent the input AC to the AC to DC converter 202.

An angle .theta., i.e., the angle between the voltage and current of one of the phases of the input AC source 204, is derived by an angle/frequency detector block 216 which is connected to the input AC source 204. The angle/frequency detector block 216 provides the angle .theta. to a sine/cosine table block 218. If the angle .theta. is not detectable from a selected one of the phases of the input AC source 204, the angle/frequency detector block 216 may be arranged to detect the angle .theta. based upon another of the phases of the input AC source 204. The sine/cosine table block 218 provides the sin(.theta.) and the cos(.theta.) to the coordinate transformation block 210. Based upon sin(.theta.) and cos(.theta.), the coordinate transformation block 210 transforms the three-phase feedback currents I.sub.a, I.sub.b, and I.sub.c into their direct and quadrature components I.sub.d and I.sub.q.

In making the coordinate transformation, the coordinate transformation block 210 first determines the component I.sub.d * and the component I.sub.q * based upon the following equations: ##EQU1## The coordinate transformation block 210 then transforms the component I.sub.d * and the component I.sub.q * according to the following matrix equation: ##EQU2##

The direct component I.sub.d is supplied to a comparator block 220 which compares the direct component I.sub.d to a direct component reference I.sub.dREF. The direct component reference I.sub.dREF may be zero in order to suppress the direct component I.sub.d related to the operation of the AC to DC converter 202. The quadrature component I.sub.q is supplied to a comparator block 222 which compares the quadrature component I.sub.q to a quantity based upon the DC link voltage across a DC link capacitor 224 and the DC reference V.sub.DCREF.

More specifically, a comparator block 226 compares the DC reference V.sub.DCREF to a DC feedback V.sub.DCFDBK, where the DC feedback V.sub.DCFDBK is the DC link voltage across the DC link capacitor 224, in order to generate an error output.

This error output is supplied through a voltage control block 228 to a positive input of the comparator block 222. The negative input of the comparator block 222 receives the quadrature component I.sub.q. The voltage control block 228 may perform the integration function of the integration block 82 of FIG. 1, the integration block 130 of FIG. 3, the integration block 170 of FIG. 4, or the like.

The outputs of the comparator blocks 220 and 222 are provided to a d/q axis current control block 230. The d/q axis current control block 230 may apply a proportional control function, or proportional and integral control functions, individually to the error outputs generated by the comparator blocks 220 and 222. These error outputs, as processed by the d/q axis current control block 230, are then passed to the coordinate transformation block 210.

Based upon sin(.theta.) and cos(.theta.), the coordinate transformation block 210 translates the error outputs as processed by the d/q axis current control block 230 into three-phase reference currents I.sub.a *, I.sub.b *, and IC. Specifically, the coordinate transformation block 210 first transforms the error functions e.sub.d and e.sub.q, which are the error outputs from the comparator blocks 220 and 222, respectively, as individually processed by the d/q axis current control block 230, according to the following matrix equation: ##EQU3## The coordinate transformation block 210 then determines the three-phase reference currents I.sub.a *, I.sub.b *, and I.sub.c *, from the following equations: ##EQU4##

The three-phase reference currents I.sub.a *, I.sub.b *, and I.sub.c * are supplied to positive inputs of corresponding comparator blocks 240, 242, and 244. The three-phase feedback currents I.sub.a, I.sub.b, and I.sub.c are provided to minus inputs of the corresponding comparator blocks 240, 242, and 244. The comparator blocks 240, 242, and 244 generate control errors between the three-phase reference currents I.sub.a *, I.sub.b *, and I.sub.c * and the corresponding three-phase feedback currents I.sub.a, I.sub.b, and I.sub.c.

These control errors are provided to a three-phase current controller block 246. The three-phase current controller block 246 may be a gain block which individually applies gain to the control errors provided by the comparator blocks 240, 242, and 244. The outputs of the three-phase current controller block 246 are then provided to a pulse width modulator block 248 which also receives a frequency input f from the angle/frequency detector block 216. The pulse width modulator block 248 may be similar to the pulse width modulator block 120 shown in FIG. 2, the primary difference being that the carrier, which is modulated by the outputs from the three-phase current control block 246, is synchronized by the frequency input f supplied by the angle/frequency detector 216. The outputs of the pulse width modulator block 248 are provided to the rectifiers of the AC to DC converter 202 in a manner similar to that shown in FIG. 1.

By setting the direct component reference I.sub.dREF supplied to the comparator block 220 to zero, the direct component I.sub.d, on which the three-phase reference currents I.sub.a *, I.sub.b *, and I.sub.c * are based, is suppressed, allowing the quadrature component I.sub.q to control the pulse width modulator block 248. In this manner, the pulse width modulator block 248 controls the AC to DC converter 202 only in response to the quadrature component of the input currents from the input AC source 204, which are aligned angularly with the input voltages from the input AC source 204. Accordingly, the power factor between the voltages and corresponding currents from the input AC source 204 is unity.

Moreover, the voltage control block 228 responds to the DC reference V.sub.DCREF and the DC link voltage across the DC link capacitor 224 so that the AC to DC converter 202 is controlled in a manner to suppress ripple on the DC link 206.

Furthermore, the level of the DC voltage on the DC link 206 is determined by the DC reference V.sub.DCREF provided to the comparator block 226. That is, the DC reference V.sub.DCREF as provided to the comparator block 226 ensures that the controller 208 controls the AC to DC converter 202 so that DC voltage on the DC link 206 is at the DC reference V.sub.DCREF.

Certain modifications of the present invention have been discussed above. Other modifications will occur to those practicing in the art of the present invention. For example, the comparator block 80, as described above, may be any device other than a summer which is suitable for generating an error between the DC feedback V.sub.DCFDBK and the DC reference V.sub.DCREF. Similarly, the comparator blocks 114, 132, 172, 220, 222, 226, 240, 242, and 244 may be any devices other than summers which are suitable for generating errors.

Also, the controller 18 and the controller 208 are shown as comprising various blocks. Each of these blocks may be implemented, either individually or in the aggregate, as one or more discrete components, as one or more integrated circuits, as one or more programmable logic circuits or arrays, as software, and/or the like.

Accordingly, the description of the present invention is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which are within the scope of the appended claims is reserved.