Voltage Generating Circuit and Liquid Crystal Display Device Incorporating the Voltage Generating Circuit

The present invention relates to a voltage generating circuit for driving a display device using a capacitive display element, such as a liquid crystal display device, and to a liquid crystal display device incorporating the voltage generating circuit.

In a resent information-oriented society, movable digital assistants, particularly, personal digital assistants (PDA) have been the center of public attention. One of the objectives to be achieved by the personal digital assistants is a lowering of power consumption. As the display device for use in the personal digital assistants, a liquid crystal display device has been most commonly used. There is also great demand for a lowering of power consumption in respect of the liquid crystal display device.

The liquid crystal display devices are roughly classified into two types, namely, passive matrix type and active matrix type. The active matrix type liquid crystal display devices are superior to the passive matrix type liquid crystal display devices in terms of the display quality. One type of the active matrix display device uses a three-terminal non-linear element, such as a TFT (thin film transistor), as a switching element. Another type of the active matrix display device uses a two-terminal non-linear element, such as an MIM (metal insulator metal), as a switching element. The two-terminal type switching element has the following advantages over the three-terminal type element. Namely, the two-terminal type switching element can be obtained at low cost because it can be produced by a simple process. Moreover, since there are only two terminals, the electrode wiring is simpler, and therefore the two-terminal type switching element achieves a higher aperture ratio of the pixel.

The active matrix type liquid crystal display devices using the two-terminal non-linear element can achieve high-contrast and even displays by an amplitude selective addressing scheme, but suffers from a drawback that a residual image (seizure) is apt to occur. In order to reduce the residual image, for example, an addressing scheme disclosed in Japanese publication of unexamined patent application (Tokukaihei) No. 8-262406 employs a method of switching one selecting period of a scanning signal among three voltage levels (the driving method with the selection period being divided into the first through third periods).

Here, a conventional driving method of this type is explained. First, referring to FIG. 3, a typical structure of a liquid crystal display device is explained.

The liquid crystal display device includes a liquid crystal display panel 50. The liquid crystal display panel 50 is provided with data electrode lines X1 through Xn, and scanning electrode lines Y1 through Ym. Additionally, in order to drive the liquid crystal panel, the liquid crystal display device includes a control section 55 for generating control signals, voltage generating circuits 51, 53 for generating voltages according to the control signal, a scanning electrode driver 54 for generating a scanning signal based on the voltage generated by the voltage generating circuit 53 and applying the scanning signal to the scanning electrode lines Y1 through Ym, and a data electrode driver 52 for generating a data signal based on the voltage generated by the voltage generating circuit 51 and applying the data signal to the data electrode lines X1 through Xn.

Referring now to FIG. 16, the following description will explain various signals used in the driving method with the selection period being divided into the first through third periods. In FIG. 16, V.sub.P represents a scanning signal applied to the scanning electrode lines Y1 through Ym. The scanning signal V.sub.P is generated as follows.

The voltage generating circuit 53 generates scanning electrode driver input signals V.sub.H, V.sub.L, V.sub.M, and inputs these signals into the scanning electrode driver 54. Here, the scanning electrode driver input signal V.sub.H is a rectangular wave in which voltages V.sub.1 and V.sub.2 alternately appear, and the scanning electrode driver input signal V.sub.L is a rectangular wave in which voltages V.sub.4 and V.sub.5 alternately appear. The scanning electrode driver input signal V.sub.M is a constant voltage as a non-selected voltage.

In the scanning electrode driver 54, the scanning voltage V.sub.P is generated based on the scanning electrode driver input signals V.sub.H, V.sub.L, V.sub.M according to control signals such as a scanning clock signal LP, a scanning start signal S and an alternating inverted signal M. Specifically, the scanning electrode driver 54 generates the scanning voltage V.sub.P by selectively outputting the scanning electrode driver input signal V.sub.H or V.sub.L in a selecting period T.sub.S, and by outputting the scanning electrode driver input signal V.sub.M as the non-selected voltage in a non-selecting period.

In order to generate a rectangular wave by outputting voltages of two different levels alternately like the scanning electrode driver input signal V.sub.H or V.sub.L, the voltage generating circuit 53 includes a voltage switching circuit shown in, for example, FIG. 17. The voltage switching circuit shown in FIG. 17 has a p-channel MOS transistor 151 and an n-channel MOS transistor 152 so as to generate the scanning electrode driver input signal V.sub.H. By controlling the p-channel MOS transistor 151 and n-channel MOS transistor 152 to be repeatedly turned into the ON state and OFF state alternately by control signals CS1, CS2, input voltages V.sub.1, V.sub.2 are alternately output as an output voltage V.sub.0. As a result, the scanning electrode driver input signal V.sub.H is generated.

FIG. 18 is a waveform illustration showing the relationship between the output voltage V.sub.0 of the voltage switching circuit of FIG. 15 and an output current I.sub.0. When a voltage like the output voltage V.sub.0 is applied to a capacitive element, such as a liquid crystal, a reverse current a is produced as shown by the waveform of the current I.sub.0 in a switching timing from the high voltage V.sub.2 to low voltage V.sub.1. The reverse current a is a cause of a waste of power, and increases the power consumption. Furthermore, this voltage switching circuit requires an input voltage of the same level as an output voltage. Therefore, the peripheral members that perform voltage switching need to have a withstand voltage not lower than the output level, resulting in an increase in the production cost.

It is an object of the present invention to provide a low-power-consuming voltage generating circuit at low cost.

In order to achieve the above object, a voltage generating circuit of the present invention is a voltage generating circuit for supplying a voltage to a display device having a capacitive element, which includes:

an output terminal connected to the display device;

two input terminals to which voltages V.sub.a and V.sub.b are input, respectively;

a switch, provided between the output terminal and the input terminals, for switching a state between first and second states;

a capacitor provided between the switch and the output terminal; and

a rectifying element connected to the capacitor in parallel, and is characterized by that

when the switch is in the first state, the voltage V.sub.a is output from the output terminal, and the capacitor is charged, and

when the switch is in the second state, a sum voltage V.sub.d of a voltage V.sub.c charged on the capacitor and one of the voltages V.sub.a and V.sub.b input from the input terminals is output from the output terminal,

V.sub.a and V.sub.d have the same polarity with respect to a reference voltage,

.vertline.V.sub.a .vertline.<.vertline.V.sub.d .vertline., and

.vertline.V.sub.b .vertline.<.vertline.V.sub.d .vertline.

With this structure, when the switch is in the first state, the voltage V.sub.a input from the input terminal is output as it is from the output terminal, and the capacitor is charged. When the switch is switched to the second state, the sum voltage V.sub.d of the voltage V.sub.c charged on the capacitor and one of the input voltages V.sub.a and V.sub.b is output from the output terminal. Namely, according to the switching operation of the switch, the voltages V.sub.a and V.sub.d are output alternately from the output terminal. The output voltages V.sub.a and V.sub.d have a positive polarity with respect to the reference voltage, and satisfy the relationship .vertline.V.sub.a .vertline.<.vertline.V.sub.d. Therefore, when the output voltage is switched from V.sub.d to V.sub.a, i.e., when immediately after the switch is switched to the first state from the second state, the charge stored in the capacitive element of the display device flows as a reverse current into the voltage generating circuit through the output terminal. The reverse current is guided to and stored on the capacitor by the rectifying effect of the rectifying element. Thereafter, when the switch is switched to the second state, the reverse current is effectively used, thereby achieving a lowering of power consumption.

Meanwhile, in a conventional structure, in order to output two levels of voltages V.sub.a and V.sub.d, it is necessary to input the voltages V.sub.a and V.sub.d of the same level as the output voltage. Thus, the component parts of the voltage generating circuit are required to have a sufficient withstanding property against the voltage V.sub.d which has a greater absolute value of the electric potential difference with respect to the reference voltage than the electric potential difference between the reference voltage and the other output voltage. In order to meet such a requirement, the above-mentioned structure uses the voltage V.sub.c charged on the capacitor. Therefore, the voltages V.sub.a and V.sub.b having smaller absolute values of the electric potential differences with respect to the reference voltage compared to the voltage V.sub.d can be used as the input voltages. Accordingly, the required withstanding property for the component parts of the voltage generating circuit is lowered, thereby achieving reduction in cost.

The above-mentioned voltage generating circuit can be constructed so that V.sub.d =V.sub.b +V.sub.c, and V.sub.c =V.sub.a.

With this structure, in a period in which the switch is in the first state, the voltage V.sub.a as one of the input voltages is output from the output terminal, and a voltage V.sub.c across the terminals of the capacitor becomes equal to the voltage V.sub.a due to the charge stored on the capacitor. A voltage V.sub.d to be output when the switch is switched to the second state becomes the sum of the voltage V.sub.b as the other of the input voltage and the voltage V.sub.c charged on the capacitor, i.e., V.sub.a. Namely, it is possible to produce output voltages of two levels, V.sub.a and V.sub.a +V.sub.b, from the input voltages V.sub.a and V.sub.b. In other words, for example, if the V.sub.a and V.sub.b are V.sub.1 and V.sub.2 -V.sub.1, respectively, it is possible to generate V.sub.1 and V.sub.2 as the output voltages.

Alternatively, the above-mentioned voltage generating circuit can be constructed so that V.sub.d =V.sub.a +V.sub.c, and V.sub.c =V.sub.a -V.sub.b.

With this structure, when the switch is in the first state, the voltage V.sub.a as one of the input voltages is output from the output terminal, and the voltage V.sub.c across the terminals of the capacitor becomes equal to the voltage V.sub.a -V.sub.b due to the amount of charge stored on the capacitor. Moreover, the voltage V.sub.d to be output when the switch is switched to the second state becomes the sum of the voltage V.sub.a and the voltage V.sub.c charged on the capacitor, i.e., V.sub.a -V.sub.b. Namely, it is possible to produce output voltages of two levels, V.sub.a and 2V.sub.a -V.sub.b, from the input voltages V.sub.a and V.sub.b. In other words, for example, if the input voltages V.sub.a and V.sub.b are V.sub.1 and 2V.sub.1 -V.sub.2, respectively, it is possible to generate V.sub.1 and V.sub.2 as the output voltages.

Besides, the above-mentioned voltage generating circuit can be constructed so that the capacity of the capacitor is smaller than the load capacity.

With this structure, by appropriately setting the capacity of the capacitor, it is possible to set the value of one of the two levels of the output voltages, which has a greater electrical potential difference with respect to the reference voltage than the other of the output voltages, to a desired value, without changing the values of the input voltages.

Furthermore, a liquid crystal display device according to the present invention includes the above-mentioned voltage generating circuit, and a liquid crystal panel as the display device.

In this liquid crystal display device, a non-linear element, for example, TFT and MIM, used as a switching element in the pixel of the liquid crystal panel functions as the capacitive element. With the use of the above-mentioned voltage generating circuit in this liquid crystal display device, even the liquid crystal display device can have the benefit of the use of the above-mentioned voltage generating circuit. It is thus possible to provide a low-power-consuming liquid crystal display device at low cost.

For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a schematic structure of a voltage generating circuit according to one embodiment of the present invention.

FIG. 2 is a waveform illustration showing the waveform of an output voltage of the voltage generating circuit shown in FIG. 1.

FIG. 3 is a block diagram illustrating a schematic structure of a liquid crystal display device as one embodiment of a display device of the present invention.

FIG. 4 is a circuit diagram illustrating an equivalent circuit of pixels of the liquid crystal display device shown in FIG. 3.

FIG. 5 is a block diagram illustrating the input paths of control signals and an input voltage to a scanning electrode driver of the liquid crystal display device shown in FIG. 3.

FIG. 6 is an equivalent circuit diagram illustrating the structure of the scanning electrode driver.

FIG. 7 is a circuit diagram showing the structure of a voltage generating circuit according to another embodiment of the present invention.

FIG. 8 is a waveform illustration showing the waveform of an output voltage of the voltage generating circuit shown in FIG. 7.

FIG. 9 is a waveform illustration showing the waveform of an output voltage of a voltage generating circuit according to still another embodiment of the present invention.

FIG. 10 is a waveform illustration showing the waveform of an output voltage of a voltage generating circuit according to yet another embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating the structure of a voltage generating circuit according to other embodiment of the present invention.

FIG. 12 is a circuit diagram illustrating the structure of a voltage generating circuit according to other embodiment of the present invention.

FIG. 13 is a waveform illustration showing the waveforms of switching control signals for controlling the switching operation in the voltage generating circuit shown in FIG. 11, and the waveform of an output voltage of the voltage generating circuit.

FIG. 14 is a waveform illustration showing the waveforms of switching control signals for controlling the switching operation according to other embodiment of the present invention, and the waveform of an output voltage of the voltage generating circuit.

FIG. 15 is a circuit diagram illustrating the structure of a voltage generating circuit according to other embodiment of the present invention.

FIG. 16 is a waveform illustration showing the waveforms of various signals used in the driving method with the selection period being divided into the first through third periods, and of scanning signals generated based on the various signals.

FIG. 17 is a circuit diagram showing the structure of a conventional voltage generating circuit.

FIG. 18 is a waveform illustration showing the waveforms of an output voltage and an output current of a conventional voltage generating circuit .

[Embodiment 1]

The following description will explain an embodiment of the present invention with reference to FIGS. 1 to 6.

FIG. 3 is a block diagram showing a schematic structure of a liquid crystal display device (display device) according to one embodiment of the present invention. This liquid crystal display device includes a liquid crystal display panel 50. The liquid crystal display panel 50 has data electrode lines X1 through Xn and scanning electrode lines Y1 through Ym, arranged to cross each other at right angles. Besides, in order to drive the liquid crystal panel 50, the liquid crystal display device includes a control section 55 for generating a control signal, voltage generating circuits 51, 53 for generating voltages according to the control signals, a scanning electrode driver 54 for generating a scanning signal based on the voltage generated by the voltage generating circuit 53 and applying the scanning signal to the scanning electrode lines Y1 through Ym, and a data electrode driver 52 for generating a data signal based on the voltage generated by the voltage generating circuit 51 and applying the data signal to the data electrode lines X1 through Xn. The voltage generating circuit 53 is a voltage generating circuit according to the present invention, and the voltage generating circuit 51 may have a known structure.

In the liquid crystal display 50, as illustrated in FIG. 4, each region separated by the data electrode lines X1 through Xn and scanning electrode lines Y1 through Ym corresponds to one pixel. Each region is provided with a liquid crystal element 141 and a two-terminal non-linear element 142. The liquid crystal element 141 and two-terminal non-linear element 142 are connected in series so that one of the electrodes of each liquid crystal element 141 is connected to any of the data electrode lines X1 through Xn, and one of each two-terminal non-linear element 142 is connected to any of the scanning electrode lines Y1 through Ym.

FIG. 5 is a block diagram showing the input path of the control signals from the control section 55 to the scanning electrode driver 54, and the input path of the input voltage.

The control section 55 generates a scanning clock signal LP, a scanning start signal S and an alternating inverted signal M as control signals, and outputs these control signals to the scanning electrode driver 54 and voltage generating circuit 53.

The voltage generating circuit 53 generates scanning electrode driver input signals V.sub.H, V.sub.L, V.sub.M based on an external input voltage V.sub.E, according to the control signals from the control section 55, and outputs these signals into the scanning electrode driver 54.

FIG. 6 is a circuit diagram showing the structure of the scanning electrode driver 54. A scanning signal V.sub.P is generated by selectively outputting one of the scanning electrode driver input signals V.sub.H, V.sub.L, V.sub.M generated by the voltage generating circuit 53, according to the scanning clock signal LP, scanning start signal S and alternating inverted signal M as the control signals. The scanning signal V.sub.P is applied to the scanning electrode lines Y1 through Ym.

FIG. 1 illustrates an example of the structure of the voltage generating circuit 53 of the liquid crystal display device of this embodiment. The voltage generating circuit 53 has input terminals 10a, 10b. The input voltages to the input terminals 10a, 10b are constant voltages of positive polarity with respect to a reference voltage V.sub.S. Their electric potentials to the reference voltage V.sub.S are V.sub.1, and V.sub.2 -V.sub.1, respectively. Here, the voltages satisfy the relationship V.sub.S <V.sub.1 <V.sub.2.

A diode (rectifying element) 13 is disposed between the input terminal 10a and the output terminal 14. A switch 11 for switching the reference voltage V.sub.S and the input voltage V.sub.2 -V.sub.1 from the input terminal 10b is provided. A terminal of the switch 11, connected to the reference voltage V.sub.S is represented by 11a, while a terminal connected to the input voltage V.sub.2 -V.sub.1 is indicated by 11b. A capacitor 12 is positioned between the switch 11 and output terminal 14.

FIG. 2 shows an example of the waveform of an output voltage V.sub.0 from the output terminal 14 when the switch 11 performs switching between the terminals 11a and 11b alternately. In a period T.sub.a1 in which the switch 11 is connected to the terminal 11a, the voltage V.sub.1 is output through the diode 13 to the output terminal 14, and simultaneously the capacitor 12 is charged with the voltage V.sub.1. Next, in a period T.sub.a2 in which the switch 11 is connected to the terminal 11b, the voltage V.sub.0 is increased to the voltage V.sub.2 as the sum voltage of the input voltage V.sub.2 -V.sub.1 and the charged voltage V.sub.1 to the capacitor 12.

When the switch 11 is connected to terminal 11a again, the voltage V.sub.1 is output as the output voltage V.sub.0 to the output terminal 14. At this time, immediately after the switch 11 is connected to the terminal 11a, a reverse current flows into the voltage generating circuit 53 from the liquid crystal panel 50 and is stored on the capacitor 12 through the output terminal 14. Consequently, the amount of current that flows from the input terminal 10a and is consumed by charging of the capacitor 12 is reduced, thereby lowering the power consumption.

The voltage generating circuit 53 repeats the above-mentioned operation by switching the switch 11, and outputs a rectangular wave V.sub.H like the one shown in FIG. 2 from the output terminal 14. As described above, in the voltage generating circuit 53, the values of the input voltages necessary for generating output voltages V.sub.1 and V.sub.2 are V.sub.1 and V.sub.2 -V.sub.1 if a sufficient amount of charge is stored on the capacitor 12. Here, the voltages satisfy the relationship V.sub.2 -V.sub.1 <V.sub.2. Namely, in a conventional voltage switching circuit shown in FIG. 17, the input voltages need to have values V.sub.1 and V.sub.2 in order to generate output voltages V.sub.1 and V.sub.2. Whereas, according to the voltage generating circuit of this embodiment, one of the input voltages can be a voltage V.sub.2 -V.sub.1 that is lower than V.sub.2. Accordingly, the component parts of the voltage generating circuit 53 and their peripheral members are not required to have a withstanding property as high as that required by a conventional circuit, thereby achieving reduction in cost and power consumption.

[Embodiment 2]

The following description will explain another embodiment of the present invention with reference to FIGS. 7 and 8. The structures having the same functions as those in Embodiment 1 will be designated by the same codes and their description will be omitted.

This embodiment explains an example of the structure of the voltage generating circuit 53, in which an input voltage having a negative polarity with respect to the reference voltage V.sub.S is used. As illustrated in FIG. 7, the voltage generating circuit 53 has input terminals 30a, 30b for inputting voltages of the negative polarity with respect to the reference voltage V.sub.S. The voltages input to the input terminals 30a, 30b, respectively, are constant voltages of the negative polarity with respect to the reference voltage V.sub.S, and their electric potentials with respect to the reference voltage V.sub.S are V.sub.4 and V.sub.5 -V.sub.4, respectively. Here, the voltages satisfy the relationship V.sub.S >V.sub.4 >V.sub.5.

A diode 33 is disposed between the input terminal 30a and the output terminal 34. A switch 31 for switching the reference voltage V.sub.S and the input voltage V.sub.5 -V.sub.4 from the input terminal 30b is provided. A terminal of the switch 31, connected to the reference voltage V.sub.S, is represented by 31c, while a terminal connected to the input voltage V.sub.5 -V.sub.4 is indicated by 31d. A capacitor 32 is positioned between the switch 31 and output terminal 34.

FIG. 8 shows an example of the waveform of an output voltage V.sub.0 from the output terminal 34 when the switch 31 performs switching between the terminals 31c and 31d alternately. In a period T.sub.b1 in which the switch 31 is connected to the terminal 31c, the voltage V.sub.4 is output through the diode 33 to the output terminal 34, and simultaneously the capacitor 32 is charged with the voltage V.sub.4. Next, in a period T.sub.b2 in which the switch 31 is connected to the terminal 31d, the output voltage V.sub.0 becomes the voltage V.sub.S as the sum voltage of the input voltage V.sub.5 -V.sub.4 and the charged voltage V.sub.4 to the capacitor 32.

When the switch 31 is connected to the terminal 31c again, the voltage V.sub.4 is output as the output voltage V.sub.0 to the output terminal 34. At this time, immediately after the switch 31 is connected to the terminal 31c, a reverse current flows into the voltage generating circuit 53 from the liquid crystal panel 50 and is stored on the capacitor 32 through the output terminal 34. Consequently, the amount of current that flows from the input terminal 30a and is consumed by charging of the capacitor 32 is reduced, thereby lowering the power consumption.

The voltage generating circuit 53 repeats the above-mentioned operation by switching the switch 31, and outputs the rectangular wave V.sub.L like the one shown in FIG. 8 from the output terminal 34. As described above, in the voltage generating circuit 53, the values of the input voltages necessary for generating output voltages V.sub.4 and V.sub.5 are V.sub.4 and V.sub.5 -V.sub.4, if a sufficient amount of charge is stored on the capacitor 32. Here, .vertline.V.sub.5 -V.sub.4 .vertline.<.vertline.V.sub.5 .vertline.. Namely, in a conventional voltage switching circuit like the one shown in FIG. 17, the input voltages need to have values V.sub.4 and V.sub.5 in order to generate output voltages V.sub.4 and V.sub.5 (.vertline.V.sub.4 .vertline.<.vertline.V.sub.5 .vertline.). Thus, the absolute value of the input voltage necessary for the voltage generating circuit 53 of this embodiment is smaller than that of the conventional circuit. Accordingly, the component parts of the voltage generating circuit 53 of this embodiment and their peripheral members are not required to have a withstanding property as high as that required by the conventional circuit, thereby achieving reduction in cost and power consumption.

[Embodiment 3]

The following description will explain still another embodiment of the present invention with reference to FIGS. 9 and 10. The structures having the same functions as those in Embodiments 1 and 2 will be designated by the same codes and their description will be omitted.

The voltage generating circuit 53 according to this embodiment has the structure shown in FIG. 1 of Embodiment 1, and is characterized by the capacitor 12 whose capacity is made smaller than a load capacity. The "load capacity" is a capacity given by the sum of the liquid crystal capacity and the element capacity of the liquid crystal panel 50. In this arrangement, the amount of charge for charging the capacitor 12 is not sufficient with respect to the voltage V.sub.1. Therefore, when the switch 11 is switched between the terminals 11a and 11b, voltages V.sub.1 and V.sub.e (V.sub.1 .ltoreq.V.sub.e .ltoreq.V.sub.2) are alternately output as the output voltage V.sub.0 from the output terminal 14 as shown in FIG. 9. Namely, by appropriately setting the capacity of the capacitor 12 within a range smaller than the load capacity, it is possible to achieve a voltage generating circuit 53 capable of outputting the voltage V.sub.1 and any voltage V.sub.e within the range (V.sub.1 .ltoreq.V.sub.e .ltoreq.V.sub.2) alternately, using the input voltages V.sub.1 and V.sub.2 -V.sub.1.

Similarly, in the structure shown in FIG. 7 of Embodiment 2, by arranging the capacity of the capacitor 32 to be smaller than the load capacity, the voltage V.sub.4 and any voltage V.sub.f within a range V.sub.5 .ltoreq.V.sub.f .ltoreq.V.sub.4 are alternately output as the output voltage V.sub.0 from the output terminal 34 as shown in FIG. 10. Namely, by appropriately setting the capacity of the capacitor 32 within the range smaller than the load capacity, it is possible to achieve a voltage generating circuit 53 capable of outputting the voltage V.sub.4 and any voltage V.sub.f within the range (V.sub.5 .ltoreq.V.sub.f .ltoreq.V.sub.4) alternately, using the input voltages V.sub.4 and V.sub.5 -V.sub.4.

Moreover, in Embodiment 1, even when the period T.sub.a1 in which the switch 11 is connected to the terminal 11a is not so long as to permit storing of a sufficient amount of charge on the capacitor 12, effects similar to those mentioned above can be produced by outputting the sum voltage of the voltage V.sub.2 -V.sub.1 and a differential voltage according to the amount of charge charged onto the capacitor 12. Furthermore, in Embodiment 2, even when the period T.sub.b1 in which the switch 31 is connected to the terminal 31c is not so long as to permit storing of a sufficient amount of charge on the capacitor 32, effects similar to those mentioned above can be obtained.

[Embodiment 4]

The following description will explain yet another embodiment of the present invention with reference to FIGS. 11 to 14. The structures having the same functions as those in the above-mentioned embodiments will be designated by the same codes and their description will be omitted.

FIGS. 11 and 12 are circuit diagrams showing examples of the structure of the voltage generating circuit 53 explained in Embodiments 1 and 2, wherein MOS transistors are used as the switches 11 and 31, respectively.

In the structure shown in FIG. 11, a p-channel MOS transistor 114 is provided between the input terminal 10a and the capacitor 12, and an n-channel MOS transistor 115 is positioned between the input terminal 10b and the capacitor 12.

The input voltages to the input terminals 10a, 10b are V.sub.1 and 2V.sub.1 -V.sub.2, respectively. The switching control signal CS1 is input to the p-channel MOS transistor 114, while the switching control signal CS2 is input to the n-channel MOS transistor 115.

As the switching control signals CS1 and CS2 shown in FIG. 13, signals, which are controlled and synchronized so that either of the signals is always in an ON state, are used. When the CS1 is in the ON state and the CS2 is in an OFF state, the voltage V.sub.1 is output to the output terminal 14 through the diode 13 from the input terminal 10a. At this time, the electric potential on the output terminal 14 side of the capacitor 12 is V.sub.1, while the electric potential on the n-channel MOS transistor 115 side thereof is 2V.sub.1 -V.sub.2. Therefore, the capacitor 12 is charged with a differential voltage V.sub.2 -V.sub.1 of the electric potential on the output terminal 14 side and the electric potential on the n-channel MOS transistor 115 side. Next, when the CS2 and CS1 are switched to OFF and ON, respectively, a voltage V.sub.2 that is the sum voltage of the input voltage V.sub.1 from the input terminal 10a and the charged voltage V.sub.2 -V.sub.2 to the capacitor 12 is output to the output terminal 14.

By repeating the above-mentioned operation, the scanning electrode driver input signal V.sub.H output from the output terminal 14 produces a rectangular wave in which the voltages V.sub.1 and V.sub.2 appear alternately.

Similarly, in the structure shown in FIG. 12, an n-channel MOS transistor 124 is provided between the input terminal 30a and the capacitor 32, and a p-channel MOS transistor 125 is positioned between the input terminal 30b and the capacitor 32. With this structure, a rectangular wave in which the voltages V.sub.4 and V.sub.5 appear alternately is output from the output terminal 34. Here, the inverted signal of the switching control signal CS1 (indicated by CS1 in FIG. 12) is input to the n-channel MOS transistor 124, while the inverted signal of the switching control signal CS2 (indicated by CS2 in FIG. 12) is input to the p-channel MOS transistor 125.

The MOS transistor permits high-speed switching with low power consumption. Therefore, the abovementioned structures can further reduce the power consumption of the voltage generating circuit 53, and produce a rectangular wave having sharp leading and trailing edges.

As the switching control signals CS1 and CS2, it is possible to use signals whose inverting timings are different from each other. For example, the switching control signals CS1 and CS2 can be input in the inverting timings shown in FIG. 14. In this case, after a period in which both of the CS1 and CS2 are in the OFF state (the period shown by hatching in FIG. 14), the CS1 or CS2 is turned ON. Accordingly, the CS1 and CS2 can never be in the ON state at the same time. It is thus possible to prevent a through current, and further reduce the power consumption compared to the structure using control signals that are controlled and synchronized so that either of the signals is always in the ON state as shown in FIG. 13.

[Embodiment 5]

The following description will explain other embodiment of the present invention with reference to FIG. 15. The structures having the same functions as those in the above-mentioned embodiments will be designated by the same codes and their description will be omitted.

As illustrated in FIG. 15, a voltage generating circuit of this embodiment has the structure of the voltage generating circuit 53 shown in FIG. 11 of Embodiment 4, but uses an n-channel MOS transistor 153 instead of the diode 13.

In this structure, an n-channel MOS transistor 153 is provided between the input terminal 10a and the output terminal 14, and the inverted signal of the switching control signal CS1 is input to the n-channel MOS transistor 153. In this case, since the timings in which the n-channel MOS transistor 153 is in the ON state and the n-channel MOS transistor 115 is in the OFF state are synchronized, the n-channel MOS transistor 153 turns into the ON state when the voltage V.sub.1 is output, and into the OFF state when the voltage V.sub.2 is output. Accordingly, the voltage generating circuit of this embodiment can perform the same operation as that of the structure using the diode 13. Moreover, since the MOS transistor is used, the loss of power in rectification can be reduced.

Similarly, in above-mentioned Embodiments 1 through 4, it is possible to use the MOS transistor mentioned above, in place of the diode as the rectifying element.

As explained in Embodiments 1 through 5, a voltage generating circuit of the present invention includes an output terminal connected to a display device, two input terminals to which voltages V.sub.a and V.sub.b are input, respectively, a switch positioned between the input terminals and output terminal, for switching the state between the first and second states, a capacitor provided between the switch and the output terminal, and a rectifying element connected to the capacitor in parallel, and is constructed so that the voltage V.sub.a is output from the output terminal and the capacitor is charged when the switch is in the first state, and a voltage V.sub.d as the sum voltage of a voltage V.sub.c charged on the capacitor and one of the voltages V.sub.a and V.sub.b input from the input terminals is output from the output terminal when the switch is in the second state, wherein V.sub.a and V.sub.d have the same polarity with respect to a reference voltage, .vertline.V.sub.a .vertline.<.vertline.V.sub.d .vertline. and .vertline.V.sub.b .vertline.<.vertline.V.sub.d .vertline..

With this structure, since the input voltage is made lower than the output voltage, it is possible to lower the withstand voltage of the peripheral members for switching the voltage. Moreover, this structure can reduce the power consumption by charging the reverse current flowing from the output terminal on the capacitor, and effectively using the charged voltage.

As explained in Embodiments 1 and 2, the abovementioned voltage generating circuit can be constructed so that V.sub.d =V.sub.b +V.sub.c, and V.sub.c =V.sub.a.

With this structure, during a period in which the switch is in the first state, the voltage V.sub.a as one of the input voltages is output from the output terminal, and the voltage V.sub.c across the terminals of the capacitor is made equal to the voltage V.sub.a by the amount of charge stored on the capacitor. Moreover, the voltage V.sub.d to be output when the switch is turned into the second state becomes the sum of the voltage V.sub.b as the other of the input voltages and the voltage V.sub.c charged on the capacitor, i.e., V.sub.a. Namely, it is possible to produce output voltages of two levels, V.sub.a and V.sub.a +V.sub.b, from the input voltages V.sub.a and V.sub.b.

As explained in Embodiments 4 and 5, the abovementioned voltage generating circuit can be constructed so that V.sub.d =V.sub.a +V.sub.c, and V.sub.c =V.sub.a -V.sub.b.

With this structure, during a period in which the switch is in the first state, the voltage V.sub.a as one of the input voltages is output from the output terminal, and the voltage V.sub.c between the terminals of the capacitor is made equal to the voltage V.sub.a -V.sub.b by the amount of charge stored on the capacitor. Moreover, the voltage V.sub.d to be output when the switch is turned into the second state becomes the sum of the voltage V.sub.a and the voltage V.sub.c charged on the capacitor, i.e., V.sub.a -V.sub.b.

Namely, it is possible to produce output voltages of two levels, V.sub.a and 2V.sub.a -V.sub.b, from the input voltages V.sub.a and V.sub.b. In other words, for example, if the input voltages V.sub.a and V.sub.b are V.sub.1 and 2V.sub.1 -V.sub.2, respectively, it is possible to generate V.sub.1 and V.sub.2 as the output voltages.

As explained in Embodiment 3, the above-mentioned voltage generating circuit can be constructed so that the capacity of the capacitor is smaller than the load capacity.

With this structure, it is possible to change the value of one output voltage which has a greater electric potential difference with respect to the reference voltage than the other output voltage, without changing the values of the input voltages.

Besides, as explained in Embodiments 4 and 5, the above-mentioned voltage generating circuit can be constructed using a MOS transistor as the switch.

With this structure, it is possible to achieve high-speed switching, and reduce the power consumed by switching.

Furthermore, as explained in Embodiment 5, the above-mentioned voltage generating circuit can be constructed using a MOS transistor as the rectifying element.

With this structure, it is possible to reduce the loss of power in the rectifying element.

A liquid crystal display device according to the present invention includes the above-mentioned voltage generating circuit, and uses non-linear elements as the switching elements in the pixels of the liquid crystal panel.

Thus, even the liquid crystal display device using the non-linear elements as the switching elements in the pixels of the display panel can have the benefit of the use of the above-mentioned voltage generating circuit. It is thus possible to provide a low-power-consuming liquid crystal display device at low cost.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.