System and Method for Generating Many Ones Codes With Hamming Distance After Precoding

1. Field of the Invention

The present invention relates generally to methods for transmission of a digital data signal over partial response maximum likelihood (PRML) data channels. More particularly, the present invention relates to a system and method designed for use with a precoder such that the precoder produces codes with a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. Still, more particularly, the present invention relates to an encoding system and method that produces at least a predetermined number of ones at the output of the channel to help derive a clock signal from the digital data signal.

2. Description of the Related Art

The use of PRML channels is well-known in the art as a method for transmitting data. There are several prior art methods for coding and detection in PRML channels. These prior art methods vary in their performance (error probability), and also vary in transmission rate.

The prior art often uses precoders to eliminate error propagation in PRML channels. For example, a 1/(1.sym.D) precoder over a 1-D channel produces non-zero channel output for each non-zero precoder input, and produces a zero channel output for each zero precoder input. In magnetic recording, a "1" channel input denotes magnetic polarization in one direction and a "0" channel input denotes magnetic polarization in the opposite direction. If a precoder is not used, then errors persist continually as the magnetic polarization directions are switched. Commonly, a precoder is used to eliminate this problem and exemplary precoders include: a 1/(1.sym.D) precoder for a 1-D channel; a 1/(1.sym.D) precoder for a (1-D)(1+D).sup.3 channel; a 1/(1.sym.D).sup.2 precoder for a 1-D.sup.2 channel; and 1/(1.sym.D.sup.4) precoder for a (1-D).sup.4 channel. However, such prior art precoding methods do not produce codes which have a Hamming distance greater than one for the channel. Therefore, there is a need for a precoder that produces codes having a Hamming distance greater than one at the input of a PRML channel to thereby improve performance and decrease error probability.

An additional problem with the prior art methods is their inability to provide sufficient clocking information at the output of the PRML channel. Clocking is the extrapolation of clock frequency and phase based on the received signal. Long sequences of consecutive zeros at the output of the PRML channel make clock detection difficult, and sometimes impossible. In contrast, a large number of ones or transitions at the output of the PRML channel can significantly improve clocking performance.

Accordingly, there exists a need for a system and method for producing many ones codes with a Hamming distance greater than one after precoding. Such codes would provide the dual advantages of improved channel performance and clock detection.

The present invention is a system and method for encoding and decoding input strings to improve the performance of a PRML data channel and also provide at least a predetermined number of ones at the output of the PRML data channel to assist in clocking. This improved channel performance is accomplished by encoding and decoding the binary digital signals such that after precoding the strings will have a Hamming distance greater than one at the output of the precoder, and thereby eliminate error events with a small distance at the output of the PRML channel. Additionally, the present invention advantageously provides a unique system and method for encoding and decoding binary digital signals such that the coded sequence at the output of the PRML data channel will have at least a predetermined number of ones to assist in clock and gain detection.

The system of the present invention preferably comprises an encoder, a precoder, a PRML data channel, a detector, and a decoder. An input signal is received by the encoder. The encoder applies encoding such that the code string after being modified by the precoder has a Hamming distance greater than one and at least a predetermined number of ones at the output of the PRML data channel. The encoder, for many input signals, generates a code string by adding one or more control bits and outputs the code string to the precoder. The control bits are situated by design to locations inside the code string where they are less susceptible to noise. The encoder preferably comprises a serial-to-parallel converter, a code generator, and a parallel-to-serial converter. In a preferred embodiment, the code generator produces a maximal ones code having rate of 16/18. The present invention also includes a decoder that is coupled to the output of the detector. The decoder restores a received string to the format that it had at the input to the encoder by performing a function that is the "inverse" of the encoder.

The method of the present invention preferably includes a number of methods. One such method is directed to encoding bit strings and comprises the steps of: 1) encoding an input string by adding at least two bits such that a many ones code that has a Hamming distance greater than one after precoding is produced; 2) transmitting the encoded signal through a precoder; 3) sending the precoded sequence through a channel to generate a channel output sequence; 4) producing a detector output sequence by applying the channel output sequence to a detector; and 5) decoding the detector output sequence. Another method is directed to reducing the maximum number of consecutive zeros at the output of the PR channel and comprises the steps of: 1) encoding an input string by adding at least one bit such that a many ones code is produced; 2) transmitting the encoded signal through a precoder; 3) sending the precoded sequence through a channel to generate a channel output sequence; 4) producing a detector output sequence by applying the channel output sequence to a detector; and 5) decoding the detector output sequence. Still another method is directed to using encoder and decoder maps to generate maximal ones codes having a Hamming distance greater than one after precoding and comprises the steps of: 1) encoding and input string using a predetermined encoder map; 2) transmitting the encoded signal through a precoder; 3) sending the precoded sequence through a channel to generate a channel output sequence; 4) producing a detector output sequence by applying the channel output sequence to a detector; and 5) decoding the detector output sequence using a predetermined decoder map.

The present invention is particularly advantageous over the prior art because for most input signals it provides a systematic encoding scheme in which many of the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The decoder is likewise easy to construct and can be implemented in a circuit that simply discards the control bits.

The present invention has other advantages and features which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a communication system of the present invention including an encode, a precoder, a partial response channel, a detector, and a decoder;

FIG. 2 is a block diagram of a preferred embodiment of the encoder constructed according to the present invention;

FIG. 3 is a block diagram of a first embodiment of a code generator used in the preferred embodiment of the encoder and constructed according to the present invention to generate a first code, Code 1;

FIG. 4 is a block diagram of a second embodiment of the code generator used in the first embodiment of the encoder and constructed according to the present invention to generate the first code;

FIG. 5 is a block diagram of a preferred embodiment of a decoder constructed according to the present invention for use in conjunction with the preferred embodiment of the encoder;

FIG. 6 is a block diagram of a first embodiment of a code de-converter used in the preferred embodiment of the decoder and constructed according to the present invention to decode the first code;

FIG. 7 is a block diagram of a third embodiment of the code generator constructed according to the present invention to generate a second code, Code 2;

FIG. 8 is a block diagram of a second embodiment of a code de-converter constructed according to the present invention for use in conjunction with the third embodiment of the code generator;

FIG. 9 shows a fourth embodiment of the code generator constructed according to the present invention to generate a third code, "Code 3";

FIGS. 10-14 are mapping diagrams illustrating the first, second, third, fourth and fifth mapping circuits that generate the mapping functions of map1 through map5 for the fourth embodiment of the code generator illustrated in FIG. 9;

FIGS. 15A and 15B are a block diagram of a multiplexer used in the forth embodiment of the code generator constructed according to the present invention to generate the third code;

FIG. 16 is a block diagram of an exemplary one of the seventeen 5-way multiplexers forming part of the multiplexer used in the fourth embodiment of the code generator;

FIG. 17 is a block diagram of a preferred embodiment for the first controller constructed according to the present invention for use in conjunction with the fourth embodiment of the code generator;

FIG. 18 is a block diagram of a preferred embodiment for the mod adder according to the present invention for use in conjunction with the fourth embodiment of the code generator shown in FIG. 9;

FIG. 19 is a block diagram of a third embodiment of the code de-converter constructed according to the present invention for use in conjunction with the fourth embodiment of the code generator, and for decoding "Code 3";

FIGS. 20-24 are block diagrams illustrating the first, second, third, fourth, and fifth mapping circuits of third embodiment of the code de-converter for mapping functions of MAP1 through MAP5 and forming part of the third embodiment of the code de-converter shown in FIG. 19;

FIGS. 25A and 25B are a block diagram of a multiplexer constructed in accordance with the present invention for use in conjunction with the third embodiment of the code de-converter;

FIG. 26 is a block diagram of one of the sixteen 5-way multiplexers forming part of the multiplexer of FIG. 25 constructed in accordance with the present invention for use in conjunction with the third embodiment of the code de-converter;

FIG. 27 is a block diagram of a second controller constructed according to the present invention for use in conjunction with the third embodiment of the code de-converter shown in FIG. 19;

FIGS. 28 and 29 show a fifth embodiment of the code generator constructed according to the present invention to generate a fourth code, "Code 4";

FIGS. 30 and 31 show a fourth embodiment of the code de-converter constructed according to the present invention to decode words encoded using Code 4, and for use with the code generator of FIGS. 28 and 29;

FIGS. 32-35 shows a seventh embodiment of the code generator constructed according to the present invention generate a fifth code, "Code 5;"

FIG. 36 shows a fifth embodiment of the code de-converter constructed according to the present invention to decode words encoded using Code 5, and for use with the code generator of FIGS. 32-25;

While the present invention will now be described with reference to a communication system encountered in magnetic recording practice, those skilled in the art will realize that the present invention can be incorporated into any one of a variety of systems for transmitting binary data.

Referring now to FIG. 1, a preferred embodiment of a communications system 10 constructed in accordance with the present invention is shown. The preferred embodiment of the system 10 comprises an encoder 12, a precoder 14, a partial response (PR) channel 16, a detector 18, and a decoder 20. The PR channel 16 preferably further comprises a low pass filter 40, a noise source 42 and an adder 44. The encoder 12 produces novel many ones codes with Hamming distance greater than one. The novel many ones codes are particularly advantageous because after precoding, the coded sequence output by the channel 16 has at least a predetermined number of ones. More specifically, the predetermined minimum number of ones at the output of the PR channel 16 contribute to clocking by providing transitions from which frequency and phase information can be extracted. The preferred embodiment of the present invention preferably has eleven exemplary many ones codes, as will be described in detail below. These codes are defined in TABLE I as follows:

Referring to TABLE I, the channel equation is the transfer function of the PR channel filter, where D is a delay operator; the Rate x/y means the encoder takes x bits and outputs y bits; 0 Mod M is the number of ones after precoding; N is the minimal number of ones at the output of the PR channel; Z is the maximum number of consecutive zeros at the output of the PR channel; Z.sub.i is the maximum number of consecutive zeros in even or odd bit positions at the output of the PR channel; and E is the number of bytes of input data that can be corrupted through typical channel errors.

Except for codes 9 and 10, the codes of the present invention generate a Hamming distance of 2 after precoding. Over a 1-D channel, it is desirable to preclude +/-(. . . 010-10 . . . ) error events at the output of the channel. Codes having M=3, codes 5 and 6, provide this desired property. Further, if codes 5 and 6 are used over a PRML channel, in an interleaved manner, then error events +/-(. . . 01000-10 . . . ) will be precluded at the channel output. This again is very desirable. The elimination of the above mentioned error events further improved the overall performance of the system.

As shown in FIG. 1, an input signal on line 22 is transmitted to an input of the encoder 12. The input signal or data is preferably in the form of an input sequence of bits {b.sub.1 b.sub.2 b.sub.3 . . . }. The encoder 12 produces and outputs an encoded sequence of bits {v.sub.1 v.sub.2 v.sub.3 . . . } from the input signal. The coded sequence is preferably one of eleven many ones codes listed in TABLE I. For ease of understanding, the remaining components of the system 10 will now be described before describing the preferred embodiments of the encoder 12 and the decoder 20 in detail.

Referring again to FIG. 1, the output of the encoder 12 is coupled to provide the coded sequence on line 24. The precoder 14 has an input and an output. The input of the precoder 14 is coupled to line 24 to receive the encoded sequence {v.sub.1 v.sub.2 v.sub.3 . . . }. The precoder 14 generates a precoded sequence {x.sub.1 x.sub.2 x.sub.3 . . . }, based on the encoded sequence {v.sub.1 v.sub.2 v.sub.3 . . . }. The precoder 14 preferably takes one of two forms, either a 1/(1.sym.D) precoder or a 1/(1.sym.D.sup.2) precoder. Those skilled in the art will realize that the precoder 14 may be any one of a variety of conventional precoders. For such conventional precoders, the many ones code must be generated such that at least a predetermined number of ones are present after encoding and precoding by the encoder 12 and the precoder 14, respectively. If the precoder 14 is 1/(1.sym.D), then the precoded sequence and the coded sequence are related by x.sub.i =v.sub.i .sym.x.sub.i-1. On the other hand, if the precoder 14 is 1/(1.sym.D.sup.2), then they are related as x.sub.i =v.sub.i .sym.x.sub.i-2. The output of the precoder 14 is coupled by line 26 to provide the precoded sequence {x.sub.1 x.sub.2 x.sub.3 . . . } to the PR channel 16.

The preferred embodiment of the PR channel 16 has an input and an output, and further comprises: the filter 40, the noise source 42, and the adder 44. The filter 40 has an input and an output. The input of the filter 40 forms the input of the PR channel 16 and is coupled to line 26 to receive the precoded sequence from the precoder 14. In the preferred embodiment, the filter 40 is either a 1-D or a 1-D.sup.2 filter. The filter 40 produces a filter sequence, {y.sub.1 y.sub.2 y.sub.3 . . . }. If the filter 40 is 1-D, then the filter sequence {y.sub.1 y.sub.2 y.sub.3 . . . } and the precoded sequence {x.sub.1 x.sub.2 x.sub.3 . . . } are related by y.sub.i =x.sub.i -x.sub.i-1, but if the channel filter 40 is 1-D.sup.2, then the filter sequence {y.sub.1 y.sub.2 y.sub.3 . . . } and the precoded sequence {x.sub.1 x.sub.2 x.sub.3 . . . } are related by y.sub.i =x.sub.i -x.sub.i-2. The output of the filter 40 is coupled to line 46 which is in turn coupled to a first input of the adder 44. A second input of the adder 44 is coupled to line 45 to receive a noise signal n(t) from the noise source 42. The noise source 42 produces a noise sequence {n.sub.1 n.sub.2 n.sub.3 . . . } that is output on line 45. The adder 44 adds the noise signal n(t) and the filter 40 output to produce a channel sequence {r.sub.1 r.sub.2 r.sub.3 . . . } on line 28. The channel sequence, is the sum of the filter sequence and the noise sequence, i.e., r.sub.i =y.sub.i +n.sub.i.

The system 10 also includes the detector 18 having an input and an output. The input of the detector 18 is coupled to line 28 to receive the channel sequence. The detector 18 is preferably a Viterbi detector, but may also be a noise predictive Viterbi detector or any other similar detector. The detector 18 generates a detector sequence {u.sub.1 u.sub.2 u.sub.3 . . . } which is a reproduction of the encoded sequence {v.sub.1 v.sub.2 v.sub.3 . . . }. Finally, the output of the detector 18 is provided on line 30 to the input of the decoder 20. The decoder 20 performs the inverse of the encoder 12 to reproduce the input signal. The output of the decoder 20 is provided on line 32 as an output signal. The decoder 20 generates a decoded sequence {b.sub.1 b.sub.2 b.sub.3 . . . } which is a reproduction of the input data. The decoder 20 has a variety of embodiments each of which will be described in more detail below.

Referring now to FIG. 2, a first embodiment of an encoder 12a of the present invention is shown. In the first embodiment, the encoder 12a is a finite state machine that performs the encoding using a first code, code 1, that has a rate 16/18. As described in APPENDIX A, the minimal number of ones per code word at the output of the channel filter 40 is 9. This result follows from the concurrent constraints of a Hamming distance of 2 after precoding and the 16/18 rate. The encoder 12a takes sixteen bits, {b.sub.16k+1 b.sub.16k+2 b.sub.16k+3, . . . , b.sub.16k+16 } every time k.gtoreq.0, and produces eighteen bits {v.sub.18k+1 v.sub.18k+2 v.sub.18k+3, . . . , v.sub.18k+18 }. We use the notation of v.sub.i (k), i.epsilon.{1, . . . , 18} for v.sub.18k+i and the notation of b.sub.i (k), i.epsilon.{1, . . . , 16} for b.sub.16k+i.

As shown in FIG. 2, the first embodiment of the encoder 12a includes a serial-to-parallel converter 150, a parallel-to-serial converter 152, and a code generator 154. The serial-to-parallel converter 150 has an input and plurality of outputs, and is preferably a one-to-sixteen converter. The serial-to-parallel converter 150 receives a serial string having a predetermined number of bits, and provides those bits simultaneously, or in parallel, at its outputs. The input of the serial-to-parallel converter 150 is coupled to line 22 to receive the input sequence {b.sub.1 b.sub.2 b.sub.3 . . . }. Each of the outputs of the serial-to-parallel converter 150 provides a single bit of the input sequence such that sixteen bits are output. Each of the outputs of the serial-to-parallel converter 150 is coupled to a respective input of the code generator 154 to generate a codeword v by signal lines 156.

The parallel-to-serial converter 152 preferably has a plurality of inputs (eighteen) and an output. The parallel-to-serial converter 152 receives a predetermined number of bits in parallel and converts them into the encoded sequence {v.sub.1 v.sub.2 v.sub.3 . . . }. The output of the parallel-to-serial converter 152 is coupled to line 24 to provide the encoded sequence. The code generator 154 preferably has a plurality of inputs coupled to receive sixteen bits of the input sequence {b.sub.1 b.sub.2 b.sub.3 . . . } via lines 156 from the serial-to-parallel converter 150. The code generator 154 produces two additional code bits, v.sub.6 and v.sub.10. Similarly, each of the outputs of the code generator 154 are coupled by a respective signal line 158 to a corresponding input of the parallel-to-serial converter 152. These additional bits are sent to the parallel-to-serial converter 152 and form part of the encoded sequence {v.sub.1 v.sub.2 v.sub.3 . . . }. The code generator 154 in the present invention has two embodiments 154a and 154b, which will be described in more detail below with references to FIGS. 3 and 4.

Referring now to FIG. 3, a first embodiment of the code generator 154a that generates the code bits v.sub.1 through v.sub.18 of Code 1 is shown. The code generator 154a will now be described using the following notations (x denotes the complement of x):

input data=b=(b.sub.1, . . . ,b.sub.16),

current state=cs,

codeword=v=[v.sub.1 . . . v.sub.18 ],

next state=ns,

w=weight of b=number of ones in b, and

[w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ]=binary representation of w, where w.sub.0 is the most significant bit (MSB) and w.sub.4 is the least significant bit (LSB).

The current state cs is used to produce the current codeword v, the next state ns is used as a current state cs by the code generator 154a to produce the next v. The initial current state cs.sub.0 is obtained from cs.sub.0 =x.sub.-1 .sym.x.sub.-2, where x.sub.-2 and x.sub.-1 are the initial conditions of the precoder 14. The logic operator .sym. means Modulo-2 summing or addition. The operation is the same as binary addition but with no carries or borrows. Thus, 1.sym.1=0 with no carry. The operation can be implemented by a two-input Exclusive-OR logic gate.

The code generator 154a is further characterized by:

The first embodiment for the code generator 154a implements equations 1-3 in hardware and comprises: an adder 160, a one-bit latch 162, a first modulo adder 164, and a second modulo adder 168. The functions performed by the adder 160, the latch 162, the first modulo adder 164, and the second modulo adder 168 all be implemented using techniques well-known to those skilled in the art.

The adder 160 receives the input data b, determines the number of ones in b, then outputs w=[w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ] (hereinafter "weight bits"). The weight bits w.sub.0 and w.sub.1 provided by the adder 160 are ORed together by an OR gate 170 to produce a binary 1 if the number of ones in b is .gtoreq.8, or a binary 0 if the number of ones in b is <8. In either case, the result is inverted by an inverter 172 whose output is coupled to a plurality of Exclusive-OR gates 174-190 where it is Exclusive-ORed with each bit of the input data b. Specifically, the input data bits [b.sub.1 b.sub.2 b.sub.5 b.sub.8 b.sub.11 b.sub.12 b.sub.15 b.sub.16 ] are Exclusive-ORed by a respective Exclusive-OR gate 174-182 with the output of the inverter 172 to produce code bits [v.sub.1 v.sub.2 v.sub.5 v.sub.9 v.sub.13 v.sub.14 v.sub.17 v.sub.18 ], respectively. The code bits [v.sub.1 v.sub.2 v.sub.5 v.sub.9 v.sub.13 v.sub.14 v.sub.17 v.sub.18 ] are then coupled to the first modulo adder 164 to produce the additional code bit v.sub.6 in accordance with equation 1. Likewise, the input data bits [b.sub.3 b.sub.4 b.sub.6 b.sub.7 b.sub.9 b.sub.10 b.sub.13 b.sub.14 ] are respectively Exclusive-OR by Exclusive-OR gates 183-190 with the output of the inverter 172 produce the code bits [v.sub.3 v.sub.4 v.sub.7 v.sub.8 v.sub.11 v.sub.12 v.sub.15 v.sub.16 ]. The code bits [v.sub.3 v.sub.4 v.sub.7 v.sub.8 v.sub.11 v.sub.12 v.sub.15 v.sub.16 ] are then provided to the second modulo adder 162 to produce the next state ns in accordance with equation 2. The current state cs is then applied as an input to the first modulo adder 164 along with the code bits [v.sub.1 v.sub.2 v.sub.5 v.sub.9 v.sub.13 v.sub.14 v.sub.17 v.sub.18 ] in accordance with equation 1. The next state ns is applied as input to the latch 162 produce the current state cs. Finally, the output of the OR gate 170 is Exclusive-ORed with the output of the inverter 172 by Exclusive-OR gate 178 produce the additional code bit v.sub.10. Code bit v.sub.10 is provided as input into the first modulo adder 164. The code generator 154a, as described above, will produce the additional code bits v.sub.6 and v.sub.10 which form part of the encoded sequence {v.sub.1 v.sub.2 v.sub.3 . . . } produced at the output 24 of the parallel-to-serial converter 152.

Referring now to FIG. 4, a second embodiment of the code generator 154b for code 1 is shown. The code generator 154b is based on the same equations as embodiment 154a, except we let v'=[v'.sub.1 . . . v'.sub.18 ] denote the last codeword sent through the 1/(1.sym.D.sup.2) precoder and compute the current state cs from the equation

where x'.sub.17 and x'.sub.18 are the output of the precoder 14 corresponding to the code bits v'.sub.17 and v'.sub.18, respectively. The initial current state is cs.sub.0 =x'.sub.-1 .sym.x'.sub.-2 as in the first embodiment.

As shown in FIG. 4, the second embodiment of the code generator 154b is similar to the first embodiment of the code generator 154a but without the second modulo adder 168 computing the next state ns. Therefore, like part numbers have be used to indicate like parts having the same function in the second embodiment. Instead of computing the next state ns, the bits x'.sub.17 and x'.sub.18 are feedback from the output 26 of the precoder 14 as shown in FIG. 1, and are Exclusive-ORed in an Exclusive-OR gate 192 produce the current sate cs which is then input into the first modulo adder 164 produce the additional code bit v.sub.6. The x'.sub.17 and x'.sub.18 bits are shown for illustration purposes as being connected to line 26, however, those skilled in the art will realize that latch and other combinational logic are used to capture the x'.sub.17 and x'.sub.18 bits.

Referring now to FIG. 5, a preferred embodiment of the decoder 20 constructed according to the present invention for decoding signals is shown. The decoder 20 preferably comprises a serial-to-parallel converter 500, code de-converter 502, and a parallel-to-serial converter 504. The serial-to-parallel converter 500 preferably has an input and eighteen outputs, and converts an input string into eighteen parallel bits. The input of the serial-to-parallel converter 500 is coupled to line 30 to receive the detector sequence {u.sub.1 u.sub.2 u.sub.3 . . . } output by the detector 18. Each of the outputs of the serial-to-parallel converter 500 are coupled by a respective signal line 506 to a respective input of the code de-converter 502. The code de-converter 502 preferably has a plurality (eighteen) of inputs and a plurality (sixteen) of outputs. The inputs of the code de-converter 502 are coupled to receive eighteen of the detector sequence {u.sub.1 u.sub.2 u.sub.3 . . . }. The sixteen outputs of the code de-converter 502 are likewise coupled to respective inputs of the parallel-to-serial converter 504. The parallel-to-serial converter 504 preferably has sixteen inputs and an output, and converts the sixteen input parallel bits into a string. The output of the parallel-to-serial converter 504 is coupled to line 32 to provide the decoded sequence {b'.sub.1 b'.sub.2 b'.sub.3 . . . }.

Referring now to FIG. 6, a first embodiment of the code de-converter 502a which reconstructs the input data b is shown. The code de-converter 502a can be characterized by the following equations: ##EQU2##

As shown in FIG. 6, the bit u.sub.10 is inverted by an inverter 600. The output of the inverter 600 is then Exclusive-ORed with bits u.sub.1 through u.sub.18, excluding bits u.sub.10 and u.sub.6, using a plurality of Exclusive-OR gates 602-617. Thus, the code de-converter 502a drops the u.sub.6 bit, and uses the u.sub.10 bit to regenerate the input sixteen bit code from eighteen bits of data.

While the encoders and decoders of the system 10 have and will be described as including serial-to-parallel converters and parallel-to-serial converters, those skilled in the art will realize that the present invention may be constructed without use of such converters. Since the control bits are assigned to one of the bits for each code, an alternate embodiment of the encoder does not require the converters. Rather, as bits enter into the alternate embodiment of the encoder, they simply pass through except at time instances where a control bit needs to be inserted. At such an instance, the input stream is stopped (via such method as clock gapping) and the control bit is computed and inserted at the output of the encoder.

Referring now to FIG. 7, a third embodiment of the code generator 154c will be described. The third embodiment of the code generator 154c uses the properties of Code 2 to reduce the number of consecutive zeros present in odd or even bit positions at the output of the PR channel 16 by utilizing a vector of weight 8 instead of codeword v. The third embodiment of the code generator 154c takes sixteen bits {b.sub.16k+1 b.sub.16k+2 b.sub.16k+3, . . . ,b.sub.16k+16 } every time k.gtoreq.0, and produces eighteen bits {v.sub.18k+1 v.sub.18k+2 v.sub.18k+3, . . . ,v.sub.18k+18 }. We use the notation of v.sub.i (k), i.epsilon.{1, . . . ,18} for v.sub.18k+i and the notation of b.sub.i (k), i.epsilon.{1, . . . ,16} for b.sub.16k+i.

Using the same notations as in the details of Code 1, the code generator 154c of code 2 is characterized as follows:

As shown in FIG. 7, the third embodiment of the code generator 154c can be implemented with either code generator 154a or 154b as described above in FIGS. 3 and 4, a multiplexer 700, a first AND gate 702, a second AND gate 706 and a NOR gate 704. The signal g=[g.sub.1 g.sub.2 g.sub.3 g.sub.4 g.sub.5 g.sub.7 g.sub.8 g.sub.9 g.sub.11 . . . f.sub.18 ] is the output of the "Code 1" code generator 154a or 154b; the signal f=[f.sub.1 f.sub.2 f.sub.3 f.sub.4 f.sub.5 f.sub.7 f.sub.8 f.sub.9 f.sub.11 . . . f.sub.18 ] is .beta.=110001100000110011; the control signal c.sub.1 is given by ##EQU4##

The input date b to be encoded is applied in parallel fashion to the inputs of the code generator 154c as shown in FIG. 7. The signal g at the output of "Code 1" code generator 154a/154b is applied to a first set of inputs of the multiplexer 700, in parallel fashion. The "Code 1" code generator 154a/154b used in this third embodiment is also modified in that the "Code 1" code generator 154a/154b outputs the c.sub.S signal. The signal f is applied to a second set of inputs of the multiplexer 700, also in parallel fashion. The signal f can be hard-wired to the inputs of the multiplexer 700. When the control signal c.sub.1 is binary 0, then v is defined by g. On the other hand, when the control signal c.sub.1 is binary 1, then v is defined by f. More particularly, when the input data b=[0101001001010101], and cs=1, the codeword f is steered to the output of the multiplexer 700. The control signal c.sub.1 is generated using by ANDing the bits [b.sub.2 b.sub.4 b.sub.7 b.sub.10 b.sub.12 b.sub.14 b.sub.16 ] using the second AND gate 706. Also, the bits [b.sub.1 b.sub.3 b.sub.5 b.sub.6 b.sub.8 b.sub.9 b.sub.11 b.sub.13 b.sub.15 ] are NORed together using a NOR gate 704. The outputs of the second AND gate 706 and the NOR gate 704 are then ANDed together along with the signal cs in the first AND gate 702 to produce the control signal c.sub.1.

In sum, the third embodiment of the code generator 154c for generating a second code, Code 2, is coupled to the precoder 14 and followed by the PR channel, and produces the following parameters: N=8, Z=17, Z.sub.i =16, and E=3. Additionally, code 2 generates a Hamming distance of 2 after precoding. Finally, code 2 has only one codeword generating 8 ones at the output of the PR channel; the rest of its code words generate at least 9 ones for improved clocking.

Referring now to FIG. 8, a second embodiment of a code de-converter 502b constructed according to the present invention for decoding signals encoded with Code 2 is shown. The code de-converter 502b preferably comprises a "Code 1" de-converter 502a as described above in FIG. 6, a multiplexer 800, a first AND gate 802, a second AND gate 804, and a NOR gate 806. The code de-converter 502b for Code 2 is characterized as follows: ##EQU5##

The signal h=[h.sub.1 h.sub.2 h.sub.3 h.sub.4 h.sub.5 h.sub.7 h.sub.8 h.sub.9 h.sub.11 . . . h.sub.18 ] is output data generated by the Code 1 de-converter 502a; the signal i=[i.sub.1 i.sub.2 i.sub.3 i.sub.4 i.sub.5 i.sub.7 i.sub.8 i.sub.9 i.sub.11 . . . i.sub.16 ] is [0101001001010101]; the control signal c.sub.2 is given by ##EQU6##

As shown in FIG. 8, the detector sequence is applied in parallel fashion to the inputs of the de-converter 502a. The output of the de-converter 502a is applied to a first set of inputs of the multiplexer 800, in parallel fashion. The signal i is applied to a second set of inputs of the multiplexer 800, also in parallel fashion. The signal i can be hard-wired to the inputs of the multiplexer 800. When u=110001100000110011, then c.sub.2 =1, and the signal i is steered to the output of the multiplexer 800. Similarly, when the control signal c.sub.2 =0, then b is defined by the signal h. The control signal c.sub.2 is generated by ANDing the bits [u.sub.1 u.sub.2 u.sub.6 u.sub.7 u.sub.13 u.sub.14 u.sub.17 u.sub.18 ] using the first AND gate 802. Also, the bits [u.sub.3 u.sub.4 u.sub.5 u.sub.8 u.sub.9 u.sub.10 u.sub.11 u.sub.12 u.sub.15 u.sub.16 ] are NORed together using the NOR gate 806. The outputs of the first AND gate 802 and the NOR gate 806 are then ANDed together by the second AND gate 804 to produce the control signal c.sub.2.

Referring now to FIG. 9, a fourth embodiment of a code generator 154d constructed according to the present invention for encoding signals encoded with a third code, "Code 3" is shown. The code generator 154d preferably comprises an adder 900, a first controller 902, a mod adder 904, a plurality of mapping circuits 906, 908, 910, 912, and 914, a multiplexer 916 and a plurality of inverters 918, 920. Recall that in Code 1, the input data b is partitioned into two sets according to weight w. Let P.sub.1 contain input data of w.gtoreq.8, and P.sub.2 contain input data of w<8. The fourth embodiment of the code generator 154d for Code 3 is characterized as follows:

Let the input data b be partitioned into three sets, S.sub.1, S.sub.2, and S.sub.3, where

Unlike Code 1 and Code 2, which use a partitioning based on a threshold weight of 8, Code 3 employs a partitioning based on a threshold weight of 6. Specifically, let R.sub.1 denote the set of input data of weight w.gtoreq.6; let R.sub.2 denote the set of input data of w<6; and let A, H, and E denote the following sets:

Now, Code 3 partitions the input data b into 5 sets, Q.sub.1 through Q.sub.5, where

Code 3 can be viewed as comprising 5 maps, map 1 through map 5, operating on distinct sets of input Q.sub.1 through Q.sub.5, respectively. Using the same notations as in the details of Code 1 and Code 2, and using the sets defined above. Code 3 can be further characterized as follows (denotes AND and denotes OR):

where the current state cs can be generated in two ways as described earlier for code 1.

Referring now to TABLE II, column 2 defines map1, column 3 defines map2, column 4 defines map3, column 5 defines map4, and column 6 defines map5. For example, map3 generates v.sub.7 according to v.sub.7 =(w.sub.1 w.sub.2 w.sub.3 )w.sub.4.

As shown in FIG. 9, the fourth embodiment of the code generator 154d preferably comprises an adder 900, a first controller 902, a mod adder 904, a first mapping circuit 906, a second mapping circuit 908, a third mapping circuit 910, a fourth mapping circuit 912, a fifth mapping circuit 914, a multiplexer 916 and a first and second inverters 918, 920. The adder 900 has a plurality of inputs coupled to receive the input data b and computes the weight w of b, and generates the weight bits [w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ] as outputs. The output of adder 900 is coupled to inputs of the first controller 902, inputs of the third mapping circuit 910, and inputs of the fourth mapping circuit 912. The adder 900 and first controller 902 can be considered a partitioning unit, as will be recognized by those skilled in the art, since they define which of the five maps will be used to generate the output data word. The output of adder 900 is also input to inverter 918, which represents a plurality of inverters, for providing the complement of the weight bits. The output of the inverter 918 is also coupled to inputs of the third mapping circuit 910, and the fourth mapping circuit 912. The first, second, third, fourth and fifth mapping circuits 906, 908, 910, 912 and 914 perform the functions of map1 through map5 of TABLE II based on input data b, its complement b provided by the output of inverter 920, and the variable p. Note that map3 and map4 are a function of the weight bits [w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ] and their complement. The controller 902 generates five control variables, q.sub.1 through q.sub.5, which are based on input data b, and the weight bits [w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ]. The generation of the control bits q.sub.1 to q.sub.5 will be described below in more detail with reference to FIG. 17. Only one of the five control bits or variables is a logical one at any given time, and the rest are logical zeros. If the input data b is in the set Q.sub.i,1.ltoreq.i.ltoreq.5, then q.sub.i =1 and the rest of the variables are zero. The outputs of each of the mapping circuits 906, 908, 910, 912 and 914 is coupled to a respective data inputs of the multiplexer 916, and the output of the controller 902 are coupled to the control inputs of the multiplexer 916. The multiplexer 916 reflects one of its input vectors map1v through map5v in response to the control bits q.sub.1 to q.sub.5 and produces the codeword v at the output. The selection is based on control variables q.sub.1 through q.sub.5. In other words, if q.sub.i =1, where 1.ltoreq.i.ltoreq.5, then the multiplexer 916 selects v=map1v. The mod adder 904 31 generates the variable p according to equation 13 by performing modulo addition on identified bits of the codeword v and the c.sub.S signal. Referring now to FIG. 10, a preferred embodiment for the first mapping circuit 906 is shown. TABLE II shows the mapping from column 2 to column 1. The first mapping circuit 906 is preferably a hard wiring of the input data b, the p bit and a logical "1" to corresponding bits of the codeword v consistent with TABLE II. The input data b is mapped directly to map1v, except for bits map1v.sub.6 and map1v.sub.10. The variable p computed according to equation 13 and is mapped to bit map1v.sub.6, and a binary "1" is mapped to bit map1v.sub.10. The bits map1v.sub.1 to map1v.sub.18 are the outputs of the first mapping circuit 906. When the input data b is in set Q.sub.1 , then the controller 902 generates q.sub.1 =1 and q.sub.2 =q.sub.3 =q.sub.4 =q.sub.5 =0. The multiplexer 916 responds by selecting map1v to be output to v. The vector map1v is generated using b and p according to column 2 in TABLE II.

Referring now to FIG. 11, a preferred embodiment for the second mapping circuit 908 is shown, and TABLE II shows the mapping from column 3 to column 1 of TABLE II which is performed in the second mapping circuit 908. Similar, to the first mapping circuit 906, the second mapping circuit 908 is preferably a hard wiring of the input data b, the p bit and a logical "1" to corresponding bits of the codeword v. The input data b is mapped directly to map2v, except for bits map2v.sub.6 and map2v.sub.10. The variable p computed according to equation 13 is mapped to bit map2v.sub.6, and a binary 0 is mapped to bit map2v.sub.10. When the input data b is in set Q.sub.2 then the controller 902 generates q.sub.2 =1 and q.sub.1 =q.sub.3 =q.sub.4 =q.sub.5 =0. The outputs are coupled to the control inputs of the multiplexer 916 select map2v to be output to v. The map map2v is generated using b and p according to column 3 in TABLE II.

Referring now to FIG. 12, a preferred embodiment for the third mapping circuit 910 is shown. The third mapping circuit 910 generates the output map3v according to the mapping from column 4 to column 1 of TABLE II. The input data bits [b.sub.11 b.sub.12 b.sub.13 b.sub.14 b.sub.15 ] are mapped via handwriting directly to bits [map3v.sub.11 . . . map3v.sub.15 ]. respectively. Similarly, the input bit b.sub.16 is mapped directly to map3v.sub.17. The variable p computed, according to equation 13, is mapped to bit map3v.sub.6, and a binary 0 is mapped to bit map3v.sub.10. The input data bits [b.sub.2 b.sub.4 b.sub.7 b.sub.10 ] are Exclusive-ORed respectively by Exclusive-OR gates 1200, 1202, 1204 and 1206 with the result of the Boolean operation w.sub.1 (w.sub.2 w.sub.3) performed by AND gate 1208 and OR gate 1210 on weight bits [w.sub.1 w.sub.2 w.sub.3 ]. The result of the Exclusive-OR operation performed by Exclusive-OR gates 1200, 1202, 1204 and 1206 is further mapped to the bits [map3v.sub.2 map3v.sub.3 map3v.sub.4 mapi3v.sub.9 ], respectively. A binary 1 is mapped to the bits map3v.sub.1, map3v.sub.16, and map3v.sub.18. The weight bit w.sub.1 is mapped to bit map3v.sub.5. The result of the operation (w.sub.1 w.sub.2 w.sub.3)w.sub.4 performed by AND gate 1208, AND gate 1212 and OR gate 1214 on weight bits [w.sub.1 w.sub.2 w.sub.3 w.sub.4 ], using conventional combinational logic, is mapped to both bits map3v.sub.7 and map.sub.3 v.sub.8, When the input data b is in set Q.sub.3, then the first controller 920 generates q.sub.3 =1 and q.sub.1 =q.sub.2 =q.sub.4 =q.sub.5 =0. The multiplexer 916 selects map3v to be output to v. The map map3v is generated using b, b, p, and weights bits [w.sub.1 w.sub.2 w.sub.3 w.sub.4 ] according to column 4 in TABLE II, and using the combinational logic as has been described above

Referring now to FIG. 13, a preferred embodiment for the fourth mapping circuit 912 is shown. The fourth mapping circuit 912 generates the mapping from column 5 to column 1 of TABLE II. The fourth mapping circuit 912 preferably comprises a first, second and third OR gates 1300, 1302, 1304 and a plurality of hardwiring of inputs to outputs to generate the map4v bits. The first, second and third OR gates 1300, 1302, 1304 are coupled to produce the result of the operation (w.sub.1 w.sub.2 w.sub.3 w.sub.4) on weight bits [w.sub.1 w.sub.2 w.sub.3 w.sub.4 ], and the output of the third OR Gate 1304 is mapped to bit map4v.sub.2. The input data bits [b.sub.1 . . . b.sub.8 ] are mapped directly to bits [map4v.sub.3 map4v.sub.4 map4v.sub.5 map4v.sub.9 map4v.sub.11 . . . map4v.sub.14 ], respectively, via hard wiring. The variable p, computed according to equation 13, is mapped to bit map4v.sub.6, a binary 0 is mapped to both bits map4v.sub.7 and map4v.sub.10, and a binary 1 is mapped to the remaining bits [map4v.sub.1 map4v.sub.8 map4v.sub.15 . . . map4v.sub.18 ]. When the input data b is in set Q.sub.4, then the first controller 290 generates q.sub.4 =1 and q.sub.1 =q.sub.2 =q.sub.3 =q.sub.5 =0, and in response the multiplexer 916 selects map4v to be output to v. The map map4v is generated using b, p, and weights bits [w.sub.1 w.sub.2 w.sub.3 w.sub.4 ] according to column 5 in TABLE II, using the hardwiring and combinational logic set forth in FIG. 13.

Referring now to FIG. 14 a preferred embodiment for the fifth mapping circuit 914 is shown. The fifth mapping circuit 914 generates the mapping from column 6 to column 1 of TABLE II. The fifth mapping circuit 914 comprises a plurality of OR gates 1400, 1402, 1404, 1406, 1408, 1410, and 1412, a plurality of inverters 1414, 1416 and 1418 and hardwiring of inputs to outputs to generate the map5v word. The variable p computed, according to equation 13, is mapped to bit map5v.sub.6. A a binary 0 is mapped to bits map5v.sub.8, map5v.sub.10, and map5v.sub.17. A binary 1 is mapped to the bits [map5v.sub.1 map5v.sub.7 map5v.sub.16 map5v.sub.18 ]. An intermediate variable l is formed by ORing the data bits (b.sub.1 b.sub.3 b.sub.5 b.sub.7 b.sub.9 b.sub.13) using OR gate 1400. The variable l, provided by the output of OR gate 1400 is then mapped to bit map5v.sub.14 and its complement l provided by inverter 1418 is mapped and output as map5v.sub.15. Input data bits b.sub.1 and b.sub.2 are ORed together by OR gate 1402 and the result is coupled to bit map5v.sub.2. The output of OR gate 1402 is inverted by inverter 1414 and mapped to bit map5v.sub.3. Input data bits b.sub.3 and b.sub.4 are ORed together by OR gate 1404 and the result is mapped to bit map5v.sub.4. Input bits b.sub.5 and b.sub.6 are ORed together by OR gate 1406 and the result is mapped to bit map5v.sub.5. Input data bits b.sub.7 and b.sub.8 are similarly ORed together by OR gate 1408 and the results is mapped to bit map5v.sub.9. Input data bits b.sub.9 and b.sub.11 are ORed together by OR gate 1410 and the result is mapped to bit map5v.sub.11. Finally, the input data bits b.sub.13 and b.sub.15 are ORed together by OR gate 1412 and the results is mapped to bit map5v.sub.12. The output of OR gate 1412 is complemented by inverter 1416 and the output of the inverter 1416 is mapped to bit map5v.sub.13. When the input data b is in set Q.sub.5, then the first controller 902 generates q.sub.5 =1 and q.sub.1 =q.sub.2 =q.sub.3 =q.sub.4 =0, and in response to the q bits, the multiplexers 916 selects map5v to be output to v. The map map5v is generated using b, and p according to column 6 in TABLE II, and using the logic shown in FIG. 14.

Referring now to FIGS. 15A and 15B15, one embodiment for the multiplexer 916 of FIG. 9 FIG. shown. The multiplexer 916 preferably comprises seventeen 5-way multiplexers 1500-1516 each producing a single output bit v.sub.i which collectively form the codeword v. The bit v.sub.6 is formed directly from map1v.sub.6, and is implemented with a hardwiring of input to output on block 1520 that maps map1v.sub.6 to v.sub.6. The remaining 5-way multiplexers 1500-1516 are responsive to the control variables q.sub.1 through q.sub.5. For example, when q.sub.1 =1, then the output of map1 is steered to the output v.sub.1 of the 5-way multiplexers 1500. Each of the other 5-way multiplexers 1501-1516 operate in a similar manner to direct one of the five input signal applied as the output for the corresponding bit of codeword v.

Referring now to FIG. 16, an exemplary embodiment for one of the seventeen 5-way multiplexers 1500-1516 constructed according to the present invention is shown. The output bit v.sub.i of the exemplary 5-way multiplexer 1500-1516 is equal to mapnjv.sub.i for 1.ltoreq.i.ltoreq.18, i.noteq.6, and q.sub.i =1 for 1.gtoreq.j .gtoreq.5. The control bits q.sub.1 through q.sub.5 generated by the first controller 902 are ANDed with the respective inputs mapjv.sub.i, for each map by the AND gates 1602, 1604, 1606, 1608, 1610. The results of the AND operations are then ORed together to produce the output bits v.sub.i. In other words, the outputs of each of the AND gates 1602, 1604, 1606, 1608, 1610 is coupled to an input of the OR gate 1600, and the output of the OR gate 1600 provides the output bit v.sub.i. Specifically, control bit q.sub.1 is ANDed with input map1v.sub.i using an AND gate 1602. The control bit q.sub.2 is ANDed with input map2v.sub.i using an AND gate 1604. The control bit q.sub.3 is ANDed with input map3v.sub.i using an AND gate 1606. The control bit q.sub.4 is ANDed with input map4v.sub.i using an AND gate 1608. The control bit q.sub.5 is ANDed with input map5v.sub.i using an AND gate 1610. Referring now to FIG. 17, the first controller 902 FIG. 9 constructed according to the present invention is shown. The first controller 902 generates five control variables, q.sub.1 through q.sub.5, which are based on input data b and the weight bits [w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ]. If the input data is in the set Q.sub.i, 1.ltoreq.i.ltoreq.5, then q.sub.i =1, and the rest of the variables are zero. An intermediate variable r.sub.1 is computed from the operation of (w.sub.0 w.sub.1 w.sub.2)(w.sub.3 w.sub.4) by OR gate 1700, AND gate 1702 and OR gate 1710 on the weights bits [w.sub.0 w.sub.1 w.sub.2 w.sub.3 w.sub.4 ]. The intermediate variable r.sub.1 is the used to derive the control variables q.sub.1 through q.sub.5 as follows: The input data bits [b.sub.1 b.sub.3 b.sub.5 b.sub.6 b.sub.8 b.sub.9 ] are ORed together by OR gate 1704 and the input data bits [b.sub.9 . . . b.sub.16 ] are ORed together by OR gate 1706. The results of these OR operations are then ANDed by AND gate 1716 with r.sub.1 (the output of OR gate 1710) to form the variable q.sub.1. The result of the OR operation on input data bits [b.sub.1 b.sub.3 b.sub.5 b.sub.6 b.sub.8 b.sub.9 ] is inverted by inverter 1714 and the output of the inverter 1714 is coupled to the input of AND gate 1712 along with the output of OR gate 1710, r.sub.1. The output of the AND gate 1712 forms the output q.sub.3. The result of an OR operation on input data bits [b.sub.9 . . . b.sub.16 ] performed by passing these bits to OR gate 1706 is also inverted by inverter 1718 and the output of the inverter 1718 is ANDed with r.sub.1 (the output of OR gate 1710) at AND gate 1720 to form q.sub.4. The input data bits [b.sub.10 b.sub.12 b.sub.14 b.sub.16 ] are ANDed together by AND gate 1708, and the output of AND gate 1708 is ORed with r.sub.1, by OR gate 1722 then inverted by inverter 1724 to form q.sub.2. Finally, the input data bits [b.sub.10 b.sub.12 b.sub.14 b.sub.16 ] are ANDed together, then the output of AND gate 1708 is ANDed by AND gate 1728 again with inverted r.sub.1 provided by inverter 1726 to form q.sub.5.

Referring now to FIG. 18, the details of modulo adder 31 in FIG. 9B constructed according to the present invention is shown. The modulo adder 31 is implemented as an OR operation, or a single OR gate 1800 on the current state cs and the bits [v.sub.1 v.sub.2 v.sub.5 v.sub.9 v.sub.10 v.sub.13 v.sub.14 v.sub.17 v.sub.18 ] according to equation 13. The result of the OR function, p, is used by map1 through map5 in the code generator 154d to produce the codeword v.

In sum, the code generator 154d, as coupled to the precoder 14 and followed by the PR channel 16, produces the following parameters: N=7, Z=16, Z.sub.i =13, and E=3. Additionally, Code 3 generates a Hamming distance of 2 at the output of the precoder 14. Finally, no codeword v belonging to Code 3 satisfies the following three properties:

1) v.sub.18 =v.sub.16 =v.sub.14 =v.sub.12 =v.sub.10,

2) v.sub.1 =v.sub.3 =v.sub.5 =v.sub.7 =v.sub.9 =v.sub.11, and

3) v.sub.11 =v.sub.12 =v.sub.13 =v.sub.14 =v.sub.15 =v.sub.16 =v.sub.17 =v.sub.18.

Referring now to FIG. 19, a third embodiment of the code de-converter 502c for use in conjunction with the fourth embodiment of the code generator 154d is shown. The third embodiment of the code de-converter 502c decodes code words that have been encoded with "Code 3." The third embodiment of the code de-converter 502c preferably comprises an adder 1900, a second controller 1902, a plurality of inverters 1904, a first mapping circuit 1906, a second mapping circuit 1908, a third mapping circuit 1910, a fourth mapping circuit 1912, a fifth mapping circuit 1914, and a multiplexer 1916. The third embodiment of the code de-converter 502c uses 5 maps. MAP1 through MAP5, which operate on distinct sets of received vectors, C.sub.1 through C.sub.5, respectively. The coded word u is input to the adder 1900 to produce weight bits which are in turn provided to the second controller 1902 along with the coded word u. The second controller 1902 uses these inputs to determine which of the five maps to use to generate the decoded word b'.

The code de-converter 502c can be characterized using the following notation: Let u=[u.sub.1 . . . u.sub.18 ] denote a received vector by the decoder 20 taken form the detector sequence {u.sub.1 u.sub.2 u.sub.3 . . . }; let W=weight of u=number of ones in u, and let sets B.sub.1 through B.sub.6, and B be defined a follows:

The above sets are not all pairwise disjoint, nonetheless, the set B is the important set and sets B.sub.1 through B.sub.6 are utilized to characterize B.

Now sets C.sub.1 through C.sub.5 are given below using sets B and B.sup.c. (Set X.sup.c is the complement of set X.)

Maps MAP1 through MAP5 are defined in TABLE III below.

As shown in FIG. 19, the adder 1900 computes the weight W of u, and it generates the weight bits [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ]. The weight bits [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ] are input to the second controller 1902. The second controller 1902 generates five control variables, c.sub.1 through c.sub.5, which are based on the received vector u and the weight bits [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ]. Only one of the five control variables is a logical one at a time, and the rest are logical zeros. In other words, if the received vector u is in set C.sub.i 1.ltoreq.i.ltoreq.5, then c.sub.i =1, and the rest of the variables are zero. The output of the second controller 1902, providing the signals c.sub.1 through c.sub.5, is coupled to the control inputs of the multiplexer 1916. The multiplexer 1916 selects one of its inputs Map1b through Map5b to produces b. The selection is based on the control variables c.sub.1 through c.sub.5. If c.sub.i =1, 1.ltoreq.i.ltoreq.5, then the multiplexer 1916 generates b=Mapib.

The first mapping circuit 1906, the second mapping circuit 1908, the third mapping circuit 1910, the fourth mapping circuit 1912, and the fifth mapping circuit 1914, respectively implement the functions described in maps Map1 through Map5 based on the received vector u and its complement u. Each of the mapping circuits 1906, 1908, 1910, 1912, 1914 has an input coupled to receive coded word u, and the inverse of coded word u from the inverter 1904. Each of the mapping circuits 1906, 1908, 1910, 1912, 1914 is described below with reference to FIGS. 20-24.

Referring now to FIG. 20, a preferred embodiment for the first mapping circuit 1906 is shown. The first mapping circuit 1906 maps column 2 of TABLE III to column 1 of TABLE III. The received vector u is mapped directly to Map1b, except for bits u.sub.6 and u.sub.10 which are discarded as shown in FIG. 20. Accordingly, MAP1 (i.e., column 2 in TABLE III) maps the eighteen bit received vector u into the sixteen bit vector Map1b. More specifically bits u.sub.1, u.sub.2, u.sub.3, u.sub.4, u.sub.5, u.sub.7, u.sub.8, u.sub.10, u.sub.11, u.sub.12, u.sub.13, u.sub.14, u.sub.15, u.sub.16, u.sub.17, and u.sub.18, are mapped to bits map1b.sub.1, map1b.sub.2, map1b.sub.3, map1b.sub.4, map1b.sub.5, map1b.sub.6, map1b.sub.7, map1b.sub.8, map1b.sub.9, map1b.sub.10, map1b.sub.11, map1b.sub.12, map1b.sub.13, map1b.sub.14, map1b.sub.15, and map1b.sub.16, respectively. This can be done through simple hard wiring of the inputs to the outputs as shown in FIG. 20.

Referring now to FIG. 21, a preferred embodiment for the second mapping circuit 1908 is shown. The second mapping circuit 1908 maps column 3 of TABLE III to column 1 of TABLE III. The selected bits of the complement of the received vector u are mapped directly to Map2b, except for bits u.sub.6 and u.sub.10 which are discarded as shown in FIG. 21. More specifically bits u.sub.1 , u.sub.2 , u.sub.3 , u.sub.4 , u.sub.5 , u.sub.7 , u.sub.8 , u.sub.9 , u.sub.11 , u.sub.12 , u.sub.13 , u.sub.14 , u.sub.15 , u.sub.16 , u.sub.17 , u.sub.18 , are mapped to bits map1b.sub.1, map1b.sub.2, map1b.sub.3, map1b.sub.4, map1b.sub.5, map1b.sub.6, map1b.sub.7, map1b.sub.8, map1b.sub.9, map1b.sub.10, map1b.sub.11, map1b.sub.12, map1b.sub.13, map1b.sub.14, map1b.sub.15, map1b.sub.16, respectively. Accordingly, MAP2 (column 3 in TABLE III) maps the eighteen bit complement of the received vector u into the sixteen bit output Map2b. The second mapping circuit 1908 can also be implemented through simple hard wiring of the inputs to the outputs as shown in FIG. 21.

Referring now to FIG. 22, a preferred embodiment for the third mapping circuit 1910 is shown. The third mapping circuit 1910 maps 4 of TABLE III to column 1 of TABLE III. The third mapping circuit 1910 preferably comprises an OR gate 2200, and a plurality of Exclusive-OR gates 2202, 2204, 2206 and 2208. The OR gate 2200 has three inputs coupled to receive bits [u.sub.5 u.sub.7 u.sub.8 ] to produce an intermediate variable s. The intermediate variable s from the output of the OR gate 2200 is input to one input of each Exclusive-OR gate 2202, 2204, 2206 and 2208. The other of each Exclusive-OR gate 2202, 2204, 2206 and 2208 is respectively coupled to receive bits [u.sub.2 u.sub.3 u.sub.4 u.sub.9 ]. The outputs of the Exclusive-OR gates 2202, 2204, 2206 and 2208 are then mapped to bits [map3b.sub.2 map3b.sub.4 map3b.sub.7 map3b.sub.10 ], respectively. A binary 0 is mapped to bits [map3b.sub.1 map3b.sub.3 map3b.sub.5 map3b.sub.6 map3b.sub.8 map3b.sub.9 ], and is implemented through hard wiring. The bits [u.sub.11 u.sub.12 u.sub.13 u.sub.14 u.sub.15 u.sub.17 ] are mapped to the bits [map3b.sub.11 . . . map3b.sub.16 ], respectively, similarly by hardwiring.

Referring now to FIG. 23, a preferred embodiment for the fourth mapping circuit 1912 is shown. The fourth mapping circuit 1912 maps column 5 of TABLE III to column 1 of TABLE III. A binary 0 is mapped to bits [map4b.sub.9 . . . map4b.sub.16 ]. The bits [u.sub.3 u.sub.4 u.sub.5 u.sub.9 u.sub.11 u.sub.12 u.sub.13 u.sub.14 ] are mapped to bits [map4b.sub.1 . . . map4b.sub.8 ], respectively. The bits [u.sub.1 u.sub.2 u.sub.6 u.sub.7 u.sub.8 u.sub.10 ] are discarded as shown in FIG. 23.

Referring now to FIG. 24, a preferred embodiment for the fifth mapping circuit 1912 is shown. The fifth mapping circuit 1912 maps 6 of TABLE III to column 1 of TABLE III. The fifth mapping circuit 1912 preferably comprises a plurality of two input AND gates 2400, 2402, 2404, 2406, 2408, 2410, 2412, 2414, 2416, 2418, 2420 and 2422. A binary 1 is mapped to the bits [map5b.sub.10 map5b.sub.12 map5b.sub.14 map5b.sub.16 ]. The bit u.sub.2 is ANDed with u.sub.14 by AND gate 2400 and the output of the AND gate 2400 is coupled to output map5b.sub.1 for the desired mapping. Similarly, the bit u.sub.2 is ANDed with u.sub.15 by the AND gate 2402 and the output of the AND gate 2402 is coupled to output map5b.sub.2. The bits [u.sub.4 u.sub.5 u.sub.9 u.sub.11 u.sub.12 ] are likewise ANDed individually by AND gates 2404, 2406, 2408, 2410, 2412, 2414, 2416, 2418, 2420 and 2422 with both u.sub.14 and u.sub.15, then mapped to the bits [map5b.sub.3 . . . map5b.sub.9 map5b.sub.11 map5b.sub.13 map5b.sub.18 ] as shown in FIG. 24.

Referring now to FIGS. 25A and 25B, the multiplexer 1916 of FIG. 19 constructed according to the present invention is shown. The multiplexer 1916 preferably comprises sixteen 5-way multiplexers 2501-2516 each producing a single output bit b.sub.j, which collectively form the reconstructed input data b. Each of the 5-way multiplexers 2501-2516 has five data inputs, and each input is coupled to a respective bit from each of the five mapping circuits 1906, 1908, 1910, 1912 and 1914. Each of the 5-way multiplexers 2501-2516 are responsive to the control variables, c.sub.1 through c.sub.5, generated by the second controller 1902. For example, when c.sub.1 =1, then the output of MAP1 is steered to the output b.sub.1 of the 5-way multiplexers 2501-2516. Thus, when the c.sub.n control variable is asserted, the nth map is output by the multiplexer 1916.

Referring now to FIG. 26, the details of an exemplary one of the sixteen 5-way multiplexers 2501-2516 in FIGS. 25A and 25B are shown. The output b.sub.i of the 5-way multiplexer 2501-2516 is MAPjb.sub.i for 1.ltoreq.i.ltoreq.16, and c.sub.j =1 for 1.ltoreq.j.ltoreq.5. The exemplary 5-way multiplexer 2501-2516 comprises and OR gate 2600 and an plurality of AND gates 2602, 2604, 2606, 2608 and 2610. The AND gates 2602, 2604, 2606, 2608 and 2610 have one input coupled to control variables c.sub.1 through c.sub.5, respectively. The other input of the AND gates 2602, 2604, 2606, 2608 and 2610 is coupled to receive the output bit of maps 1 through 5, respectively. The outputs of each AND gate 2602, 2604, 2606, 2608 and 2610 are coupled to an input of the OR gate 2600 and the output of the OR gate 2600 provide the output of the multiplexer 2501-2516. Thus, the control variables c.sub.1 through c.sub.5 are ANDed with the inputs MAPjb.sub.i, and the results of the AND operations are then ORed together to produce the output b.sub.i.

Referring now to FIG. 27, the second controller 1902 of FIG. 19 is shown. The second controller 1902 preferably comprises a plurality of OR gates 2704, 2712, 2732, 2734, 2744 and 2752. AND gates 2702, 2706, 2708, 2710, 2714, 2716, 2718, 2720, 2722, 2724, 2726, 2728, 2730, 2736, 2738, 2740, 2742, 2746, 2748, 2750, 2754, 2756, 2758 and 2760, and an inverter 2762 for generating nine intermediate variables and five control variables or signals (c.sub.1 through c.sub.5). The intermediate variables x,y,z,t,s,s.sub.1, s.sub.2,s.sub.3,s.sub.4, and the control variables are c.sub.1 through c.sub.5.

As shown in FIG. 27, the intermediate variables x,y,z,t,s,s.sub.1,s.sub.2,s.sub.3,s.sub.4 are formed using combinational logic devices. The intermediate variable y is formed by performing the logical operation (u.sub.18 u.sub.10 u.sub.16)((u.sub.1 u.sub.2 )v u.sub.1 )) using AND gates 2700, 2702, 2706 and OR gate 2704. The variable Z is formed by performing the Boolean operation (u.sub.1 u.sub.10 u.sub.16)((u.sub.17 u.sub.18 )u.sub.18)) using AND gates 2708, 2710, 2714 and OR gate 2712. The variable x is formed by performing the logical operation u.sub.17 u.sub.18 u.sub.1 u.sub.10 u.sub.16 using AND gates 2716 and 2718. The variable t is formed by performing the logical operation u.sub.2 u.sub.18 u.sub.1 u.sub.10 u.sub.16 using AND gates 27120 and 2718.

The intermediate variable s through s.sub.4 are formed from the weight bits [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ] and their complement [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ]. The variable s.sub.1 is formed by ANDing the weight bits W.sub.0 and W.sub.1 using AND gate 2722. The variable S.sub.2 is formed by ANDing the weights bits [W.sub.0 W.sub..sub.1 W.sub.2 W.sub.3 W.sub.4 ] using AND gate 2724. The variable s.sub.3 is formed by ANDing the weight bits [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ] using AND gate 2726, and finally, The variable s.sub.4 is formed by ANDing [W.sub.0 W.sub.1 W.sub.2 W.sub.3 W.sub.4 ] using AND gate 2728. Finally, the variable s is formed using the variables x, y, z, t, s.sub.1, s.sub.2, s.sub.3, and s.sub.4. The OR gates 2730, 2732, 2744 and AND gates 2732, 2734, 2736, 2738, 2740 and 2742 perform the logical operation (([t]Z)S.sub.3)(tS.sub.4)((([t]Z)y)s.sub.2)(((([t]Z)Y)X)s.sub.1) using the applied variables x,y,z,t,s.sub.1,s.sub.2, s.sub.3, and s.sub.4. The output of OR gate 2744 provides the s signal, it is complemented by inverter 2762. Both these signals are used to generate the control signals c.sub.1 through c.sub.5 output by the second controller 1902.

Furthermore, as shown in FIG. 27, the control variables c.sub.1 through c.sub.5 are also formed using combination logic devices. The control variable c.sub.1 is formed by ANDing s and u.sub.10 using AND gate 2746. Control variable c.sub.2 is similarly formed by ANDing s and u.sub.10 using AND gate 2748. Control variable c.sub.3 is formed by ANDing u.sub.7 and u.sub.8 and ANDing u.sub.7 and u.sub.8 using AND gate 2750 and 2756, respectively. The results of these AND operations are then ORed by OR gate 2752, and the output of OR gate 2752 is ANDed with s by AND gate 2754 to produce c.sub.3. Control variable c.sub.4 is formed by ANDing s, u.sub.7 , and u.sub.8 using AND gate 2758. Finally, control variable c.sub.5 is formed by ANDing s.sub.0, u.sub.7, and u.sub.8 AND gate 2760. All of the operations defined above are implemented using combinational logic techinques well-known in the art.

The sets C.sub.1 through C.sub.5 form a partition of {0,1}.sup.18 and the third embodiment of the code de-converter 502c uses a distinct MAP1 through MAP5 to decode the received vectors u of each of the sets C.sub.1 through C.sub.5. The bits [u.sub.7 u.sub.8 u.sub.10 ] are employed to characterize C.sub.1 through C.sub.5. Therefore, if errors occur in the bits [u.sub.7 u.sub.8 u.sub.10 ], it is possible that the code de-converter 502c could select the incorrect map to decode the received vector u. In fact, usually more data bits are corrupted this way than due to errors occurring elsewhere. Accordingly, the bits [u.sub.7 u.sub.8 u.sub.10 ] are situated by design to locations inside the received vector u where they would be less susceptible to typical noise (e.g., the 8th and 10th bit positions of each received vector u)

Referring now to FIG. 28, a fifth embodiment of the code generator 154e constructed according to the present invention for encoding signals with a fourth code, "Code 4," is shown. The fifth embodiment of a code generator 154e provides a fourth code, "Code 4," that is a rate 16/18 run length limited code with the additional property that after precoding for the (1-D.sup.2) channel the code words have 0 mod 2 number of ones. As best illustrated by FIG. 28, the fifth embodiment of the code generator 154e receives a 16-bit word, b.sub.1 (k) . . . b.sub.16 (k) which is defined to be variable B=(b.sub.1, y, b.sub.2) where b.sub.1 =b.sub.11, . . . b.sub.17 ; b.sub.2 =b.sub.21, . . . , b.sub.27 and y=y.sub.1, y.sub.2 ; and outputs a 18-bit word, v.sub.1 (k) . . . v.sub.18 (k), defined to be variable U=(u.sub.1, v, u.sub.2) where u.sub.1 =u.sub.11, . . . , u.sub.17 ; u.sub.2 =u.sub.21, . . . , u.sub.27 and v=v.sub.1, v.sub.2, v.sub.3, v.sub.4. Referring now to FIG. 29, the fifth embodiment of the code generator 154e is shown in more detail. The fifth embodiment of the code generator 154e preferably comprises a partitioning unit 2900 and a mapping unit 2902. The partitioning unit 2900 is preferably coupled to receive the 16 bits of the input word, (b.sub.1, y, b.sub.2), and generate a signal, preferably a four bit signal, that indicates which map the mapping unit 2902 is to use in generating the output word. The partitioning unit 2900 receives the input data bits, (b.sub.1, y, b.sub.2) of the encoder 12. The number of ones in the input data bits are used to partition the data word and select a encoding map using the following equations:

Auxiliary Sets: partitioning (b.sub.1, b.sub.2)

Partition of data words: (b.sub.1, y, b.sub.2)

where n.sub.1 is defined to be the number of ones in b.sub.1 ; n.sub.2 is defined to be the number of ones in b.sub.2 ; and G1 through G12 correspond to a row of the encoding map for Code 4, as will be described below with reference to TABLE IV. Since exemplary partitioning units have been described above for Codes 1-3, the specific implementation in combinational logic, registers and multiplexers will not be described here. However, those skilled in the art would be able to construct the pertaining unit 2900 from the above equations and the above disclosure for Codes 1-3.

As shown in FIG. 29, the mapping unit 2902 receives the inputs bits (b.sub.1, y, b.sub.2), and the output of the partitioning unit 2900, variable G. The mapping unit 2902 uses the map shown in TABLE IV to determine its output. The mapping unit 2902 generates eighteen output bits, (u.sub.1, v, u.sub.2). The value of the variable G from the partitioning unit 2900 identifies which row of TABLE IV that will be used to generate the output bits (u.sub.1, v, u.sub.2). For example, if the input word B is in the set G1, then the first row of TABLE IV will be used to generate the output word U.

The values in TABLE IV are generated from the input word B, and the following equations:

P is chosen such that the following equation is satisfied:

Those skilled in the art will recognize that the mapping unit 2902 may be constructed using combinational logic in conjunction with the following maps that are used to generate certain values of TABLE IV as specified in the above equations. The preferred embodiment of the mapping unit 2902 includes: f maps (TABLE V); g(D) map, a 1-to-1 map from D to non-zero 5-bit binary words (TABLE VI); map h(D3)=(h1,h2), a 1-to-1 map from D3 to Z75 (TABLE VII); map h'(D2)=(h.sub.1 ',h.sub.2 '), a 1-to-1 map from D2 to Z37 (TABLE VIII); and map j(h.sub.2, h.sub.1 '), a 1-to-1 map from Z53 to I (TABLE IX), as shown below.

Those skilled in the art will further recognize that the mapping unit 2902 need only provide mapping for values G1 through G8 if the maximum number of run length zeros on the odd and even subsequences can be infinite. However, the encoding provided by TABLE IV limits the maximum number of run length zeros on the odd and even subsequences to ten.

Referring now to FIGS. 30 and 31, a fourth embodiment of the code de-converter 502e constructed according to the present invention to decode words encoded using Code 4, and for use with the code generator 154e of FIGS. 28 and 29, is shown. The Code 4 de-converter 502e is defined here in terms of the same variables used for encoding namely that an encoded 18-bit word, u.sub.1 (k) . . . u.sub.18 (k), defined to be variable U=(u.sub.1,v,u.sub.2) where u.sub.1 =u.sub.11, . . . u.sub.17 ; u.sub.2 =u.sub.21, . . . u.sub.27 and v=v.sub.1,v.sub.2,v.sub.3,v.sub.4 is received by the Code 4 de-converter 502e, and in response the Code 4 de-converter 502e generates a 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k) which is defined to ve variable B=(b.sub.1,y,b.sub.2) where b.sub.1 =b.sub.11, . . . b.sub.17 ; b.sub.2 =b.sub.21, . . . b.sub.27 and y=y.sub.1,y.sub.2. This is best illustrated in FIG. 30, where the Code 4 de-converter 502e is shown as receiving the encoded 18-bit word, u.sub.1 (k) . . . u.sub.18 (k), and as outputting the 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k). The Code 4 de-converter 502e preferably is constructed similar the code generator 154e in that the Code 4 de-converter 502e comprises a partitioning unit 3100 and a mapping unit 3102. The partitioning unit 3100 has inputs coupled to receive input bits U=(u.sub.1,v,u.sub.2), and an output coupled to the mapping unit 3102 to provide the select signal. The partitioning unit 3100 is preferably combinational logic as defined by the first column of TABLE X to generate a select signal that identifies which of eight (or twelve) maps is to be used to generate the 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k). The mapping unit 3102 is circuitry defined according to TABLE X to map the input bits to the output bits using a row of TABLE X according to the value of the select signal. The mapping unit 3102 is coupled to receive the input bits U=(u.sub.1,v,u.sub.2), and the select signal from the partitioning unit 3100. The mapping unit 3102 preferably implements eight maps (the first eight rows) for mapping U to B. If the eight maps are used then the maximum number of run length zeros on the odd and even subsequences can be infinite. However, if the mapping circuit 3102 uses all twelve rows of TABLE X for the mapping function, then the maximum number of run length zeros on the odd and even subsequences will be equal to ten. The mapping unit 3102 preferably uses the following equations to decode the input signal and re-produce the original signal.

where

Referring again to FIGS. 28-31, a modified embodiment of the code generator 154f is shown for encoding according to Code 4'. The modified version encodes using Code 4', and has the same general structure as the code generator 154e for Code 4. The Code 4' code generator 154f differs in that it uses a different partition and a different encoder mapping. The variable definitions for the input bits and output bits are the same as defined above for Code 4. The Code 4' also uses the same f.sub.1 (b) and f.sub.2 (b) maps as defined above in TABLE V, and the same g(D) map defined above in TABLE VI. The partitioning unit 2900 for the Code 4' preferably generates the partition using the same auxiliary partitioning sets as Code 4, but selects a partition using the following equations:

Partition of data words: (b.sub.1, y, b.sub.2)

It should be noted that the Code 4' is generally easier to implement because it has fewer maps than Code 4.

The mapping unit 2902 for the Code 4' code generator 154f also receives the input bits and the output of the partitioning unit 2900, variable G1-G7. The Code 4' code generator 154f uses the map shown in TABLE XI to generate the output bits. Again, the value of the G variable determines which row of TABLE XI will be used to map the input bits to the output bits.

where,

The Code 4' described by TABLE XI has N=7, Z=10 and Z.sub.i =11. The Code 4' is particularly advantageous because it has the property that minimum distance error events corrupt at most 3 user bytes, since minimum distance error events occurring across coeword boundaries are prevented from corrupting the first 8 bits of the first codeword, by ensuring there is at least one 1 on both the odd and even subsequences in bits u.sub.21, . . . , u.sub.27 which will protect u.sub.11, . . . , u.sub.17 and v.sub.1, v.sub.2, v.sub.3, v.sub.4 and thus enable data bits b.sub.11, . . . , b.sub.17, y.sub.1 to be correctly decoded.

The mapping used for encoding in Code 4' is derived using the maps as defined above for code 4 and a h (D3) map, which is 1-to-1 map from D3 to 4-bit non-zero words, shown in TABLE XII below.

Referring again to FIGS. 30 and 31, a code de-converter 502f for Code 4' is shown. The Code 4' de-converter 502f receives an encoded 18-bit word, u.sub.1 (k) . . .u.sub.18 (k), defined to be variable U=(u.sub.1, v, u.sub.2) where u.sub.1 =u.sub.11, . . . , u.sub.17 ; u.sub.2 =u.sub.21, . . . , u.sub.27 and v=v.sub.1, v.sub.2, v.sub.3, v.sub.4, and in response the Code 4' de-converter 502f generates a 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k) which is defined to be variable B=(b.sub.1, y, b.sub.2) where b.sub.1 =b.sub.11, . . . , b.sub.17 ; b.sub.2 =b.sub.21, . . . , b.sub.27 and y=y.sub.1, y.sub.2. The Code 4' de-converter 502f preferably comprises a partitioning unit 3100 and a mapping unit 3102. The partitioning unit 3100 has inputs coupled to receive input bits U=(u.sub.1, v, u.sub.2), and an output coupled to the maping unit 3102 to provide the select signal. The partitioning unit 3100 is preferably combinational logic as defined by the first column of TABLE XIII to generate a select signal that identifies which row of the map is to be used to generate the 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k). The mapping unit 3102 is circuitry defined according to TABLE XIII to map the input bits to the output bits using a row of TABLE XIII according to the value of the select signal. The mapping unit 3102 is coupled to receive the input bits U=(u.sub.1, v, u.sub.2), and the select signal from the partitioning unit 3100. The mapping unit 3102 preferably uses the following equations to decode the input signal and re-produce the original signal.

where

Referring now to FIGS. 32 and 33, a seventh embodiment of the code generator 154g constructed according to the present invention for encoding signals with a fifth code. "Code 5," is shown. The seventh embodiment of the code generator 154g provides a fifth code, "Code5," that is a rate 16/18 run length limited code with the additional property that after precoding for the 1-D channel the code words have 0 mod 3 number of ones. As best illustrated by FIG. 32, the seventh embodiment of the code generator 154g receives a 16-bit word b.sub.1 (k) . . . b.sub.16 (k) which is defined to be variable B=(b.sub.1,b',b.sub.2) where b.sub.1 =b.sub.11, . . . , b.sub.17 ; b.sub.2 =b.sub.21, . . . ,b.sub.27 and b'=b'.sub.1, b'.sub.2 ; and outputs a 18-bit word, v.sub.1 (k) . . . v.sub.18 (k), defined to be variable U=(u.sub.1,u',u.sub.2) where u.sub.1 =u.sub.11, . . . ,u.sub.17 ; u.sub.2 =u.sub.21, . . . ,u.sub.27 and u'=u'.sub.1, u'.sub.2, u'.sub.3, u'.sub.4. For convenience and ease of notation and understanding the variable U will also be referred to as variable a where (u.sub.11, . . . ,u.sub.17,u'.sub.1,u'.sub.2,u'.sub.3,u'.sub.4,u.sub.21, . . . ,u.sub.27)=(a.sub.1, . . . ,a.sub.18).

Referring now to FIG. 33, the seventh embodiment of the code generator 154g is shown in more detail. The seventh embodiment of the code generator 154g preferably comprises a partitioning unit 3300, a mapping unit 3302, and a modification unit 3306. The partitioning unit 3300 is preferably coupled to receive the 16 bits of the input word, (b.sub.1,b',b.sub.2), and generate a signal, preferably a four bit signal, that indicates which map the mapping unit 3302 is to use in generating the output word. The partitioning unit 3300 receives the input data bits, (b.sub.1,b',b.sub.2) of the encoder 12. The number of ones in the input data bits are used to partition the data word and select a encoding map using the following equations:

Auxiliary Sets: partitioning (b.sub.1,b.sub.2)

Partition of data words: (b.sub.1,b',b.sub.2)

where G1 through G8 correspond to a row of the encoding map for Code 5, as will be described below with reference to TABLE XIV. Since exemplary partitioning units 2900,3100 have been described above for Codes 1-4', the specific implementation in combinational logic, registers and multiplexers will not be described here. However, a more detailed description that is also applicable to this Code 5 implementation is described in detail below with reference to Code 6 and FIGS. 34 and 35. Those skilled in the art will be able to construct the Code 5 code generator 154g from the equations and the disclosure below.

As shown in FIG. 33, the mapping unit 3302 receives the input bits (b.sub.1,b',b.sub.2), and the output of the partitioning unit 3300, variable G. The mapping unit 3302 uses the map shown in TABLE XIV to determine its output. The mapping unit 3302 generates eighteen output bits, (u.sub.1,u',u.sub.2). The value of the variable G from the partitioning unit 3300 identifies which row of TABLE XIV that will be used to generate the output bits (u.sub.1,u',u.sub.2). For example, if the input word B is in the set G3, then the third row of TABLE XIV will be used to generate the output word U.

The values in TABLE XIV are generated from the input word B, and the following equations:

where:

d.sub.1 d.sub.2 d.sub.3 is in {000,011,101} if b.sub.2 '=0, and it is in {001,010,100} if b.sub.2 '=1, and is chosen such that

z.sub.1 z.sub.2 z.sub.3 is in {011,101,110} and it is chosen such that

k.sub.1 k.sub.2 k.sub.3 is in {000,011,101} if b.sub.1 '=0, and it is in {001,010,100} if b.sub.1 '=1, and is chosen such that

Those skilled in the art will recognize that the mapping unit 3302 may be constructed using combinational logic in conjunction with the following maps that are used to generate certain values of TABLE XIV as specified in the above equations. The preferred embodiment of the mapping unit 3302 includes: a f map; a f.sup.-1 map; a h map, a h.sup.-1 map, a h' map, a h'.sup.-1 map, a j map, a j.sup.-1 map, a g map, and a g.sup.-1 map as characterized by the equations shown below.

Map f:

Let x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7) be in {(0000000),(0000001),(0000010),(0000100),(0001000),(0010000),(0100000),(10 00000)} then

where

In words, f points (in base 2) to the location of the one in x. In terms of logic, the map f can be characterized as:

and f.sup.-1 can be characterized as

Map h:

h maps

B.sub.3 to {(y.sub.1,y.sub.2,y.sub.3):(y.sub.1,y.sub.2,y.sub.3).noteq.(0,0,0)}.times. {(z.sub.1,z.sub.2,z.sub.3):(z.sub.1,z.sub.2,z.sub.3).noteq.(1,0,1),(1,1,0) and (1,1,1)}, where B.sub.3 ={x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7):x has weight 3}, (note .vertline.B.sub.3 .vertline.=35). In terms of logic, the map h can be characterized as:

where

where

Map h.sup.-1

h.sup.-1 maps {(y.sub.1,y.sub.2,y.sub.3):(y.sub.1,y.sub.2,y.sub.3).noteq.(0,0,0)}.times. {(z.sub.1,z.sub.2,z.sub.3):(z.sub.1,z.sub.2,z.sub.3).noteq.(1,0,1),(1,1,0) and (1,1,1)} to B.sub.3, where B.sub.3 ={x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7):x has weight 3}, (note .vertline.B.sub.3 .vertline.=35). In terms of logic, the map h.sup.-1 can be characterized as:

where

Map h'

h' maps B.sub.2 to {(y.sub.1,y.sub.2):(y.sub.1,y.sub.2)=(0,0),(0,1),(1,0)}.times.{(z.sub.1,z. sub.2,z.sub.3):(z.sub.1,z.sub.2,z.sub.3).noteq.(0,0,0)}, where B.sub.2 ={x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7):x has weight 2}, (note .vertline.B.sub.2 .vertline.=21). In terms of logic, the map h' can be characterized as:

where

Map h'.sup.-1

h'.sup.-1 maps {(y.sub.1,y.sub.2):(y.sub.1,y.sub.2)=(0,0),(0,1),(1,0)}.times.{(z.sub.1,z. sub.2,z.sub.3):(z.sub.1,z.sub.2,z.sub.3).noteq.(0,0,0)} to B.sub.2, where B.sub.2 ={x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7):x has weight 2}, (note .vertline.B.sub.2 .vertline.=21). In terms of logic, the map h'.sup.-1 can be characterized as:

where

Map j:

j maps {(y.sub.1,y.sub.2,y.sub.3):(y.sub.1,y.sub.2,y.sub.3).noteq.(1,0,1),(1,1,0) ,(1,1,1)}.times.{(x.sub.1,x.sub.2):(x.sub.1,x.sub.2)=(0,0),(0,1),(1,0)} to {(z.sub.1,z.sub.2,z.sub.3,z.sub.4):(z.sub.1,z.sub.2,z.sub.3,z.sub.4).noteq .(0,0,0,0)}. In terms of logic, the map j can be characterized as:

where

Map j.sup.-1 :

j.sup.-1 maps {(z.sub.1,z.sub.2,y.sub.3,z.sub.4):(z.sub.1,z.sub.2,y.sub.3,z.sub.4).noteq .(0,0,0,0)} to {(y.sub.1,y.sub.2,y.sub.3):(y.sub.1,y.sub.2,y.sub.3).noteq.(1,0,1),(1,1,0) ,(1,1,1)}.times.{(x.sub.1,x.sub.2):(x.sub.1,x.sub.2)=(0,0),(0,1),(1,0)}. In terms of logic, the map j.sup.-1 can be characterized as:

where

Map g:

g maps B.sub.2 ' to {(y.sub.1,y.sub.2,y.sub.3,y.sub.4,y.sub.5):(y.sub.1,y.sub.2,y.sub.3,y.sub. 4,y.sub.5).noteq.(0,0,0,0,0)}, where B.sub.2 '={x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7):x has weight 0, 1, and 2}, (note .vertline.B.sub.2 '.vertline.=29). In terms of logic, the map g can be characterized as:

where

Map g.sup.-1 :

g.sup.-1 maps {(y.sub.1,y.sub.2,y.sub.3,y.sub.4,y.sub.5):(y.sub.1,y.sub.2,y.sub.3,y.sub. 4,y.sub.5).noteq.(0,0,0,0,0)} to B.sub.2 ', where B.sub.2 '={x=(x.sub.1,x.sub.2,x.sub.3,x.sub.4,x.sub.5,x.sub.6,x.sub.7):x has weight 0, 1, and 2}, (note .vertline.B.sub.2 '.vertline.=29). In terms of logic, the map g.sup.-1 can be characterized as:

where

Referring now to FIG. 36, a fourth embodiment of the code de-converter 502g constructed according to the present invention to decode words encoded using Code 5, and for use with the code generator 154g of FIGS. 32-35, is shown. The Code 5 de-converter 502g is defined here in terms of the same variables used for encoding namely that an encoded 18-bit word, u.sub.1 (k) . . . u.sub.18 (k), defined to be variable U=(u.sub.1,u',u.sub.2) where u.sub.1 =u.sub.11, . . . ,u.sub.17 ; u.sub.2 =u.sub.21, . . . , u.sub.27 and u'=u'.sub.1,u'.sub.2,u'.sub.3,u'.sub.4 is received by the Code 5 de-converter 502g, and in response the Code 5 de-converter 502g generates a 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k) which is defined to be variable B=(b.sub.1,b',b.sub.2) where b.sub.1 =b.sub.11, . . . ,b.sub.17 ; b.sub.2 =b.sub.21, . . . ,b.sub.27 and b'=b'.sub.1,b'.sub.2, as best illustrated in FIG. 36. The Code 5 de-converter 502g preferably is constructed similar the Code 4 de-converter 502e shown in FIG. 31 in that the Code 5 de-converter 502g comprises a partitioning unit and a mapping unit. The partitioning unit 3100 has inputs coupled to receive input bits U=(u.sub.1,v,u.sub.2), and an output coupled to the mapping unit 3102 to provide the select signal. The partitioning unit is preferably combinational logic as defined by the first column of TABLE XV to generate a select signal that identifies which of eight maps is to be used to generate the 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k). The mapping unit is circuitry defined according to TABLE XV to map the input bits to the output bits using a row of TABLE XV according to the value of the select signal. The mapping unit preferably uses the following equations to decode the input signal and re-produce the original signal.

Where:

Referring again to FIGS. 32-35, an eighth embodiment of the code generator 154h is shown for encoding according to Code 6. Here, for describing the eighth embodiment of the code generator 154h, the same variables used above for Code 5. As best illustrated by FIG. 32, the eighth embodiment of the code generator 154h also receives a 16-bit word, b.sub.1 (k) . . . b.sub.16 (k) which is defined to be variable B=(b.sub.1,b',b.sub.2) where b.sub.1 =b.sub.11, . . . ,b.sub.17 ; b.sub.2 =b.sub.21, . . . ,b.sub.27 and b'=b'.sub.1,b'.sub.2 ; and outputs a 18-bit word, v.sub.1 (k) . . . v.sub.18 (k), defined to be variable U=(u.sub.1,u',u.sub.2) where u.sub.1 =u.sub.11, . . . ,u.sub.17 ; u.sub.2 =u.sub.21, . . . ,u.sub.27 and u'=u'.sub.1,u'.sub.2,u'.sub.3,u'.sub.4. Again, for convenience and ease of notation and understanding the variable U will also be referred to as variable a where (u.sub.11, . . . ,u.sub.17,u'.sub.1,u'.sub.2,u'.sub.3,u'.sub.4,u.sub.21, . . . ,u.sub.27)=(a.sub.1, . . . ,a.sub.18).

Referring now to FIG. 33, the eighth embodiment of the code generator 154h is shown in more detail. The eighth embodiment of the code generator 154h preferably comprises a partition unit 3300, a mapping unit 3302, and a modification unit 3306. As shown in FIG. 33, the partition unit 3300, the mapping unit 3302 and the modification unit 3306 are coupled to receive the input bits (b.sub.1,b',b.sub.2). The partition unit 3300 determines which row of the encoder map to use for encoding and outputs G, a signal indicating the row of the encoder map to be used for encoding, to the mapping unit 3302 and the modification unit 3306. The mapping unit 3302 generates an output, D[1-18], from the encoder map using the G signal from the partitioning unit 3300 and the input bits (b.sub.1,b',b.sub.2). The modification unit 3306 receives the input bits (b.sub.1,b',b.sub.2), the G signal, and mapping unit 3302 output, D[1-18], and alters the bits from the mapping unit 3302, D[1-18], such that they will contain 0 mod 3 ones after precoding, thereby producing the encoded output word, (u.sub.1,u',u.sub.2).

The partitioning unit 3300 takes as input the encoder input data bits (b.sub.1,b',b.sub.2) of the encoder 12. The number of ones (the weight) in the input is summed and used in the equations shown below. The weight of the encoder input data (b.sub.1,b',b.sub.2) is mapped, using the following equations, to values for G1-G11. G1-G11 are used to determine which row of the encoder map, shown in TABLE XVI, will be used in the mapping unit 3302. The eleven possible G values are mapped into four bits G'[1-4] and are the output of the partitioning unit 3300 in the variable G'. The equations used to generate the G'[1-4] are:

The mapping unit 3302 receives as input the encoder input (b.sub.1,b',b.sub.2) as well as the 4 bits of the variable G',G'[1-4], from the partitioning unit 3300. It uses the map shown below in TABLE XVI, to determine its output, D[1-18]. The mapping unit 3302 generates D[1-18], which comprises 15 of the 18 final encoder output bits (u.sub.1,u',u.sub.2); the three remaining encoder output bits are not finalized at this stage. Instead, three auxiliary bits (aux1, aux2, aux3) are generated. The locations and values of the auxiliary bits, as seen in TABLE XVI, depends on the variable G', as seen in TABLE XVII. For G'=10, the mapping unit 3302 generates all the 18 encoder output bits. The auxiliary bits will be modified to accomplish the 0 mod 3 requirement of the code. The auxiliary bits are chosen using TABLE XVII.

It should be noted that the values for TABLE XVI, other than the auxiliary bits (aux1, aux2, aux3) are generated using the same equations an maps as specified above for Code 5.

Referring now to FIG. 34, the preferred embodiment for the modification unit 3306 will be described. As noted above, the modification unit 3306 receives the input bits (b.sub.1,b',b.sub.2) (more particularly the two bits of b'), the G'[1-4] bits from the partition unit 3300, and the output bits D[1-18] from the mapping unit 3302, and generates the encoded output word, (u.sub.1,u',u.sub.2) such that it will contain 0 mod 3 ones after precoding. The modification unit 3306 essentially changes the auxiliary bits of D[1-18] such that after precoding the bits will have 0 mod 3 ones. The modification unit 3306 preferably comprises a parallel precoder 3400, an auxiliary bit selector 3402 and an output multiplexer 3406.

As shown in FIG. 34, the parallel precoder 3400 has inputs coupled to receive the output bits, D[1-18], of the mapping unit 3302, which includes the 3 auxiliary bits, and the variable G' as input. From these inputs the parallel precoder 3400 generates two variables: a 2-bit variable p[1-2] and 1-bit variable M. The first variable, p[1-2], represents the number of ones mod 3 in the encoder output after precoding if the Table XVI values, D[1-18], are used as the encoder output. The second variable, M, represents the output of the precoder 14 for the codeword bit immediately to the left of the first auxiliary bit. Incidentally, the variable M is the state of the precoder 14 when the input to the precoder 14 is the first auxiliary bit. The variable M is used to determine the modification that will be made to the auxiliary bits to ensure 0 mod 3 ones in the output.

The relationships between the variables p[1-2] and M and the parallel precoder 3400 input D[1-18] and G'[1-4] can be described as follows: ##EQU14## where b.sub.i =a.sub.i .sym.b.sub.i-1 for i>1, and b.sub.1 =a.sub.1.

The variable p[1-2] is a binary representation of the ternary variable S. To reduce the time necessary to compute S, the above sum is broken into three sums and then it is simplified as follows:

First, let pre1[1-6], pre2[1-6], and pre3[1-6] be defined as follows.

Further, let D.sub.i denote D[i]. Then, ##EQU15## In the above, C1=-2pre1[6]+1, and C2=-2(pre1[6].sym.pre2[6])+1.

Letting S1, S2, and S3 to represent ##EQU16## we rewrite S as

We let 2-bits variables p1[1-2], p2[1-2], and p3[1-2] denote binary representations of the ternary variable S1, S2 and S3, respectively, i.e., for i=1, 2, and 3. ##EQU17## To further reduce the total calculation time, we note that if mod 3 values of 0, 1, and 2 are mapped onto 2-bits variables as in the above, identifying 11 with 00, -pi[1-2] can be accomplished by a simple inversion of pi[1-2] bits.

Referring now to FIG. 35, a preferred embodiment for the parallel precoder 3400 is shown. The parallel precoder 3400 comprises a plurality of six-bit precoders 3500, 3502, 3504, a plurality of six-bit mod 3 adders 3508, 3510, 3512, 3516, a M multiplexer 3514, an exclusive-OR gate 3524, inverters 3526, 3522 and multiplexers 3518, 3520. The output bits D[1-18] from the mapping unit 3302 are broken into 3 sets: D[1-6], D[7-12], and D[13-18]. These three six-bits sets are input to respective six-bit precoders 3500, 3502, 3504 that generate the output signals pre1[1-6], pre2[1-6], respectively, based on equations EQ16-EQ18 above. The outputs of each of the six-bit precoders 3500, 3502, 3504 are coupled to a respective six-bit mod 3 adders 3508, 3510, 3512 to generate sums, S1, S2, and S3 which are output by the six-bit mod 3 adders 3508, 3510, 3512 as p1[1-2], p2[1-2], and pr[1-2], respectively.

The signals p2[1-2] and p3[1-2], are inverted by inverters 3526 and 3522 respectively. The signals p2[1-2] and p3[1-2], and their inverses are applied to the inputs of the multiplexers 3518 and 3520. Based on the value of C1=-2pre1[6]+1 and C2=-2(pre1[6].sym.pre2[6])+1, the output of the multiplexers 3518 and 3520, respectively, p2'[1-2] and p3'[1-2] are generated. More specifically,

Thus, the pre1[6] signal is used as the select control input to multiplexer 3518, and the result of exclusive-ORing the pre1[6] signal with the pre2[6] signal is used as the select control input to multiplexer 3520. The output of the six-bit mod 3 adder 3508, and the multiplexers 3518 and 3520 are then concatenated, and input to the six-bit mod 3 adder 3516. Finally, the variable p[1-2] is computed by the six-bit mod 3 adder 3516 based on TABLE XVIII.

Referring to FIG. 35, the variable M is computed in the parallel precoder 3400 by the M multiplexer 3514. The M multiplexer 3514 is coupled to receive signals pre1[3,5,6] from six-bit precoder 3500, pre2[2,6] from six-bit precoder 3502, pre3[3,4] from six-bit precoder 3504, and bit G'[1-4], and it generates M based on the below equations: ##EQU18##

Referring back to FIG. 34, the coupling of the auxiliary bit selector 3402 is also shown. The auxiliary bit selector 3402 has inputs coupled to receive the G'[1-4] from the partition unit 3300 and b' of the input bits. The auxiliary bit selector 3402 also receives the p[1-2] and M signals from the parallel precoder 3400. In order to ensure 0 mod 3 ones in the final output, the auxiliary bit selector 3402 modifies the auxiliary bits. The auxiliary bit selector 3402 generates 3 new auxiliary bits (aux'[1-3])according to the TABLE XIX below. The output of the auxiliary bit selector 3402 is coupled to the output multiplexer 3406 to provide the new auxiliary bits. The significance of the new auxiliary bits (aux'[1-3]) is that if the original auxiliary bits (aux[1-3]) are replaced by the new auxiliary bits (aux'[1-3]), then the number of ones after precoding will be 0 mod 3 over the length of each codeword. Note that if the variable p, the number of ones mod 3, is equal to zero, then no modification need to take place and the auxiliary bit selector 3402 merely passes the current auxiliary bits through to the output (aux').

Referring again to FIG. 34, the coupling of the output multiplexer 3406 will be described. The output multiplexer 3406 is preferably coupled to the auxiliary bit selector 3402 to receive the modified auxiliary bits (aux'[1-3]) from the auxiliary bit selector 3402, the G'[1-4] from the partition unit 3300, and the D[1-18] from the mapping unit 3302. The output multiplexer 3406 preferably combines the modified auxiliary bits, aux'[1-3], and the output bits, D[1-18], from the mapping unit 3302. The output multiplexer 3406 uses variable G' from the partition unit 3300 as a control signal to determine where the auxiliary bits, aux'[1-3], are placed in the final encoder output (u.sub.1,u',u.sub.2). The modified auxiliary bits are placed in the same positions as the original auxiliary bits (aux[1-3]) in TABLE XVI. This output is then used as the final encoder output (u.sub.1,u',u.sub.2).

Referring now to FIG. 36, a fifth embodiment of the code de-converter 502h constructed according to the present invention to decode words encoded using Code 6 is shown. The Code 6 de-converter 502h is defined here in terms of the same variables used for encoding namely that an encoded 18-bit word, u.sub.1 (k) . . . u.sub.18 (k), defined to be variable U=(u.sub.1,u',u.sub.2) where u.sub.1 =u.sub.11, . . . ,u.sub.17 ; u.sub.2 =u.sub.21, . . . ,u.sub.27 and u'=u'.sub.1,u'.sub.2,u'.sub.3,u'.sub.4 is received by the Code 6 de-converter 502h, and in response the Code 6 de-converter 502h generates a 16-bit word, b'.sub.1 (k) . . . b'.sub.16 (k) which is defined to be variable B=(b.sub.1, b', b.sub.2) where b.sub.1 =b.sub.11, . . . ,b.sub.17 ; b.sub.2 =b.sub.21, . . . ,b.sub.27 and u'=u'.sub.1,u'.sub.2, as best illustrated in FIG. 36. The Code 6 de-converter 502h preferably is constructed similar the Code 4 de-converter 502e shown in FIG. 31 in that the Code 6 de-converter 502h comprises a partitioning unit and a mapping unit. Since such a configuration has been described above for codes 4 and 5, the description here of the Code 6 de-converter 502h will be limited to the partitioning identified by column 1 of TABLE XX below, and the mapping shown in columns 2 through 5 of TABLE XX. The mapping unit preferably uses the following equations to decode the input signal and re-produce the original signal.

Where:

and where the mapping and equations for generating the values of TABLE XX are the same as those identified above for Code 5.

Referring again to FIGS. 28-31, an ninth embodiment of the code generator will be described. For simplicity and ease of understanding, the description of the Code 7 code generator will focus on those aspects that are different from the Codes 4'-6. For example, Code 7 uses the same maps and equations as the f map; the f.sup.-1 map; the g map, and the g.sup.-1 map described above for Code 5, and has the same general structure as the code generator 154e for Code 4, and uses the same variable definitions as code 4. Therefore, they will not be described again here. For convenience and ease of notation and understanding, the variable U will also be referred to as variable a where (b.sub.1, y.sub.1 y.sub.2, b.sub.2)=(a.sub.1 , . . . , a.sub.18).

Code 7 differs from the previous codes in the following respects. First, the partition is defined by the following equations:

Partition of data words: (b.sub.1, y, b.sub.2)

Second, the mapping unit performs the mapping from row to row according to the map defined below in TABLE XXI

where:

and the h.sub.1 and h.sup.-1.sub.1 maps are defined as follows:

Third, the code de-converter for Code 7 performs the mapping from row to row according to the map defined below in TABLE XXII.

Similar to Code 7, Code 8 will be described below primarily by reference to portions of the Codes 1-7 already described above, and by highlighting the differences between the previous codes and Code 8. Code 8 uses the same a variable notation as Codes 4 and 7 for defining the input and output signals. Code 8 also uses the same partitioning as Code 4, but limited to G1 to G8; and the same auxiliary maps as Code 4 as described above in TABLES V through IX.

However, Code 8 preferably encodes using the map defined by TABLE XXIII.

Where,

P is chosen such that the following equation is satisfied:

and the remaining values of TABLE XXIII are determined using the same equations defined above for Code 4 as part of TABLE IV on page 36-37. Code 8 as described by TABLE XXIII has N=8, Z=10.

Furthermore, the code de-converter for Code 8 consists of eight maps as defined below in TABLE XXIV.

where

and the remaining values of TABLE XXIV are determined using the same equations defined above for Code 4 as part of TABLE X on page 41-42.

Code 9 provides yet another embodiment of the encoder and decoder constructed according to the present invention. Code 9 is very similar to Code 7 and uses the same variable or signal definitions and maps as Code 7 including the f map; the f.sup.-1 map; the g map, the g.sup.-1 map, the h.sub.1 map and the h.sup.-1.sub.1 map described above on pages 49, 53-54, and 69 and 70.

Code 9, however uses a different partition for the encoding the words as defined by the following equations:

Partition of data words: (b.sub.1, y, b.sub.2)

Code 9 also uses a unique mapping defined by TABLE XXV. The mapping for code 9 is as follows:

and where the value for the mapping are defined as follows:

(q.sub.1,q.sub.2,q.sub.3)=f(b.sub.2)

(m.sub.1,m.sub.2,m.sub.3)=f(b.sub.1)

(l.sub.11,l.sub.12,l.sub.13,l.sub.14,l.sub.15,l.sub.16)=h.sub.1 (b.sub.1)

(l.sub.21,l.sub.22,l.sub.23,l.sub.24,l.sub.25,l.sub.26)=h.sub.1 (b.sub.2)

(r.sub.11,r.sub.12,r.sub.13,r.sub.14,r.sub.15)=g(b.sub.2)

(r.sub.21,r.sub.22,r.sub.23,r.sub.24,r.sub.25)=g(b.sub.1)

(t.sub.1,t.sub.2,t.sub.3,t.sub.4,t.sub.5)=g(b.sub.1)

(c.sub.1,c.sub.2,c.sub.3,c.sub.4,c.sub.5)=g(b.sub.2)

Code 9 also provides a mapping for decoding as defined by TABLE XXVI. The decoder mapping for code 9 is as follows:

Finally, Code 10 provides still another embodiment of the encoder and decoder constructed according to the present invention. Code 10 is very similar to Code 7 and uses the same variable or signal definitions and maps as Code 7 including the f map; the f.sup.-1 map; the g map, the g.sup.-1 map, the h.sub.1 map and the h.sup.-1.sub.1 map described above on pages 49, 53-54, and 69 and 70.

Code 10, however, uses a different partition as defined below in TABLE XXVII, a different encoding map as defined below in TABLE XXVIII, an a different decoding map as defined below in TABLE XXIX.

where:

The code 1 encoder 12a produces the following parameters when used with a 1/(1.sym.D.sub.2) precoder and a 1-D.sup.2 partial response (PR) channel: N=9, Z=17, Z.sub.i =arbitrarily long sequence of zeros in even or odd bit positions, and E=3 The following Propositions stated in APPENDIX A are based on Corollaries 2.1, 2.4, and LEMMA 2 set forth in U.S. Pat. No. 5,196,849, entitled "Method and Apparatus For Implementing PRML Codes With Maximum Ones", by Richard L. Galbraith.

Proposition 1: Code 1 generates a Hamming distance of 2 at the output of a 1/(1.sym.D.sup.2) precoder.

Proof:

Let x=[x.sub.1 . . . x.sub.18 ] be the output of the precoder corresponding to the precoder input v=[v.sub.1 . . . v.sub.18 ]. Then, based on Corollaries 2.1 and 2.4, we have ##EQU21##

Therefore, code 1 generates a Hamming distance of 2 at the output of a 1/(1.sym.D.sup.2) precoder.

Proposition 2: Given a Hamming distance 2 after precoding, and given a rate 16/18, the minimal number of 9 ones per codeword at the output of the channel filter is the best possible.

Proof: Let N.sub.11 denote the number of binary vectors, v=[v.sub.1 . . . v.sub.18 ], of weight w.gtoreq.11. Thus, we have ##EQU22## it follows that the minimum number of 11 ones per codeword is not feasible given a rate 16/18.

Next, we show that 10 ones is also not feasible either given a rate 16/18 and Hamming distance 2. To this end, there are N.sub.10 binary vectors, v=[v.sub.1 . . . v.sub.18 ], of weight w.gtoreq.10. Thus we have ##EQU23## Now, let us define N.sub.10 (even) and N.sub.10 (odd) as follows: N.sub.10 (even)=# of v=[v.sub.1 . . . v.sub.18 ] of weight.gtoreq.10 such that v.sub.1 +v.sub.2 +v.sub.5 +v.sub.6 +v.sub.9 +v.sub.10 +v.sub.13 +v.sub.14 +v.sub.17 +v.sub.18 is even.

N.sub.10 (odd)=# of v=[v.sub.1 . . . v.sub.18 ] of weight.gtoreq.10 such that v.sub.1 +v.sub.2 +v.sub.5 +v.sub.6 +v.sub.9 +v.sub.10 +v.sub.13 +v.sub.14 +v.sub.17 +v.sub.18 is odd.

Therefore, we have

and

Accordingly, regardless of the value of current state cs, the conditions of LEMMA 2 cannot be satisfied with any rate 16/18 code. Q.E.D.

Proposition 3: Code 2 generates a Hamming distance of 2 at the output of the 1/(1.sym.D.sup.2) precoder.

Proof: See proof of Proposition 1.

We note that code 2 has only one codeword generating 8 ones at the output of the 1-D.sup.2 channel filter, and the rest of its codewords generate at least 9 ones.

Proposition 4: Code 3 generates a Hamming distance of 2 at the output of the 1/(1.sym.D.sup.2) precoder.

Proof: See proof of Proposition 1.

Let E be as a subset of {0,1}.sup.n1 and F be a subset of {0,1}.sup.n2. Elements in E can be represented by m.sub.1 =.left brkt-top.log.sub.2 .vertline.E.vertline..right brkt-top. bits and elements in F by m.sub.2 =.left brkt-top.log.sub.2 .vertline.F.vertline..right brkt-top. bits. Therefore, the elements of the set E.times.F can be represented by m.sub.1 +m.sub.2 =.left brkt-top.log.sub.2 .vertline.E.vertline.+log.sub.2 .vertline.F.vertline..right brkt-top.=bits. This representation has an interesting property, namely, if only the first m.sub.1 bits are corrupted, then the element of F can be decoded based on the last m.sub.2 bits. On the other hand, if only the last m.sub.2 bits are corrupted, then the element of E can be decoded based on the first m.sub.1 bits. Sometimes, it is possible to represent E.times.F with m.sub.1 +m.sub.2 bits and still satisfy a property similar to the one mentioned above.

LEMMA: Let E be as a subset of {0,1}.sup.n1 and F be a subset of {0,1}.sup.n2. Also, let .vertline.E.vertline..ltoreq.p.sub.1 xq.sub.1 and .vertline.F.vertline..ltoreq.p.sub.2 xq.sub.2, then elements in E.times.F can be represented by n.sub.1 +n.sub.2 +n.sub.3 bits, where n.sub.1 =.left brkt-top.log.sub.2 p.sub.1 .right brkt-top., n.sub.2 =.left brkt-top.log.sub.2 q.sub.1 .right brkt-top., n3.sub.2 =.left brkt-top.log.sub.2 (q.sub.1 p.sub.2).right brkt-top..

Proof: We list the elements of in a p.sub.1 xq.sub.1 table, and list the elements of F in a p.sub.2 .times.q.sub.2 table. To represent an element (e,f) in E.times.F, we represent the row of e by n.sub.1 =.left brkt-top.log.sub.2 p.sub.1 .right brkt-top. bits, the column of f by n.sub.2 =.left brkt-top.log.sub.2 q.sub.1 .right brkt-top., and the column of e and row of f by n.sub.3 =.left brkt-top.log.sub.2 (q.sub.1 p.sub.2).right brkt-top. bits.

In the representation of E.times.F suggested by the above lemma, if only the n.sub.1 bits are corrupted, then the element of F can be decoded based on n.sub.2 and n.sub.3 bits. On the other hand, if only the n.sub.3 bits are corrupted, then the element of E can be decoded based on n.sub.1 and n.sub.2 bits. Furthermore, in some cases, the above lemma produces a representation with n.sub.1 +n.sub.2 +n.sub.3 bits that is one less than m.sub.1 +m.sub.2. For instance, let's suppose .vertline.E.vertline.=35=7.times.5=p.sub.1 xq.sub.1, and .vertline.F.vertline.=21=3.times.7=p.sub.2 .times.q.sub.2, then m.sub.1 +m.sub.2 =6+5=3+4+3+1=n.sub.1 +n.sub.2 +n.sub.3 +1. This construction is used on most of the codes 4-10.