US 6,084,261 AGrant
DRAM Cell With a Fork-Shaped Capacitor
Issue Date:2000-07-04
•16 Claims
•6 Drawing Sheets
Abstract
A fork-shaped capacitor of a dynamic random access memory cell is disclosed. This capacitor includes a semiconductor layer (110), and a first dielectric layer (119) formed over the semiconductor layer. The capacitor also includes a first conductive region (118) formed on a portion of the first dielectric layer, the first conductive region communicating to the semiconductor layer via a hole in the first dielectric layer. At least two second conductive regions (122) are formed on the first conductive region, each of the conductive regions being spaced from each other. Further, at least two third conductive regions (126) are formed on the first dielectric layer, each of the third conductive regions being spaced from each other, each of the third conductive regions being spaced from each of the second conductive regions, wherein a portion of each of the third conductive regions abuts a sidewall of the first conductive region. Finally, the capacitor includes a second dielectric film (136) formed on surface of the first conductive region, the second conductive regions, and the third conductive regions; and a conductive layer (138) formed on the second dielectric film.
Metadata
Inventor
- Shye-Lin Wu
Application Information
Application Number:US 2325527
Filing Date:1999-01-18
Priority Date:1998-01-26
Art Unit:285
Classifications
IPC:
H07L 27108
Field of Search:
257306-309
Patent Drawings (6 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) fabrication, and more particularly, to a dynamic random access memory cell with a fork-shaped capacitor.
2. Description of the Prior Art
The increasing popularity of electronic equipment, such as computers, is increasing the demand for large semiconductor memories. FIG. 1 shows a simplified diagram of the organization of a typical large semiconductor memory 14. The storage cells of the memory 14 are arranged in an array including horizontal rows and vertical columns. The horizontal lines connected to all of the cells in the row are referred to as word lines 11, and the vertical lines connected to all of the cells in the column are referred to as bit lines 13. Data flow into and out of the cells via the bit lines 13.
Row address 10 and column address 12 are used to identify a location in the memory 14. A row address buffer 15 and a column address buffer 17, respectively, receive row address 10 signals and column address 12 signals. The buffers 15 and 17 then drive these signals to a row decoder 16 and column decoder 18, respectively. The row decoder 16 and the column decoder 18 then select the appropriate word line and bit line corresponding to the received address signal. The word and bit lines select a particular memory cell of the memory 14 corresponding to the received address signals. As is known in the art of semiconductor memory fabrication, the row decoder 16 and the column decoder 18 reduce the number of address lines needed for accessing a large number of storage cells in the memory 14.
The array configuration of semiconductor memory 14 lends itself well to the regular structure preferred in "very large scale integration" (VLSI) ICs. For example, the memory 14 can be a dynamic random access memory (DRAM). DRAMs have become one of the most widely used types of semiconductor memory due to its low cost per bit, high device density and flexibility of use concerning reading and writing operations.
Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. A circuit schematic diagram corresponding to this structure is shown in FIG. 2A. The gate of the transistor 20 is controlled by a word line signal, and data, represented by the logic level of a capacitor voltage, is written into or read out of the capacitor 22 through a bit line. FIG. 2B shows the cross-section of a traditional one-transistor DRAM storage cell that uses a polysilicon layer 24 as one plate of the capacitor. The substrate region under the polysilicon plate 24 serves as the other capacitor electrode. A voltage can be applied to the plate 24 to store a logic value into the capacitor.
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks. Thus, the capacitance of the capacitor is reduced owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, thereby achieving both high cell integration and reliable operation.
One approach for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this approach, the polysilicon layer implementing the capacitor electrodes may have protrusions, fins, cavities, etc., to increase the surface area of the capacitor electrode, thereby increasing the capacitor's capacitance while maintaining the small area occupied on the substrate surface. Consequently, this type of capacitor has come to be widely used in DRAM devices.
Summary of the Invention
In accordance with the present invention, a fork-shaped capacitor of a dynamic random access memory cell is disclosed that substantially increases the surface of the capacitor. In one embodiment, the capacitor includes a semiconductor layer, and a first dielectric layer formed over the semiconductor layer. The capacitor also includes a silicon oxide layer formed on the first dielectric layer, wherein the silicon oxide layer includes a top surface. A first conductive region is formed on a portion of the silicon oxide layer, wherein the first conductive region includes a top surface, and the first conductive region communicates to the semiconductor layer via a hole in the silicon oxide layer and the first dielectric layer. Further, a pair of second conductive regions abutting the top surface of the first conductive region is provided, each of the pair of second conductive regions being spaced from each other. A pair of third conductive regions abutting the top surface of the first dielectric layer is also provided, each of the pair of third conductive regions being spaced from each other, each of the pair of third conductive regions being spaced from each of the pair of second conductive regions, wherein a portion of each of the pair of third conductive regions abuts a sidewall of the first conductive region. Finally, a second dielectric film is formed on surface of the first conductive region, the pair of second conductive regions, and the pair of third conductive regions; and a conductive layer is formed on the second dielectric film.
Brief Description of the Drawings
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 shows a simplified diagram illustrative of the organization of a typical large semiconductor memory;
FIG. 2A shows a circuit schematic diagram of a typical one-transistor dynamic random access memory (DRAM) cell;
FIG. 2B shows a cross-sectional view illustrative of traditional one-transistor DRAM storage cell; and
FIGS. 3-10 show cross-sectional views illustrative of various stages in the fabrication of a DRAM capacitor in accordance with the present invention.
Description of the Preferred Embodiment
FIG. 3 shows a cross-sectional view illustrative of a portion of a dynamic random access memory (DRAM) cell in accordance with one embodiment of the present invention, wherein a dielectric layer 112, such as tetraethylorthosilicate (TEOS) or boro-phosphosilicate glass (BPSG), is deposited on a semiconductor substrate 110. A silicon oxide layer 114 is then deposited on the dielectric layer 112. In this embodiment, this silicon oxide layer 114 is deposited using a conventional low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) process. The thickness of the silicon oxide layer 114 can range from about 1000 to 10000 angstroms. It is noted that a contact hole 116 is also formed in the silicon oxide layer 114 and the dielectric layer 112 so that a portion of the substrate 110, such as a source region, is exposed.
A first conductive layer 118 is then formed on the silicon oxide layer 114, therefore filling the contact hole 116. Conductive materials like polysilicon, metals, or metal compounds can be used. In this embodiment, the first conductive layer 118 is preferably selected from metals or metal compound materials. In the case, metals like titanium (Ti), tungsten (W), tantalum (Ta), Nickel (Ni), Palladium (Pd), Platinum (Pt), Cobalt (Co), Molybdenum (Mo), Strontium (Sr), Yttrium (Y), Ruthenium (Ru), Lead (Pb) or metal compounds like metal nitride, metal silicide, and metal oxide of above mentioned metals can be used to serve as a portion of the conductive electrode of the capacitor structure. Some commonly employed materials in present semiconductor manufacturing process include titanium nitride, tungsten nitride, tantalum nitride, and tungsten silicide. The metal or metal compound can be deposited with a chemical vapor deposition (CVD) process. A sputtering process can be used alternatively to deposit the metals or metal compound. By employing a metal or metal compound material as a portion of the capacitor electrode, the conductivity of the plate and the operational characteristics of the capacitor can be greatly increased. The first conductive layer 118 can be deposited with a thickness of about 1000-6000 angstroms above the surface of the silicon oxide layer 114.
In order to adopt the physical and electrical characteristics between different materials, a barrier layer like titanium nitride can be employed between the deposited metal or metal compound and the silicon substrate 110. The conductivity of the interface connection can be increased with the barrier layer. A dielectric layer 119, such as silicon nitride, is deposited on the first conductive layer 118 to a thickness of about 3000-10000 angstroms. In this embodiment, the silicon nitride layer 119 is deposited using a conventional low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
A photoresist layer 120 is then formed and patterned on the silicon nitride 119 using conventional photolithographic techniques, defining a storage node region using conventional etch process in the silicon nitride layer 119 as shown in FIG. 4.
After the photoresist layer 120 is removed, a second conductive layer 122 is deposited on the silicon nitride layer 119 and the first conductive layer 118 as shown in FIG. 5. Conductive materials like polysilicon, metals, or metal compounds can be used. In this embodiment, the second conductive layer 122 is preferably selected from metals or metal compound materials. In the case, metals like titanium (Ti), tungsten (W), tantalum (Ta), Nickel (Ni), Palladium (Pd), Platinum (Pt), Cobalt (Co), Molybdenum (Mo), Strontium (Sr), Yttrium (Y), Ruthenium (Ru), Lead (Pb) or metal compounds like metal nitride, metal silicide, and metal oxide can be used to serve as a portion of the conductive electrode of the capacitor structure. Some commonly employed materials in present semiconductor manufacturing process include titanium nitride, tungsten nitride, tantalum nitride, and tungsten silicide. The metal or metal compound can be deposited with a chemical vapor deposition (CVD) process. A conformal layer of conductive layer can be formed with the process to form the second conductive layer 122. A sputtering process can be used alternatively to deposit the or metal compound. The thickness of the second conductive layer 122 can be about 300-3000 angstroms in the embodiments. By employing metal or metal compound material as a portion of the capacitor electrode, the conductivity of the plate and the operational characteristics of the capacitor can be greatly increased. A barrier layer can also be employed if an interface between silicon and metals or metal compounds is presented.
Next, referring to FIG. 6, a dielectric spacer 124, such as silicon nitride spacer, is formed on the sidewall of the second conductive layer 122. This silicon nitride spacer 124 is preferably formed by firstly blanket depositing a silicon nitride layer 124 over the second conductive layer 122, followed by etching back to form the silicon nitride spacer 124. In this embodiment, the silicon nitride layer 124 is deposited using a conventional low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
Referring to FIG. 7, the second conductive layer 122 and the first conductive layer 118 are etched back using the silicon nitride layer 124 as a mask until the surfaces of the silicon nitride layer 119 and the silicon oxide layer 114 are exposed. The etching of the second conductive layer 122 and the first conductive layer 118 is preferably done, for example, by a plasma etching process in this embodiment.
Third conductive spacers 126 are formed on the sidewalls of the silicon nitride spacer 124, the second conductive layer 122, and the first conductive layer 118 as shown in FIG. 8. Conductive materials like polysilicon, metals, or metal compounds can be used. In this embodiment, the third conductive spacers 126 are preferably selected from metal or metal compound materials. In the case, metals like titanium (Ti), tungsten (W), tantalum (Ta), Nickel (Ni), Palladium (Pd), Platinum (Pt), Cobalt (Co), Molybdenum (Mo), Strontium (Sr), Yttrium (Y), Ruthenium (Ru), Lead (Pb) or metal compounds like metal nitride, metal silicide, and metal oxide can be used to serve as a portion of the conductive electrode of the capacitor structure. Some commonly employed materials in present semiconductor manufacturing processes include titanium nitride, tungsten nitride, tantalum nitride, and tungsten silicide. As mentioned above, the metal or metal compound can be deposited with a chemical vapor deposition (CVD) process. A conformal layer of conductive layer can be formed with the process to form the second conductive layer 122. A sputtering process can be used alternatively to deposit the metal or metal compound. The thickness of the second conductive layer 122 can be about 300-3000 angstroms in the embodiments. This third conductive spacers 126 are preferably formed by firstly blanket depositing a conformal layer over the structure of FIG. 7, followed by etching back to form the third conductive spacers 126.
After removing the silicon nitride layer 119 and the silicon nitride layer 124, for example, by hot phosphoric acid (H.sub.3 PO.sub.4) solution, a fork-shaped bottom electrode of the DRAM cell is thus formed as shown in FIG. 9.
Referring to FIG. 10, a dielectric film 136 and a top electrode 138 of the DRAM cell capacitor can then be formed in the conventional manner. In this embodiment, a thin dielectric layer 136, such as stacked oxide-nitride-oxide (ONO) film, is formed on the exposed surface of the bottom electrode (i.e., the storage node including conductive regions 118, 122, and 126) and the surface of the silicon oxide layer 114. As is known in the art of DRAM fabrication, the ONO film is reliable over shaped silicon surfaces, and is typically used as a capacitor insulator. The bottom oxide layer of the stacked oxide-nitride-oxide (ONO) film 136 is conventionally formed by thermally oxidizing the silicon surface, depositing an LPCVD silicon nitride layer and then oxidizing the silicon nitride layer to form the top oxide layer. Other materials such as NO, Ta.sub.2 O.sub.5, TiO.sub.2, PZT, BST, PLZT, PST, Al.sub.2 O.sub.3, and Y.sub.2 O.sub.3 can be used as the thin dielectric layer 136. A conductive layer 138 is then deposited over the stack oxide/silicon nitride/oxide layer 136 to serve as an upper plate of the DRAM cell capacitor. Typically, the conductive layer 138 can be a layer of polysilicon, metals, metal compound, or metal silicide as described above.
Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from the spirit which is intended to be limited solely by the appended claims.
Claims
What is claimed is:
1. A capacitor of a dynamic random access memory cell, said capacitor comprising: a semiconductor layer; a first dielectric layer formed over said semiconductor layer; a silicon oxide layer formed on said first dielectric layer; a first conductive region formed on a portion of said silicon oxide layer, said first conductive region communicating to said semiconductor layer via a hole in said first dielectric layer; at least two second conductive regions formed on said first conductive region, each of said at least two second conductive regions being spaced from each other; at least two third conductive regions formed on said silicon oxide layer, each of said at least two third conductive regions being spaced from each other, each of said at least two third conductive regions being spaced from each of said at least two second conductive regions, wherein a portion of each of said at least two third conductive regions abuts a sidewall of said first conductive region; a second dielectric film formed on surface of said first conductive region, said at least two second conductive regions, and said at least two third conductive regions; and a conductive layer formed on said second dielectric film.
2. The capacitor according to claim 1, wherein said first dielectric layer comprises silicon nitride.
3. The capacitor according to claim 1, wherein said first conductive region comprises an element chosen from the group consisting of doped polysilicon, metals, and metal compounds.
4. The capacitor according to claim 1, wherein said second conductive regions comprise an element chosen from the group consisting of doped polysilicon, metals, and metal compounds.
5. The capacitor according to claim 1, wherein said third conductive region comprise an element chosen from the group consisting of doped polysilicon, metals, and metal compound.
6. The capacitor according to claim 1, wherein said second dielectric film comprises an element chosen from the group consisting of oxide-nitride-oxide (ONO), NO, Ta.sub.2 O.sub.5, TiO.sub.2, PZT, BST, PLZT, PST, Al.sub.2 O.sub.3, and Y.sub.2 O.sub.3.
7. The capacitor according to claim 1, wherein said conductive layer comprises an element chosen from the group consisting of doped polysilicon, metals, metal compounds and silicide.
8. A capacitor of a dynamic random access memory cell, said capacitor comprising: a semiconductor layer; a first dielectric layer formed over said semiconductor layer; a silicon oxide layer formed on said first dielectric layer, said silicon oxide layer including a top surface; a first conductive region formed on a portion of said silicon oxide layer, said first conductive region including a top surface, said first conductive region communicating to said semiconductor layer via a hole in said silicon oxide layer and said first dielectric layer, said first conductive region comprising an element chosen from the group consisting of metals and metal compounds; a pair of second conductive regions abutting the top surface of said first conductive region, each of said pair of second conductive regions being spaced from each other, said second conductive regions comprising an element chosen from the group consisting of said metals and said metal compounds; a pair of third conductive regions abutting the top surface of said first dielectric layer, each of said pair of third conductive regions being spaced from each other, each of said pair of third conductive regions being spaced from each of said pair of second conductive regions, wherein a portion of each of said pair of third conductive regions abuts a sidewall of said first conductive region, said third conductive regions comprising an element chosen from the group consisting of said metals and said metal compounds; a second dielectric film formed on surface of said first conductive region, said pair of second conductive regions, and said pair of third conductive regions; and a conductive layer formed on said second dielectric film.
9. The capacitor according to claim 8, wherein said first dielectric layer comprises silicon nitride.
10. The capacitor according to claim 8, wherein said second dielectric film comprises an element chosen from the group consisting of oxide-nitride-oxide (ONO), NO, Ta.sub.2 O.sub.5, TiO.sub.2, PZT, BST, PLZT, PST, Al.sub.2 O.sub.3, and Y.sub.2 O.sub.3.
11. The capacitor according to claim 8, wherein said conductive layer comprises an element chosen from the group consisting of doped polysilicon, said metals, said metal compounds and silicide.
12. The capacitor according to claim 8, wherein said first dielectric layer comprises tetraethylorthosilicate (TEOS).
13. The capacitor according to claim 8, wherein said first dielectric layer comprises boro-phosphosilicate glass (BPSG).
14. The capacitor according to claim 8, wherein said first conductive region comprises an element chosen from the group consisting of metal nitride, metal silicide, and metal oxide.
15. The capacitor according to claim 8, wherein said second conductive regions comprise an element chosen from the group consisting of metal nitride, metal silicide, and metal oxide.
16. The capacitor according to claim 8, wherein said third conductive regions comprise an element chosen from the group consisting of metal nitride, metal silicide, and metal oxide.