Method for Preventing Micromasking in Shallow Trench Isolation Process Etching

The present invention concerns the fabrication of integrated circuits and pertains particularly to a method for preventing micromasking in shallow trench isolation process etching.

In fabricating integrated circuits, various processes are used to form field oxide. For example, a local oxidation of silicon (LOCOS) process is often used to form field oxide regions. In a LOCOS process, a layer of pad oxide is formed. On top of the pad oxide, a layer of nitride is formed. The nitride is patterned and etched. Field oxide is grown on the substrate at places where the nitride has been etched to expose the substrate. The nitride and pad oxide are then removed.

Shallow trench isolation (STI) is gradually replacing conventional LOCOS process for the formation of an isolation structure as technology is evolving to submicron geometry. STI has various advantages over the conventional LOCOS process. For example, STI allows for the planarization of the isolation structure. This results in better control of critical dimension (CD) when defining a gate stack of a transistor. Better control of CD when defining the gate stack results in better control of CD in further processing steps which occur after the gate stack is defined.

During conventional STI process, a buffer oxide/nitride mask is patterned onto the silicon wafer to define the trench area. Before a trench etch is performed, a cleaning is performed with wet chemicals such as sulfuric acid and hydrogen peroxide, typically ending with a spin-rinse-dry (SRD). The trench area is etched and filled by chemical vapor deposition (CVD) with a fill oxide so that, for an average trench width, local planarization between the trench and the nitride mask is achieved. The fill oxide is then polished back by chemical mechanical polishing (CMP) or etched back by dry plasma etch until it is flush with the nitride layer. The nitride mask is then removed, leaving the fill oxide extending above the trench. The fill oxide is then further removed and a planar surface is provided. This further removal of the fill oxide is done by dry or wet plasma etching of the fill oxide.

Unfortunately, SRD tools are prone to leaving water spots which can induce micromasking. The micromasking can result in a leakage site resulting in defective parts.

In accordance with the preferred embodiment of the present invention, an isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.

While the present invention allows for use of a variety of chemicals and flow rates to form the plasma, in one embodiment, CF.sub.4 is introduced into an ashing environment at a flow rate of approximately 180 SCCM. H.sub.2 O vapor is then introduced into the ashing environment at a flow rate of approximately 300 SCCM.

In the preferred embodiment, before subjecting the trench area to an ashing environment, the trench area is cleaned with wet chemicals and a spin rinse dry is performed. For example, the wet chemicals include sulfuric acid and/or hydrogen peroxide.

After etching, the trench is filled, for example, with a fill oxide. A part of the fill oxide is removed so that a remaining part of the fill oxide remaining in the trench is above a top surface of the substrate. The nitride layer is then removed.

The present invention prevents micromasking over a trench area. The micromasking resulting from prior art methods can result in leakage sites.

FIG. 1 is a flowchart for a shallow trench isolation process in accordance with a preferred embodiment of the present invention.

FIGS. 2, 3, 4, 5, 6 and 7 illustrate the shallow trench isolation process described in FIG. 1 in accordance with a preferred embodiment of the present invention.

FIGS. 8, 9, 10 and 11 illustrate how not using the process set out in the flowchart in FIG. 1 can lead to formation of a leakage site.

FIG. 1 is a flowchart for a shallow trench isolation process in accordance with a preferred embodiment of the present invention. In a step 21, a layer of buffer (pad) oxide is formed on a substrate of a semiconductor wafer. For example, the layer of buffer oxide is formed by thermal oxidation of silicon to grow the oxide. The layer of buffer oxide is, for example, 200 Angstroms (.ANG.) thick. In a step 22, a layer of nitride is formed on top of the layer of buffer oxide. For example, the layer of nitride is formed by low pressure chemical vapor deposition (LPCVD, SiH.sub.2 Cl.sub.2 =NH.sub.3 .cndot. Dichlorosilane(Ammonia). The layer of nitride is, for example, 2000 .ANG. thick. In a step 23, the nitride and buffer oxide is patterned by a dry etch process to define a trench area.

In a step 24, a convention clean of the trench area is performed. The clean is performed, for example, with wet chemicals such as sulfuric acid and hydrogen peroxide. The clean typically ends with a spin-rinse-dry (SRD).

In a step 25, an additional clean is performed. Specifically, the semiconductor wafer is placed in an ashing environment such as, for example, an inductively coupled plasma. Although such an ashing environment is used in the present embodiment, the present invention is also well suited to the use of various other well known ashing environments.

In one embodiment, the ashing environment operates at a pressure of approximately 1.2 Torr and a power of approximately 1000 Watts. H.sub.2 O and CF.sub.4 are then introduced into the ashing environment to form an inductively coupled plasma. For example, H.sub.2 O is introduced at a flow rate of approximately 300 standard cubic centimeters per minute (SCCM). CF.sub.4 is introduced at a flow rate of approximately 180 SCCM. Alternatively, in another embodiment of the present invention, gaseous polyfluorocarbons such as C.sub.2 F.sub.6, or fluorinated hydrocarbons such as CHF.sub.3, instead of CF.sub.4, are introduced into the ashing environment at a flow rate of approximately 180 SCCM. Alternatively, other flow rates may be used to introduce the gases into the ashing environment. Also, other plasma sources such as microwave, can be used in place of the inductive coupled plasma.

For example, in one embodiment of the present invention, the ashing environment comprising H2.sub.O vapor and the gaseous fluorocarbon or a fluorinated hydrocarbon gas, efficiently and thoroughly removes water spots or polymer contaminants introduced over the trench area into residues. FIG. 2 illustrates the result of the completion of step 25. In FIG. 2, on top of a silicon substrate 30, sections 32 of a nitride layer are over sections of a buffer oxide layer 31. The trench area is clean.

FIG. 8 illustrates what can happen when step 25 is skipped. In FIG. 8, on top of a silicon substrate 50, sections 52 of a nitride layer are over sections of a buffer oxide layer 51. An impurity 57 remains on the trench area.

In a step 26, a trench is formed by, for example performing a dry etch of the silicon wafer. The dry etch can be one or more steps to etch the silicon and smooth out the sidewall profile. FIG. 3 illustrates the result of the completion of step 26. In FIG. 3, a trench 33 is shown etched in silicon substrate 30. For example, trench 33 is 0.5 microns wide and extends 0.4 microns below the surface of substrate 30.

FIG. 9 illustrates what can happen when step 25 is skipped. In FIG. 9, a trench 53 is shown etched in silicon substrate 50. For example, trench 53 is 0.5 microns wide and extends 0.4 microns below the surface of substrate 50. In a region 58, however, micromasking has occurred preventing full excavation of the trench.

In a step 27, the trench is filled by chemical vapor deposition (CVD) with a fill oxide so that, for an average trench width, local planarization between the trench and the nitride mask is achieved. For example, the CVD oxide extends 0.7 micron above the top surface of the nitride layer. FIG. 4 illustrates the result of the completion of step 27. In FIG. 4, fill oxide 35 has filled trench 33 (shown in FIG. 3). For example, fill oxide 35 extends 0.7 microns above the top surface of the nitride layer 32.

FIG. 10 illustrates what can happen when step 25 is skipped. In FIG. 10, fill oxide 55 has filled trench 53 (shown in FIG. 9). However, there is no oxide deposited in region 58 where micromasking occurred and the trench was not fully excavated.

In a step 28, the fill oxide is etched to a level just above the surface of the substrate. This etch is performed, for example, by a combination of chemical mechanical polish (CMP) process and a wet etch. The amount of fill oxide left above the surface of the substrate is such that future processing steps will remove/etch the remaining fill oxide, such that the remaining fill oxide will be aligned with, or slightly above the surface of the gate oxide.

FIG. 5 illustrates the result of the completion of step 28. In FIG. 5, fill oxide 35 has been etched to a level just above the top surface of buffer oxide layer 31. For example, fill oxide 35 extends 800 .ANG. above the top surface of the buffer layer 31.

In a step 29, the nitride is stripped away, for example, by a wet etch using a "hot" phosphoric acid solution. The result is shown in FIG. 6. In FIG. 6, nitride layer 32 (shown in FIG. 5) is removed.

After additional conventional processing steps, including polysilicon deposition, mask etch and strip, for example, a polysilicon region is formed over the trench area. FIG. 7 shows a polysilicon region 36 located over fill oxide 35. FIG. 11 illustrates what can happen when step 25 is skipped. A polysilicon region 56 is located over fill oxide 55. However, there is very little oxide between polysilicon region 56 and region 58 where micromasking occurred. This can result in a leak between the substrate and polysilicon region 56.

The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.