Image Display Apparatus

The present invention generally relates to an image display apparatus, and particularly to an image display apparatus capable of displaying image information signals of a plurality of different types in personal computers and of television signals.

Recently, so-called multimedia type image display apparatuses have been widely getting attention which can display on the same screen image information signals of different types such as output signals with much letter information from personal computers (hereinafter, abbreviated "PC") and television signals with chiefly images. In addition, as disclosed in, for example, JP-A-6-276462, these image display apparatuses have often used displays of the flat panel type having fixed pixels in which liquid crystals or plasma are used.

These image display apparatuses often have a plurality of input terminals, for example, input terminals for the output signals from PC, and input terminals for ED (Extended Definition) TV signals. One of the image types of these input terminals is selected by a signal change-over circuit in response to the order or command from the user. The input image signal produced from this signal change-over circuit is identified in its type (PC signal or TV signal) by an input signal discrimination circuit. The input image signal of the type identified as above is converted in its pixels by a pixel conversion circuit to be suited for the number of pixels of the display screen in accordance with the result from the signal discrimination circuit. The pixel information is displayed on the display screen. The above input signal discrimination circuit discriminates the type of the input image signal on the input image signal on the basis of the horizontal synchronizing frequency and vertical synchronizing frequency fed in superposition on or separately from the input image signal. In addition, the pixel conversion circuit sets a conversion coefficient (magnification or reduction rate) according to the discrimination result from the input signal discrimination circuit, and carries out pixel conversion process for the input image signal by use of the conversion coefficient.

When a signal of 640.times.480 pixels (horizontal synchronizing frequency of about 31.5 kHz, vertical synchronizing frequency of about 60 Hz) corresponding to, for example, VGA mode is applied to the PC signal input terminal of the image display apparatus which has (1024.times.768) pixels corresponding to XGA mode, the input signal discrimination circuit recognizes the input image signal as a PC signal corresponding to VGA from the horizontal and vertical synchronizing frequencies. The pixel conversion circuit sets the horizontal and vertical conversion coefficients (magnifying coefficients) to be 1.5 times, respectively. Then, the input image signal is magnified, or expanded in the horizontal and vertical directions by 1.5 times by use of the conversion coefficients, thus converting the input signal into a signal of 960.times.720 pixels.

Thus, when the input image signal is magnified, or expanded, new pixels for interpolation are required to be created and inserted into the input image signal. As this system for producing and inserting the interpolating pixels, the following system is chiefly known. In the following system it is assumed, for example, that pixels are converted from 2 dots to 3 dots (1.5 times magnification). FIGS. 3A and 3B briefly show the idea.

(a) As a first system, a pixel having the same image information (luminance, chromaticity and so on) as a certain pixel is used for the interpolation to be inserted adjacent to the certain pixel (see FIG. 3A).

(b) As a second system, the image information of two adjacent pixels are averaged into a pixel for the interpolation to be inserted between the two adjacent pixels (see FIG. 3B).

In the above conventional systems, the signal fed to the EDTV signal input terminal has its horizontal synchronizing frequency twice larger than the normal NTSC signal, or about 31.5 kHz, and its vertical synchronizing frequency of about 60 Hz. In other words, since the EDTV signal is the same format as the PC signal corresponding to the VGA mode fed from the PC signal input terminal, the input signal discriminating circuit recognizes the EDTV signal as the same signal as the VGA signal. Therefore, the pixel conversion circuit changes the pixel number so that the number of pixels of the EDTV signal is expanded or increased by 1.5 times as described above. The pixel conversion system is fixed to any one of the two systems mentioned above.

When the first system of the image conversion systems is applied to the PC signal with chiefly much letter information, the outlines of the letters or characters can be sharply displayed with no blur in the outlines or contour of the letters or characters. However, if it is applied to the EDTV signal which is chiefly for natural pictures, the outlines of an object become serrate, and thus the pictures are unnatural.

Conversely, when the second system is applied to the PC signal with chiefly much letter information, the outlines of the letters become dim or blurred. If however it is applied to the EDTV with chiefly natural images, natural pictures can be obtained.

Thus, in the conventional image display apparatus, since the image conversion system used is fixed to either first or second system, the apparatus using only the first system has the drawback that it is difficult to display the EDTV signal image naturally, or clearly, and the apparatus using only the second system has the disadvantage that it is difficult to display the letter information of the PC signal or the like clearly, or definitely.

Accordingly, in view of the above problems, it is an object of the invention to provide an image display apparatus for magnifying and displaying a plurality of different types of image signals, which is capable of displaying expanded images with high quality by performing a magnification process suited for a plurality of different types of the input image signals.

In order to achieve the above object, according to one aspect of the present invention, the pixel conversion means is provided with the first conversion mode and the second conversion mode, which are selectively switched in accordance with the result from the input signal discrimination means, thereby converting the input image signal by the selected conversion mode. In the first conversion mode, a pixel having the same image information as a certain pixel is inserted as an interpolation image to be adjacent to the certain pixel. In the second conversion mode, the image information of two adjacent pixels are averaged and used as a pixel for interpolation to be inserted between the two adjacent pixels. More specifically, when the input image signal is a PC signal, it is converted by the first conversion mode, and when the input image signal is a television signal, it is converted by the second conversion mode. Thus, both the image information signal from a PC and the television signal can be displayed with high quality by the appropriate conversion systems.

In addition, another signal conversion means may also be provided which converts the image information signal fed from an input terminal into a signal format equivalent to the image information signal fed from the other input signal. Therefore, there is no need to provide a plurality of conversion coefficients (magnification coefficients) in the image conversion means, thus making it possible that the image conversion means can be simplified in its construction.

The above signal conversion means may be one in which a television signal of a standard television system is converted into the VGA signal format. With the arrangement, the standard-television system television signal can be converted into the VGA signal format, thereby making it unnecessary for the pixel conversion means to have conversion coefficients (magnification coefficients) suitable for the standard television system, thereby simplifying the pixel conversion means in its construction.

FIG. 1 is a block diagram of the construction of a first embodiment of an image display apparatus according to the invention.

FIG. 2 is a block diagram of the construction of a second embodiment of an image display apparatus according to the invention.

FIGS. 3A and 3B are schematic diagrams to which reference is made in explaining the pixel conversion systems used in the invention.

FIG. 4 is a schematic diagram to which reference is made in explaining the expanded pixels according to the invention.

Embodiments of the invention will be described in detail with reference to the accompanying drawings.

[Embodiment 1]

FIG. 1 is a block diagram of the construction of the first embodiment of the image display apparatus according to the invention. Referring to FIG. 1, there are shown a PC signal input terminal 101 to which a signal from a PC is supplied, an EDTV signal input terminal 102 to which an EDTV signal is fed, and a signal change-over circuit 103 for switching between the input image signals and producing a selected signal. The output terminal of the signal change-over circuit 103 is connected to the input terminals of pixel conversion circuits 104, 105 and an input signal discrimination circuit 106. The first pixel conversion circuit 104 and the second pixel conversion circuit 105 constitute a pixel conversion circuitry for converting the number of pixels of the input image signals. The first pixel conversion circuit 104 carries out the pixel conversion in the first conversion mode in which mode a pixel having the same image information (luminance, chromaticity) as that of a certain pixel is inserted as an interpolation pixel so as to be adjacent to the pixel of interest as shown in FIG. 3A. The second pixel conversion circuit 105 carries out the pixel conversion in the second conversion mode in which mode the average of the image information of two adjacent pixels is inserted as an interpolation pixel so as to be between the two adjacent pixels as shown in FIG. 3B. The input signal discrimination circuit 106 identifies the type of the input image signal from the horizontal synchronizing frequency and vertical synchronizing frequency of the input image signal, and sets the magnification factors in the first and second pixel conversion circuits 104, 105. The output terminal from which the input signal discrimination circuit 106 produces the signals for setting the magnification factors is connected to the control terminals of the first and second pixel conversion circuits 104, 105.

The output terminals of the first and second pixel conversion circuits 104, 105 are connected to the two input terminals of another signal change-over circuit 108, respectively. The signal change-over circuit 108 switches between the input signals and produces a selected one. The control terminals of the signal change-over circuits 103, 108 and input signal discrimination circuit 106 are connected to a PC/TV switching signal input terminal 107, to which a PC/TV switching signal is supplied from an operation unit (not shown) which the user operates to select the signal type. The signal change-over circuits 103, 108 selects the PC signal or TV signal in accordance with the PC/TV switching signal, and the input signal discrimination circuit 106 sets the magnification factors of the first and second pixel conversion circuits 104, 105 on the basis of the PC/TV switching signal.

The output terminal of the signal change-over circuit 108 is connected to the input terminal of a display unit 109 which has a TFT liquid crystal panel of, for example, 1024.times.768 pixels corresponding to XGA mode. The display unit 109 has more pixels than does the NTSC-system equivalent, and thus it is able to display with high quality. In addition, a plasma display panel may used. Also, the display may have 800.times.600 pixels corresponding to SVGA mode.

The operation of this embodiment will be described below.

The PC signal and EDTV signal input, respectively, from the PC signal input terminal 101 and EDTV signal input terminal 102 are fed to the signal change-over circuit 103, and the signal change-over circuit 103 selects one of the input signals in accordance with the PC/TV switching signal which the user inputted and which is fed from the PC/TV switching signal input terminal 107.

The signal produced from the signal change-over circuit 103 is supplied to the first and second pixel conversion circuits 104, 105, and to the input signal discrimination circuit 106, respectively. The input signal discrimination circuit 106 identifies the type of the input signal according to the horizontal synchronizing frequency and vertical synchronizing frequency of the input signal. The pixel conversion circuits 104, 105 make pixel conversion (magnifies the pixels) of a selected image signal according to the set conversion system in order to fit the number of pixels of the display unit 9 on the basis of the result from the input signal discrimination circuit 106.

When a signal having, for example, 640.times.480 pixels corresponding to VGA mode (about 31.5 kHz in its horizontal synchronizing frequency, and about 60 Hz in its vertical synchronizing frequency) is applied to the PC signal input terminal 101 in this embodiment shown in FIG. 1, the input signal discrimination circuit 106 recognizes the input image signal as a signal corresponding to VGA from the horizontal and vertical synchronizing frequencies. In addition, the input signal discrimination circuit 106 supplies the control signal for setting the conversion coefficients (magnification factors) to the first and second pixel conversion circuits 104, 105. This control signal causes the conversion coefficients of the first and second pixel conversion circuits 104, 105 to change to the coefficients by which the input image signal can be expanded by 1.5 times in the horizontal and vertical directions as shown in FIG. 4. The first and second pixel conversion circuits 104, 105 convert the input PC signal corresponding to VGA into 960.times.720 pixels by using the set conversion coefficients. The signal change-over circuit 108 selects the output signal from the first pixel conversion circuit 104 which makes pixel conversion in the first conversion mode shown in FIG. 3A, and supplies it to the display unit 109 in accordance with the PC/TV switching signal fed from the PC/TV switching signal input terminal 107.

Similarly, if the EDTV signal (of about 31.5 kHz in its horizontal synchronizing frequency and about 60 Hz in its vertical synchronizing frequency) is applied to the EDTV input terminal 102 in this embodiment shown in FIG. 1, the input signal discrimination circuit 106 recognizes the input image signal as the signal corresponding to VGA from the horizontal and vertical synchronizing frequencies. In addition, the input signal discrimination circuit 106 supplies the control signal for setting the conversion coefficients (magnification coefficients) to the first and second pixel conversion circuits 104, 105. This control signal makes the first and second pixel conversion circuits 104, 105 be set at the conversion coefficients for magnifying the input image signal by 1.5 times in the horizontal and vertical directions as shown in FIG. 4. The first and second pixel conversion circuits 104, 105 convert the input PC signal corresponding to VGA into 960.times.720 pixels by using the set conversion coefficients. The signal change-over circuit 108 selects the output signal from the second pixel conversion circuit 105 for making pixel conversion in the second conversion mode shown in FIG. 3B, and supplies it to the display unit 109 in accordance with the PC/TV switching signal from the PC/TV switching signal input terminal 107,

While in this embodiment the first and second pixel conversion circuits 104, 105 are separately provided, and switched by the following signal change-over circuit 108, a single pixel conversion circuit may be provided in place of the separate ones, so that the conversion coefficients (magnification factors) can be switched in one conversion circuit, thereby achieving such conversion system as shown in FIGS. 3A and 3B.

[Embodiment 2]

FIG. 2 is a block diagram of the construction of the second embodiment of an image display apparatus according to the invention. In FIG. 2, like elements corresponding to those of the first embodiment shown in FIG. 1 are identified by the same reference numerals, and will not be described.

In this embodiment, the EDTV signal input terminal 102 in the first embodiment is replaced by an input terminal 202 for an NTSC signal (an interlaced signal having a horizontal synchronizing frequency of about 15.75 kHz and a frame frequency of 30 Hz), and an NTSC-VGA signal conversion circuit 201 for converting the NTSC signal into a VGA signal. The NTSC signal input terminal 202 is connected to the input terminal of the NTSC-VGA signal conversion circuit 201. The output terminal of the NTSC-VGA signal conversion circuit 201 is connected to one input terminal of the signal change-over circuit 103.

The NTSC-VGA signal conversion circuit 201 converts the input NTSC signal into a non-interlaced signal which corresponds to a VGA signal and which has a horizontal synchronizing frequency of about 31.5 kHz and a vertical synchronizing frequency of 60 Hz. Thus, the input signal discrimination circuit 106 recognizes this converted signal as a signal corresponding to VGA, and supplies the control signal to the first and second pixel conversion circuits 104, 105 as a signal for setting the conversion coefficients to magnify the input signal by 1.5 times in the horizontal and vertical directions. As a result, the magnification factors of the first and second pixel conversion circuits 104, 105 are set to be 1.5 times, and the pixel conversion can be performed on the basis of this magnification factor. Then, when the signal change-over circuit 108 selects the input PC signal in accordance with the PC/TV switching signal, the output signal from the first pixel conversion circuit 104 for making the pixel conversion in the first conversion mode shown in FIG. 3A is supplied to the display unit 109. When it selects the input NTSC signal, the output signal from the second pixel conversion circuit 105 for making the pixel conversion in the second conversion mode shown in FIG. 3B is transmitted to the display unit 109.

In this embodiment, since the NTSC signal is converted into the non-interlaced signal which has the horizontal and vertical synchronizing frequencies corresponding to a VGA signal, there is no need to provide a plurality of conversion coefficients such as the conversion coefficients for NTSC signal and VGA signal in the first and second pixel conversion circuits 104, 105. Therefore, the first and second pixel conversion circuits 104, 105 can be simplified in their constructions.

This embodiment may be modified so that the conversion coefficients (magnification factors) are switched within one pixel conversion circuit, realizing the conversion systems shown in FIGS. 3A and 3B.

Thus, according to the present invention, even when a plurality of signals of different types are recognized as the same signal type or format by the input signal discrimination circuit, and converted in their pixels by the same conversion coefficient (magnification factor), they can be converted by the optimum conversion system suitable for each of the PC signal and TV signal so that high-quality pictures can be obtained.