Current Output Type Digital-to-Analog Converter Capable of Suppressing Output Current Fluctuation Using a Current Mirror

1. Field of the Invention

The present invention relates to a digital-to-analog (D/A) converter, and more particularly, to the improvement of the fluctuation of an output current of a current output type D/A converter.

2. Description of the Related Art

A current output type D/A converter has the following advantages:

output impedance can be reduced;

high speed operation is possible;

high precision resistors are unnecessary;

the converter is easily incorporated into an integrated circuit (IC); and

a high speed clock signal is unnecessary.

A prior art D/A converter of this kind (see JP-A-61-95623) is constructed by a logic circuit, a reference current source, and a digital-to-analog conversion section connected between the logic circuit and the reference current source. In this case, bipolar transistors of the digital-to-analog conversion section form current mirror circuits with a bipolar transistor of the reference current source. This will be explained later in detail.

In the above-mentioned prior art D/A converter, however, a resistance by switching means is introduced into each of the current mirror circuits, so that the output current is fluctuated. On the other hand, in order to minimize the above mentioned resistances and the fluctuation thereof, transistors used as the switching means can be large in size, which, however, decreases the integration.

It is an object of the present invention to provide a current output type D/A converter capable of suppressing the fluctuation of an output current.

According to the present invention, in a D/A converter, a logic circuit includes a plurality of MOS transistors each having a gate connected to one of input signal lines, a drain connected to a first power supply terminal and a source which has one of a connection state where the source is connected to one of output signal lines and a disconnection state where the source is not connected to the output signal lines. A reference current source includes a constant current source and a first transistor connected in series. A digital-to-analog conversion section includes a plurality of second transistors each connected to one of the output signal lines and to the first transistor. Each of the second transistors forming a current mirror circuit with the first transistor. The digital-to-analog conversion section also includes a plurality of third transistors each connected between an output terminal and one of the output signal lines.

Thus, there is no substantial resistance between the first transistor and the second transistors within the current mirror circuits.

The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram illustrating a prior art D/A converter;

FIG. 2 is a table showing the input/output relationship of the logic circuit of FIG. 1;

FIG. 3 is a circuit diagram illustrating a first embodiment of the D/A converter according to the present invention;

FIG. 4 is a circuit diagram illustrating a second embodiment of the D/A converter according to the present invention; and

FIG. 5 is a circuit diagram illustrating a modification of the D/A converter of FIG. 3.

Before the description of the preferred embodiments, a prior art D/A converter will be explained with reference to FIG. 1 (see JP-A-61-95623).

In FIG. 1, reference numeral 100 designates a logic circuit for converting a 3-bit Gray code signal formed by bits S.sub.0, S.sub.1 and S.sub.2 into a 3-bit binary code signal formed by D.sub.0, D.sub.1 and D.sub.2 which has a relationship with the 3-bit Gray code signal (S.sub.2, S.sub.1, S.sub.0) as shown in FIG. 2. The logic circuit 100 is constructed by seven three-input gate circuits 111, 112, . . . , 117 connected to input terminals IN.sub.0, IN.sub.1 and IN.sub.2 for receiving the Gray code signal (S.sub.2, S.sub.1, S.sub.0), and three OR circuit 120, 121 and 122 each connected to four of the gate circuits 111, 112, . . . , 117. That is, the logic circuit 100 serves as a decoder for decoding the Gray code signal (S.sub.2, S.sub.1, S.sub.0) to generate the binary code signal (D.sub.2, D.sub.1, D.sub.0).

Also, a reference current source 200 is constructed by a constant current source 201, a collector-base connected NPN type bipolar transistor 202 and a resistor 203. In this case, the mutual conductance of the bipolar transistor 202 is defined by g.sub.m, and a current I.sub.0 flows therethrough.

Further, a digital-to-analog conversion section 300 receives the binary code signal (D.sub.2, D.sub.1, D.sub.0) to generate an output current I.sub.out at an output terminal OUT in accordance with the binary code signal (D.sub.2, D.sub.1, D.sub.0). The digital-to-analog conversion section 300 is powered by the reference current source 200.

The digital-to-analog converter 300 is constructed by an NPN type bipolar transistor 310 and a resistor 320 connected in series between the output terminal OUT and a ground terminal GND, an NPN type bipolar transistor 311 and a resistor 321 connected in series between the output terminal OUT and the ground terminal GND, and an NPN type bipolar transistor 312 and a resistor 322 connected in series between the output terminal OUT and the ground terminal GND. Also, N-channel MOS transistors 330, 331 and 332 are connected between the reference current source 200 and the bases of the bipolar transistors 310, 311 and 312, and are controlled by the binary code bits D.sub.0, D.sub.1 and D.sub.2, respectively. Further, N-channel MOS transistors 340, 341 and 342 are connected between the ground terminal GND and the bases of the bipolar transistors 310, 311 and 312, and are controlled by the inverted signals of the binary code bits D.sub.0, D.sub.1 and D.sub.2, respectively.

The emitter areas of the bipolar transistors 310, 311 and 312 are determined so that the mutual conductances of the bipolar transistors 310, 311 and 312 are caused to be g.sub.m, 2g.sub.m and 4(=2.sup.2)g.sub.m, respectively.

When the bit D.sub.0 of the binary code signal of the logic circuit 100 is high, the transistors 330 and 340 are turned ON and OFF, respectively, so that the transistors 202 and 310 form a current mirror circuit. In this case, since the mutual conductance of the transistor 310 is the same as that the transistor 202, a current I.sub.0 flows through the transistor 310. On the other hand, when the bit D.sub.0 of the binary code signal of the logic circuit 100 is low, the transistors 330 and 340 are turned OFF and ON, respectively, so that the transistor 310 is turned OFF.

Also, when the bit D.sub.1 of the binary code signal of the logic circuit 100 is high, the transistors 331 and 341 are turned ON and OFF, respectively, so that the transistors 202 and 311 form a current mirror circuit. In this case, since the mutual conductance of the transistor 311 is twice that of the transistor 202, a current 2I.sub.0 flows through the transistor 311. On the other hand, when the bit D.sub.1 of the binary code signal of the logic circuit 100 is low, the transistors 331 and 341 are turned OFF and ON, respectively, so that the transistor 311 is turned OFF.

Further, when the bit D.sub.2 of the binary code signal of the logic circuit 100 is high, the transistors 332 and 342 are turned ON and OFF, respectively, so that the transistors 202 and 312 form a current mirror circuit. In this case, since the mutual conductance of the transistor 312 is four times that the transistor 202, a current 4I.sub.0 (=2.sup.2 I.sub.0) flows through the transistor 312. On the other hand, when the bit D.sub.2 of the binary code signal of the logic circuit 100 is low, the transistors 332 and 342 are turned OFF and ON, respectively, so that the transistor 312 is turned OFF.

In FIG. 1, however, in each of the current mirror circuits, if a resistance between the bases of the two transistor 202 and 310 (311, 312) is large, the output currents I.sub.0, 2I.sub.0 and 4I.sub.0 include error components. Also, if such resistances are different from each other, the output currents I.sub.0, 2I.sub.0 and 4I.sub.0 also include error components. Therefore, in order to minimize the above-mentioned resistances and the fluctuation thereof, the transistors 330, 331 and 332 have to be large in size, which decreases the integration.

Also, in FIG. 1, when the number of bits of the input signal is increased, the number of elements of logic circuit 100 is remarkably increased, which also decreases the integration.

In FIG. 3, which illustrates a first embodiment of the present invention, a logic circuit 1 is connected to signal lines L.sub.x.spsb.0, L.sub.x.spsb.1 and L.sub.x.spsb.2 connected to input terminals IN.sub.0, IN.sub.1 and IN.sub.2, respectively, and signal lines L.sub.y.spsb.0, L.sub.y.spsb.1, . . . , L.sub.y.spsb.5, and is constructed by MOS transistors Q.sub.00, Q.sub.01, . . . , Q.sub.05, Q.sub.10, Q.sub.11, . . . , Q.sub.15, Q.sub.20, Q.sub.21, . . . , Q.sub.25 located at intersections of the signals L.sub.x.spsb.0, L.sub.x.spsb.1 and L.sub.x.spsb.2 and L.sub.y.spsb.0, L.sub.y.spsb.1, . . . , L.sub.y.spsb.5. In this case, the gates of the transistors Q.sub.00, Q.sub.01, . . . , Q.sub.05 are connected to the signal line L.sub.x.spsb.0, the gates of the transistors Q.sub.10, Q.sub.11, . . . , Q.sub.15 are connected to the signal line L.sub.x.spsb.1, and the transistors Q.sub.20, Q.sub.21, . . . , Q.sub.25 are connected to the signal line L.sub.x.spsb.2. Also, the drains of the transistors Q.sub.00, Q.sub.10, Q.sub.20, Q.sub.10, Q.sub.11, . . . , Q.sub.15, Q.sub.20 Q.sub.21, . . . , Q.sub.25 are connected to a power supply whose voltage is V.sub.1. On the other hand, some of the sources of the transistors are connected to the corresponding signal line L.sub.y.spsb.0, L.sub.y.spsb.1, . . . , L.sub.y.spsb.5, while the other are not connected to the signal lines L.sub.y.spsb.0, L.sub.y.spsb.1, . . . , L.sub.y.spsb.5. Thus, the transistors Q.sub.01, Q.sub.02, . . . , Q.sub.25 form a (3 rows, 6 columns) matrix similar to a memory cell array of a read-only memory.

Also, a reference current source 2 having the same configuration as the reference current source 200 is provided.

Further, a digital-to-analog conversion section 3 is constructed by an NPN type bipolar transistor 350 and a resistor 360 connected in series between the signal line L.sub.y.spsb.0 and the ground terminal GND, an NPN type bipolar transistor 351 and a resistor 361 connected in series between the signal line L.sub.y.spsb.1 and the ground terminal GND, an NPN type bipolar transistor 352 and a resistor 362 connected in series between the signal line L.sub.y.spsb.2 and the ground terminal GND, an NPN type bipolar transistor 353 and a resistor 363 connected in series between the signal line L.sub.y.spsb.3 and the ground terminal GND, an NPN type bipolar transistor 354 and a resistor 364 connected in series between the signal line L.sub.y.spsb.4 and the ground terminal GND, and an NPN type bipolar transistor 355 and a resistor 365 connected in series between the signal line L.sub.y.spsb.5 and the ground terminal GND. The emitter areas of the bipolar transistors 350, 351, 352, 353, 354 and 355 are determined so that the mutual conductances of the bipolar transistor 350, 351, 352, 353, 354 and 355 are caused to be g.sub.m, 2g.sub.m, 4(=2.sup.2)g.sub.m, 8(=2.sup.3)g.sub.m, 16(=2.sup.4)g.sub.m and 32(=2.sup.5)g.sub.m, respectively. In this case, the bases of the transistors 350, 351, . . . , 355 are connected to the base and collector of the transistor 202 of the reference current source 2. Therefore, if the transistors 350, 351, 352, 353, 354 and 355 are active, the transistor 350, 351, 352, 353, 354 and 355 with the transistor 202 form current mirror circuits, so that currents I.sub.0, 2I.sub.0, 4(=2.sup.2)I.sub.0, 8(=2.sup.3)I.sub.0, 16(=2.sup.4)I.sub.0 and 32(-2.sup.5)I.sub.0 flow through the transistors 350, 351, 352, 353, 354 and 355, respectively.

The digital-to-analog conversion section 300 is also constructed by NPN type bipolar transistor 370, 371, 372, 373, 374 and 375 connected between an output terminal OUT and the signal lines L.sub.y.spsb.0, L.sub.y.spsb.1, L.sub.y.spsb.2, L.sub.y.spsb.3 L.sub.y.spsb.4 and L.sub.y.spsb.5. The bases of the transistors 370, 371, 372, 373, 374 and 375 are connected to a power supply whose voltage is V.sub.2.

The operation of the D/A converter of FIG. 3 is explained next.

When the input signals S.sub.0, S.sub.1 and S.sub.2 are high, low and low, respectively, the gate voltages of the transistors Q.sub.00, Q.sub.01, . . . , Q.sub.05 are high. In this case, if the base-to-emitter voltages of the transistors 370, 371, . . . , 375 are defined by V.sub.BE.spsb.0, V.sub.BE.spsb.1, . . . , V.sub.BE.spsb.5, respectively.

where V.sub.th is a threshold voltage of the MOS transistors. As a result, the transistors 370, 373 and 374 are turned OFF. On the other hand, since the transistors Q.sub.01, Q.sub.02 and Q.sub.05 are not connected to the signals lines, irrespective of the voltage of the input signal S.sub.0,

Therefore, the transistors 371, 372 and 375 are turned ON. Thus, ##EQU1##

Next, when the input signals S.sub.0, S.sub.1 and S.sub.2 are low, high and low, respectively, the gate voltages of the transistors Q.sub.10, Q.sub.11, . . . , Q.sub.15 are high. In this case,

As a result, the transistors 370, 372, 374 and 375 are turned OFF. On the other hand, since the transistors Q.sub.11 and Q.sub.13 are not connected to the signal lines, irrespective of the voltage of the input signal S.sub.1,

Therefore, the transistors 371 and 373 are turned ON. Thus, ##EQU2##

Next, when the input signals S.sub.0, S.sub.1 and S.sub.2 are low, low and high, respectively, the gate voltages of the transistors Q.sub.20, Q.sub.21, . . . , Q.sub.25 are high. In this case,

As a result, the transistors 370, 373 and 375 are turned OFF. On the other hand, since the transistors Q.sub.21, Q.sub.22 and Q.sub.24 are not connected to the signals lines, irrespective of the voltage of the input signal S.sub.2,

Therefore, the transistors 371, 372 and 374 are turned ON. Thus, ##EQU3##

In addition, two of the input signals S.sub.0, S.sub.1 and S.sub.2 can be high, and all of the input signals S.sub.0, S.sub.1 and S.sub.2 can be high. In the latter case, the gate voltages of all the transistors Q.sub.00, Q.sub.01, . . . , Q.sub.25 are high. In this case,

As a result, the transistors 370, 372, 373, 374 and 375 are turned OFF. On the other hand, since the transistors Q.sub.01, Q.sub.11 and Q.sub.21 are not connected to the signals lines, irrespective of the voltage of the input signals S.sub.0, S.sub.1 and S.sub.2,

Therefore, only the transistor 371 is turned ON.

Thus,

In FIG. 3, since the base of the transistor 202 of the reference current source 2 is connected directly to the bases of the transistors 350, 351, . . . , 355 of the digital-to-analog conversion section 3 without switching means, and the switching of the transistors 350, 351, . . . , 355 is carried out by the logic circuit 1, the fluctuation of the currents flowing through the transistors 350, 351, . . . , 355, i.e., the fluctuation of the output current I.sub.out can be suppressed. Also, the logic of the digital-to-analog conversion section 1 is preset by providing the presence or absence of contact throughholes between the sources of the transistors Q.sub.00, Q.sub.01, . . . Q.sub.25 and the signal lines L.sub.y.spsb.0, L.sub.y.spsb.1, . . . , L.sub.y.spsb.5, thus easily changing the logic of the D/A converter.

In FIG. 4, which illustrates a second embodiment of the present invention, the NPN type transistors 370, 371, . . . , 375 of FIG. 3 are replaced by a multi-emitter type NPN bipolar transistor 37 which has six emitters. In this case, the operation of the D/A converter of FIG. 4 is the same as that of the D/A converter of FIG. 3.

In FIG. 5, which is a modification of the D/A converter of FIG. 3, the bipolar transistors 202, 350, 351, . . . , 355, 370, 371, . . . , 375 of FIG. 3 are replaced by N-channel type MOS transistors 202', 350', 351', . . . , 355', 370', 371', . . . , 375', respectively. Even in this case, the operation of the D/A converter of FIG. 5 is similar to that of the D/A converter of FIG. 5.

As explained hereinabove, according to the present invention, the fluctuation of the output current can be suppressed.