Communication Control System and Apparatus

1. Field of the Invention

The present invention relates to a communication control system and apparatus for performing communication via a clock signal line and a data signal line.

2. Related Background Art

In recent years, the number of output/drive devices such as a display device, a stepping motor, an electromagnetic clutch, and a solenoid or input/sensor devices such as an operation switch, a photointerruptor, and a mechanical binary switch has tended to increase to improve the performance of an image forming apparatus such as a copying machine. Accordingly, the number of signal lines for transmitting control signals in such systems has increased. This results in serious problems including an increase in size and weight of bundled signal lines, degradation in assembly/decomposition properties and reliability, and an increase in cost.

To solve these problems, a serial communication system is proposed in which communication substations each addressed to a unique address are arranged at various points in the system. At least one serial data line and one serial communication synchronous clock line are extracted from a main controller for controlling the entire system. The communication substations are sequentially cascade-connected to perform serial data transmission/reception between a desired communication substation and the main controller.

Such a conventional serial communication system will be described with reference to FIG. 7, which is a block diagram showing the arrangement of the conventional serial communication system. Referring to FIG. 7, a main controller 1 controls the entire image forming apparatus. A host microcomputer (to be referred to as a host hereinafter) 2 serves as the control center of the main controller 1. A serial controller 3 is coupled to the host 2 via buses and serves as a master controller for serial communication. Communication substations (relay substations) 4 and 5 are set at various points in the system. Serial communication substation ICs 6 and 7 are mounted in the communication substations 4 and 5, respectively.

In this example, one serial communication substation IC 6 is an input IC exclusively used for reception, i.e., the input IC fetches binary data from various input devices such as a photointerruptor (sensor) and transfers the data to the serial controller 3 of the host 2. The other serial communication substation IC 7 is an output IC exclusively used to output data, i.e., the output IC receives data from the serial controller 3 of the host 2 and outputs the binary data to various drive devices such as a clutch. In this example, one serial communication substation IC 6 is addressed to address 0, and the other serial communication station IC 7 is addressed to address 1. Each 8-bit packet of communication data is made to correspond to an input port or an output port.

This system also includes a +5V power supply 8 for logic circuits, a data line (DATA) 9 for serial communication, a synchronous clock line (CLK) 10, a ground line (GND) 11, a +24V power supply 12 for drive devices, and a ground line (GND) 13. The main controller 1 and the communication substations 4 and 5 are cascade-connected via these lines. Particularly, in the system of this example, the data line 9 and the synchronous clock line 10 directly cascade-connect the serial controller 3 of the host 2 to the serial communication substation ICs 6 and 7 of the communication substations 4 and 5, and the serial communication substation IC at the intermediate position transmits the output from the preceding stage to the next stage via an internal buffer in real time, as shown in FIG. 7.

The operation of the serial communication system having the above arrangement will be described next with reference to a communication format shown in FIG. 8. To acquire the value of the photointerruptor connected to bit 0 of address 0, the host 2 issues a predetermined command to the serial controller 3 via an address bus (detailed description of the actual form of the command will be omitted). In response to the command, the serial controller 3 generates a desired number of synchronous clocks and transmits the synchronous clocks to the synchronous clock line 10. The serial controller 3 also executes the following serial data transmission/reception operation on the data line 9. Each substation fetches data at the rising of the synchronous clock. Upon detecting data of "L" (low) together with the clock during waiting for communication, the substation recognizes the start of a communication frame.

At the first clock, a start bit of "L" for declaring the start of a communication frame is output. In this example, the logical level in the noncommunication state of the data line 9 is "H" (high). At the next clock, an R/W bit for defining a mode requested by the serial controller 3 for this frame, i.e., a data input mode or a data output mode, is transferred. In this example, when this bit is at "H", a read mode wherein the serial controller 3 receives data from the substation is set. When this bit is at "L", a write mode wherein the serial controller 3 outputs data is defined. Since the input IC is set at address 0, the serial controller 3 sets this bit at "H", as a matter of course.

In synchronism with the next four clocks, address 0 indicating the desired communication substation is serially transferred. All substations monitor the transferred data, and substation 0 whose self address coincides with the desired communication station address on the serial data is involved in subsequent communication. Substations having addresses different from the desired communication station address buffer the clocks and transmit them to the subsequent stages (in the direction away from the serial controller 3). In the read mode, the data line 9 buffers data from the subsequent stages and transmits it to the preceding stages. In the write mode, the data line 9 buffers data from the preceding stages and transmits it to the subsequent stages. Address 0, i.e., the designated station neglects (releases) data from the subsequent stage and serially transmits 8-bit data from the self input port in synchronism with the next eight clocks. The serial controller 3 receives the 8-bit serial data and recognizes the desired photointerruptor data at bit 0.

Almost the same procedure can be used when the host 2 drives a clutch connected to bit 0 of the output IC at address 1. The host 2 writes address 1 and issues the data and the data request command to the serial controller 3 via a bus (when data other than data at bit 0 of address 1 need not be changed, the same data as in the previous processing must be written in fact, and these data are transmitted to the serial controller 3).

The serial controller 3 transmits the necessary number of synchronous clocks to the clock line 10, as in the above processing. The serial controller 3 sequentially transmits a start bit, a write mode bit, address 1 as the 4-bit target address, and 8-bit write data. Only a substation at address 1 designated by the address bits fetches the 8-bit data on the data line 9 and outputs the data to the output port at the end of communication. In the read mode, data up to address bit A3 is output from the serial controller 3, and data bits D0 to D7 are output from the substation IC 6 or 7 to the serial controller 3. The serial controller 3 outputs clocks corresponding to one frame. The substation IC 6 or 7 outputs data bits D0 to D7 in synchronism with these clocks.

In serial communication following the above procedure, data of a plurality of bits can be transmitted/received to/from the communication substations arranged at various points in the system, so the number of signal lines for transmitting control information can be substantially reduced.

In the above-described prior art, however, the substation ICs only execute, as frame synchronization for serial data transmission/reception, simple sequence processing using synchronous clocks with reference to the start bit because of restrictions on cost whereby synchronization is maintained. Neither a variety of determination processing operations using a timer or a microcomputer for measuring frame time nor frame synchronization using a frame synchronous line different from the serial line is performed.

As shown in FIG. 9, when two noise components are mixed into the clock line in the transmission mode, and sequence processing of the substation advances by two steps from the original clock cycle, the frame ends before the end of the normal clock cycle in the substation. If transmission data bit D6 synchronizing with a subsequent normal clock is at "L" unexpectedly, the substation erroneously recognizes the bit data as the start of a new communication frame. Sequence processing progresses in synchronism with the remaining clocks, and even when the normal clock cycle is ended, processing continues to wait for next synchronous clocks to perform remaining sequence processing. When synchronous clocks of a new normal frame are generated, the remaining sequence processing starts, so the substation continues data reception in erroneous frame units.

As shown in FIG. 10, when six noise components are mixed, and accidentally, data bit D2 is at "L", data bit D3 is at "H", data bits D4 to D6 are at "L", and data bit D7 is at "H", the substation at address 1 is to output the data to the serial data line. Assume that the first data bit is at "L", and the serial controller 3 outputs data of level "H" to the serial data line because the serial controller 3 considers that communication is ended (FIG. 10). In this case, a potential difference of 25 V is generated on the serial data line, and the IC may be destroyed.

It is an object of the present invention to provide a communication control system and apparatus which solve the above problems.

It is another object of the present invention to provide a communication control system and apparatus capable of canceling erroneous recognition of the start of data in a second communication apparatus, which occurs when noise or the like is mixed into a clock signal line.

Other objects and features of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings.

FIG. 1 is a flow chart showing the operation of a serial communication system according to the first embodiment of the present invention;

FIG. 2 is a flow chart showing the operation of the serial communication system according to the first embodiment;

FIG. 3 is a block diagram showing the arrangement of a serial communication system according to the second embodiment of the present invention;

FIG. 4 is a flow chart showing the operation of the serial communication system according to the second embodiment;

FIG. 5 is a flow chart showing the operation of the serial communication system according to the second embodiment;

FIG. 6 is a view showing a dummy clock in the embodiments of the present invention;

FIG. 7 is a block diagram showing the arrangement of a conventional serial communication system;

FIG. 8 is a view showing a format in the convent ional serial communication system ;

FIG. 9 is a view showing a frame shift in the conventional serial communication system;

FIG. 10 is a view showing a frame shift in the conventional serial communication system; and

FIG. 11 is a block diagram showing the arrangement of the conventional serial communication system.

(First Embodiment)

The first embodiment of the present invention will be described below with reference to FIGS. 1 and 2. The basic arrangement of the serial communication system of this embodiment is the same as that of the conventional system shown in FIGS. 7 and 8, and a detailed description of the common part will be omitted.

FIGS. 1 and 2 are flow charts showing the operation of the serial communication system according to the first embodiment of the present invention. A host 2 in a main controller 1 loads a control program stored in a storage means to execute these processing operations.

Referring to FIG. 1, initialization is performed in step S101. In step S102, main body sequence control for the system is performed. Serial data transmission processing (step S103) and serial data reception processing (step S104) are performed. A procedure of the host 2 which occasionally reads/writes data from/in each substation in the system as needed while performing sequence control of the entire system is the same as in the above-described prior art.

The first embodiment is different from the prior art in that a dummy clock generation processing routine is executed every predetermined time by timer interruption processing shown in FIG. 2 independently of the main routine of the host 2 shown in FIG. 1. This routine is executed independently of detection of a communication error.

In FIG. 2, it is determined in step S201 whether data transmission or reception on the serial communication line is being performed, and this determination is made until data transmission or reception is ended. When data transmission or reception is ended, a dummy clock transmission command is issued in step S202. Accordingly, a serial controller 3 sets a data line 9 at "H" and transmits clocks in a number necessary for one normal frame. The interruption processing is ended in step S203.

More specifically, in the dummy transmission interruption processing shown in FIG. 2, while dummy clocks for one frame are being output on the data transmission line 9 a packet of, data whose start bit, R/W bit, address bits, and data bits are set at "H" is written in the serial controller 3 (as in the noncommunication state), as shown in FIG. 6, and a communication start command is issued. If a dummy clock generation command is defined in the serial controller 3, data need not be designated. If the serial communication line is already being used for data transmission/reception, processing waits until the frame is ended When the communication line becomes free, the serial controller 3 sets the data line 9 at H (noncommunication state), and transmits a number of clocks necessary for one frame. Even when a frame shift as shown in FIG. 9 has been generated in any one of substations before the dummy clock transmission operation, sequence processing of a single frame properly progresses to the final step in synchronism with the dummy clocks in the substation, as shown in FIG. 6. Even when a frame is prematurely ended halfway, an erroneous operation of starting a new frame in synchronism with the remaining clocks can be prevented because the data line 9 is set in the noncommunication state (H) (no bit of "L" representing the start). In such a case, the number of dummy clocks to be output may be greater than the number corresponding to one frame.

In the above embodiment, the host 2 issues a command for generating dummy clocks to the serial controller 3 every predetermined time. However, the present invention is not limited to this. When the serial controller 3 can be equipped with an internal timer function, the serial controller 3 may independently generate dummy clocks on the basis of time management without waiting for the command from the host 2.

(Second Embodiment)

The second embodiment of the present invention will be described next with reference to FIGS. 3 to 5. The first embodiment exemplifies a system for transmitting dummy clocks every predetermined time on the basis of time management by a timer. In the second embodiment, before transmitting data to the address of a substation connected to a high priority load (i.e., a load for which proper communication data transfer is much more critical than for other devices), dummy bits corresponding to one frame are transmitted, and then, normal communication is executed.

FIG. 3 is a block diagram showing the arrangement of a serial communication system according to the second embodiment of the present invention. The same reference numerals as in the prior art shown in FIG. 7 denote the same parts in FIG. 3. FIG. 3 is different from FIG. 7 in that the arrangement assumes an image forming apparatus using a fluorescent lamp as an exposure light source. When the ON timing of the fluorescent lamp delays due to a communication error, the leading edge of an image may be sometimes undesirably omitted, and this problem must be avoided. Referring to FIG. 3, the system includes a fluorescent lamp inverter 14 and a fluorescent lamp 15.

In FIG. 3, before transmission of an activation signal for the fluorescent lamp 15, dummy clocks corresponding to one frame as shown in FIG. 6 are unconditionally transmitted. Even if a frame shift has occurred in some portion of the communication line, error cancellation processing is temporarily performed, and then actual data is transmitted at the next frame timing. For this reason, the probability of delay due to the communication error of the ON timing of the fluorescent lamp 15 can be lowered.

The operation of the serial communication system of the second embodiment will be described next with reference to flow charts shown in FIGS. 4 and 5.

FIGS. 4 and 5 are flow charts showing the operation of the serial communication system according to the second embodiment of the present invention. A host 2 in a main controller 1 loads a control program stored in a storage means to execute these processing operations.

Referring to FIG. 4, initialization is performed in step S401. In step S402, main body sequence control for the system is performed. The fluorescent lamp 15 is turned on and the sequence of turning off the fluorescent lamp 15 is performed (step S403), and serial data transmission processing (step S404) and serial data reception processing (step S405) are performed. A procedure of the host 2 which occasionally reads/writes data from/to each substation in the system as needed while performing sequence control of the entire system is the same as in the above-described prior art.

Communication processing for turning on the fluorescent lamp 15 is independently executed in the fluorescent lamp activation subroutine shown in FIG. 5, and normal communication processing in the main routine program shown in FIG. 4 is not used.

In FIG. 5, it is determined in step S501 whether data transmission or reception on the serial communication line is being performed, and this determination is made until data transmission or reception is ended. When data transmission or reception is ended, a dummy clock transmission command is issued in step S502. Accordingly, a serial controller 3 sets a data transmission line 9 at "H" and transmits a number of clocks necessary for one normal frame. In step S503, the fluorescent lamp turning-on transmission data is set, and serial transmission processing is performed. The interruption processing is ended in step S504.

In the above embodiment, communication processing for tuning on the fluorescent lamp 15 is independently executed in the fluorescent lamp tuning-on subroutine shown in FIG. 5, and normal communication processing in the main routine program shown in FIG. 4 is not used. However, the present invention is not limited to this. Depending on the processing capability (processing time) of the main routine program, dummy clock processing may be executed, and only transmission data setting for turning on the fluorescent lamp 15 may be performed in the fluorescent lamp turning-on processing subroutine. Actual data transmission may be performed in communication processing of the main routine program.

The present invention has as its object to transmit dummy synchronous clocks in a number corresponding to one frame (or in a larger number) in a communication frame before actual data is transmitted while holding the data transmission line 9 in the noncommunication state (H). As far as the program can realize this procedure, any arrangement and technique can be used.

(Third Embodiment)

A storage medium used for the serial communication system and apparatus of the present invention will be described next.

A storage medium stores a control program for controlling a serial communication system in which a plurality of communication stations each addressed to a unique address are sequentially cascade-connected on a communication synchronous clock line and at least one serial data transmission line, and when the address of a desired communication partner is transmitted from the communication subject to the serial transmission line, a communication station coinciding with this address recognizes it and subsequently executes an operation of transmitting/receiving desired data to/from the communication subject. The storage medium also may store the program code of a "control module".

The "control module" is a program module for performing control such that a predetermined communication subject transmits communication synchronous clocks in a number necessary to transmit one communication unit (frame) or a larger number to the communication synchronous clock transmission line at a predetermined interval or a predetermined timing outside the normal data communication operation between communication stations independently of detection or nondetection of a communication error while transmitting data on the serial data transmission line at the logic level of the noncommunication state.