C-v Method to Extract Lateral Channel Doping Profiles of MOSFETs

The present invention relates to apparatus and methods for determining lateral distribution of dopants along the channel of MOS transistors in the sub-quarter micron regime. More particularly, the present invention relates to apparatus and methods for determining lateral distribution of dopants along the channel of MOS transistors in the sub-quarter micron regime using gate-to-substrate capacitance behavior. Even more particularly, the present invention relates to apparatus and methods for determining lateral distribution of dopants along the channel of MOS transistors in the sub-quarter micron regime using information relating to voltage bias dependence of gate-to-substrate capacitance C.sub.gb.

As MOS transistors are scaled to the sub-quarter micron regime, the lateral distribution of dopants along the channel becomes a critical factor affecting their operation and performance. A technique that allows one to obtain the lateral doping profile is therefore indispensable. Vertical profiling techniques such as the C-V and SIMS have widely been used. The vertical C-V methods assumes a uniform lateral doping of channel and substrate regions, while the SIMS method is not feasible for submicron channel lengths. Lateral techniques for small size transistors, however, have met with less success. N. Khalil et al. in IEEE EDL-16(1), G. J. L. Ouwerling in Solid State Electronics., vol 34, p. 197, 1991 and Lee et al. in IEDM'97 Proceedings teach inverse modeling approach techniques by finding a lateral doping profile using an iterative procedure. Basically, these approaches determine whether the C-V/I-V characteristics of an assumed lateral doping profile matches the measured C-V/I-V characteristics of a device under test. However, none of these approaches teach, suggest, nor motivate how to accurately extract lateral doping profile directly from the measured data of the device under test.

Accordingly a need is seen to exist for a method for determining the non-uniform lateral surface doping for sub-micron CMOS devices directly from C-V measurements of the device, which is simple, nondestructive and accurate.

It is therefore a primary object of the present invention to provide a method and system for determining the non-uniform lateral surface doping for sub-micron CMOS devices directly from C-V measurements of the device. Even more particularly, the present invention relates to apparatus and methods for determining lateral distribution of dopants along the channel of MOS transistors in the sub-quarter micron regime using bias dependence of gate-to-substrate capacitance C.sub.gb in accumulation to obtain channel doping concentration and its variations along the channel.

Accordingly, the foregoing objects are accomplished by taking advantage of a relationship that exists in short channel (sub-quarter micron) semiconductor devices, namely that the gate length is proportional to the gate-to-substrate capacitance C.sub.gb. In general, C.sub.gb data of a short channel device contains the lateral source/drain substrate junction depletion width variation information at different source/drain substrate bias voltages. The above capacitance and length relationship means that shifts in C.sub.gb vs. source/drain substrate voltage (V.sub.sb /V.sub.db) can translate directly into the variations of the substrate junction depletion width (W) vs. V.sub.sb /V.sub.db. Consequently, information about the channel doping profile is contained in the C.sub.gb vs. V behavior. In accordance with the method of the present invention, the extraction of the channel doping profile starts with setting up a reference for length calculations by employing a large gate capacitor (e.g. 100.times.100 .mu.m) to get the capacitance per unit area in accumulation regime. Then, the C.sub.gb of the sub-micron device being tested is measured at different drain/source bias voltages. Then, these C.sub.gb values are compared with the unit area C.sub.gb of the large area capacitor. The depletion width W at a given bias voltage is determined from comparing the sub-micron devices C.sub.gb values with the unit area C.sub.gb reference value measurement of a large capacitor. After that, C.sub.gb -V.sub.db slope is extracted and used to calculate the channel doping using depletion relation: ##EQU1## derived from equations (18c) and (18d) on page 81 of "The Physics of Semiconductor Devices" 1981 by S. M. Sze, where N.sub.ch is channel doping concentration, .epsilon..sub.s the silicon dielectric permitivity and q the electron charge.

Other features of the present invention are disclosed or apparent in the section entitled: "BEST MODE FOR CARRYING OUT THE INVENTION.

For fuller understanding of the present invention, reference is made to the accompanying drawing in the following detailed description of the Best Mode of Carrying Out the Present Invention. In the drawing:

FIG. 1 is a schematic illustration of the apparatus used in the practice of the invention.

FIGS. 2a, 2b, and 2c are schematic illustrations of a MOS transistor which is tested in the device illustrated in FIG. 1 using a first method.

FIGS. 3a, 3b, and 3c are schematic illustrations of a MOS transistor which is tested in the device illustrated in FIG. 1 using a second method.

FIG. 4 is a graph of a typical MOS gate to substrate capacitance plotted against the voltage between the drain and the substrate of the MOS gate.

FIG. 5 is a graph of the doping profile obtained through the practice of the invention of a typical MOS gate without halo implantation.

FIG. 6 is a graph of the doping profile obtained through the practice of the invention of a typical MOS gate with halo implantation.

FIG. 7 is a graph of the extracted quasi-neutral channel length reduction of the drain junction depletion extension for MOSFET with and without halo doping.

Reference numbers refer to the same or equivalent parts of the present invention throughout the several figures of the drawing.

Conventional 0.18 .mu.m MOSFETs are employed in this work. Here, devices with halo and non-halo implantation are chosen to illustrate the application of the proposed method. Devices with halo implantation are created by implanting extra dopants into the channel with a tilted angle after the gate formation.

FIG. 1 depicts a MOS transistor 10 attached to a testing device 11 used to practice the invention. The MOS transistor 10 comprises a gate 14, a source 15, and a drain 16 mounted on a substrate 17. The gate 14 is separated from the substrate 17 by a thin insulating layer 60, which is formed by a thin oxide layer. Spacers 65 are placed on opposite ends of the gate 14. A source extension 61 extends from the source 15 to a point under the gate 14 so that the gate 14 overlaps with part of the source extension 61 by a source overlap length. A drain extension 62 extends from the drain 16 to a point under the gate 14 so that the gate 14 overlaps with part of the drain extension 62 by a drain overlap length. An effective gate length 27 (L.sub.eff) extends from an end of the source extension 61 to an end of the drain extension 62, so that the gate length (L.sub.MET) is the sum of the drain overlap length, the source overlap length, and the effective gate length 27.

The test device 11 uses an LCR meter 30. The LCR meter has a variable DC power source 19 and a AC source 20 in series with the DC source 19. A source variable DC power supply 22 is electrically connected between the source 15 and the substrate 17, and a drain variable DC power supply 23 is electrically connected between the drain 16 and the substrate 17. A controller 31 is electrically connected to the LCR meter 30, the source variable DC power supply 22, and the drain variable DC power supply 23. In the preferred embodiment a precision LCR meter (e.g. HP 4284 A) is used as a combined LCR meter 30 and controller 31 in single unit.

In operation, large area gate capacitors (e.g. 100.times.100 .mu.m) are employed to determine by experimentation the capacitance per unit of length C.sub.ox of the type of gate being measured. The capacitance per unit length C.sub.ox is entered into the controller 31. Throughout the measurements, a calibration structure is employed to zero out all the parasitic capacitances due to probing pad and wiring. By using HP4284 LCR meter the resolution of the measurement setup is better than 0.1 fF.

The controller 31 signals the LCR meter 30 to apply a set gate voltage V.sub.G to the gate. A fixed voltage is applied between the gate and the substrate. The absolute value of the fixed voltage applied between the gate 14 and substrate 16 V.sub.Gb is less than the absolute value of the threshold voltage V.sub.T of the MOS transistor 10, expressed as, .vertline.V.sub.Gb .vertline..ltoreq..vertline.V.sub.T .vertline.. The LCR meter 30 and controller 31 then measure and record the capacitance C.sub.gb (the capacitance between the gate 14 and the substrate 16, which is generated across the channel) for different voltages applied to the source and the drain. FIGS. 2a, 2b and 2c are schematic illustrations of the transistor 10 shown in FIG. 1 with depletion regions generated by different drain/source (meaning source or drain) to substrate voltages V.sub.SB /V.sub.DB. The testing setup is not shown to simplify the figures. The transistor 10 being tested in this example is an NMOS. In an NMOS transistor, the drain/source depletion region shrinks with an applied negative drain/source to substrate voltage V.sub.SB /V.sub.DB and expands with and applied positive drain/source to substrate voltage V.sub.SB /V.sub.DB. In a PMOS transistor, the opposite behavior will be observed. In the example shown in FIGS. 2a, 2b, and 2c the voltage applied to the source V.sub.SB is set to equal the voltage of the drain V.sub.DB through the testing, so that for these examples the voltage between the source and substrate V.sub.SB and the voltage between the drain and the substrate V.sub.DB are represented by a single notation V.sub.SD.

The controller 31 signals the source variable DC power supply 22 and the drain variable DC power supply 23 to apply a series of increasing voltages, which increases the lengths of the depletion regions 39 adjacent to the source 15 and the drain 16, as shown in FIGS. 2a, 2b, and 2c. FIGS. 2a, 2b, and 2c illustrate depletion regions 39 for the i-1, i, and i+1 values of the series of increasing voltages.

The controller 31 signals the source variable DC power supply 22 and the drain variable DC power supply 23 to set the source/drain to substrate voltage to V.sub.SD (i-1), which causes the depletion regions 38 adjacent to the source 15 and the drain 16, as shown in FIG. 2a. The width of the depletion regions for V.sub.SD (i-1) is notated as W(i-1), with the width of the depletion region being the sum of the lengths of the depletion regions 39. The controller 31 then signals the LCR meter 30 to measure the gate capacitance C.sub.gb (i-1), which is recorded by the controller 31.

The controller 31 signals the source variable DC power supply 22 and the drain variable DC power supply 23 to increase the source/drain voltage to V.sub.SD (i), which increases the lengths of the depletion regions 39 adjacent to the source 15 and the drain 16, as shown in FIG. 2b. The width of the depletion regions for V.sub.SD (i) is notated as W(i), with the width of the depletion region being the sum of the lengths of the depletion regions 39. The controller 31 then signals the LCR meter 30 to measure the gate capacitance C.sub.gb (i), which is recorded by the controller 31.

The controller 31 signals source variable DC power supply 22 and the drain variable DC power supply 23 to increase the source/drain voltage to V.sub.SD (i+1), which increases the lengths of the depletion regions 39 adjacent to the source 15 and the drain 16, as shown in FIG. 2c. The width of the depletion regions for V.sub.SD (i+1) is notated as W(i+1), with the width of the depletion region being the sum of the lengths of the depletion regions 39. The controller 31 then signals the LCR meter 30 to measure the gate capacitance C.sub.gb (i+1), which is recorded by the controller 31.

One way of determining effective channel length L.sub.eff is by setting V.sub.SD to the maximum negative value so that there is no depletion region. Then effective channel length L.sub.eff is defined as the length of the channel L.sub.C. Using the measured gate capacitance C.sub.gb (x) the controller is able to determine the channel length L.sub.c (x)=C.sub.gb (x)/C.sub.ox (Equation 2). L.sub.eff =L.sub.c (x) when there is no depletion region. There are other ways of determining the effective channel length, such as the method described in "A New `Shift and Ratio` Method for MOSFET Channel-Length Extraction", by Yuan Taur et al., IEEE Electron Device Letters. Vol 13, No: 5, May 1992, which can be used here, instead.

For V.sub.SD (x), the width of the depletion region 39 W(x)=L.sub.eff -L.sub.c (x), so that for V.sub.SD (i-1), W(i-1)=L.sub.eff -L.sub.c (i-1), and for V.sub.SD (i), W(i)=L.sub.eff -L.sub.c (i), and for V.sub.SD (i+1), W(i+1)=L.sub.eff -L.sub.c (i+1).

Starting with the general equation W(x)=L.sub.eff -L.sub.c (x) (Equation 3), we get: ##EQU2##

For the point V.sub.SD (i), dL.sub.c /dV.sub.gd can be estimated as: ##EQU3##

The controller 31 is then able to solve Equation 1 for N.sub.ch (i). The controller continues to take readings until the depletion regions of the source and drain contact each other so that the channel length L.sub.c approaches zero and the gate capacitance C.sub.gb drops abruptly.

The controller 31 calculates N.sub.ch (x) for every measured V.sub.SD (x). Assuming that the lateral doping profile is symmetric about the center of the gate, the controller 31 is able to calculate the doping profile at a distance x from and end of the gate.

In another embodiment of the invention using the same testing device at different settings in a different manner, the controller 31 signals the source variable DC power supply 22 output voltage V.sub.SB to always be set to the maximum negative value so that there is no depletion region around the source 15. The controller 31 signals the LCR meter 30 to apply a set gate voltage V.sub.G to the gate. The LCR meter 30 and controller 31 then measure and record the capacitance C.sub.gb (the capacitance between the gate 14 and the substrate 16, which is generated across the channel) for each different drain to substrate voltage V.sub.DB.

FIGS. 3a, 3b and 3c are schematic illustrations of the transistor 10 shown in FIG. 1 with depletion regions generated by different drain to substrate voltages V.sub.DB. The measurement setup is not shown to simplify the figures. The transistor 10 being tested in this example is an NMOS. In an NMOS transistor, the drain/source depletion region shrinks with an applied negative drain/source to substrate voltage V.sub.SB /V.sub.DB and expands with and applied positive drain/source to substrate voltage V.sub.SB /V.sub.DB (the opposite behavior will be observed for PMOSFET's).

The controller 31 signals the drain variable DC power supply 23 to apply a series of increasing voltages, which increases the lengths of the depletion region 39 adjacent to the drain 16, as shown in FIGS. 3a, 3b, and 3c. FIGS. 3a, 3b, and 3c illustrate depletion regions 39 for the i-1, i, and i+1 values of the series of increasing voltages.

The controller 31 signals the drain variable DC power supply 23 to set the drain to substrate voltage to V.sub.DB (i-1), which causes the depletion region 38 adjacent to the drain 16, as shown in FIG. 3a. The controller 31 then signals the LCR meter 30 to measure the gate capacitance C.sub.gb (i-1), which is recorded by the controller 31.

The controller 31 signals the drain variable DC power supply 23 to increase the drain voltage to V.sub.DB (i), which increases the length of the depletion region 39 adjacent to the drain 16, as shown in FIG. 3b. The controller 31 then signals the LCR meter 30 to measure the gate capacitance C.sub.gb (i), which is recorded by the controller 31.

The controller 31 signals the drain variable DC power supply 23 to increase the drain voltage to V.sub.DB (i+1), which increases the length of the depletion region 39 adjacent to the drain 16, as shown in FIG. 3c. The controller 31 then signals the LCR meter 30 to measure the gate capacitance C.sub.gb (i+1), which is recorded by the controller 31.

One way of measuring effective channel length L.sub.eff is by setting V.sub.SD to the maximum negative value so that there is no depletion region. Then effective channel length L.sub.eff is defined as the length of the channel L.sub.c. Using the measured gate capacity C.sub.gb (x) the controller is able to determine the channel length L.sub.c (x)=C.sub.gb (x)/C.sub.ox. L.sub.eff =L.sub.c (x) when there is no depletion region. There are other ways of measuring the effective channel length, such as the method described in "A New `Shift and Ratio` Method for MOSFET Channel-Length Extraction", by Yuan Taur et al., IEEE Electron Device Letters. Vol 13, No: 5, May 1992, which can be used instead.

For V.sub.DB (x), the width of the depletion region 39 W(x)=L.sub.eff L.sub.c (x), so that for V.sub.DB (i-1), W(i-1)=L.sub.eff -L.sub.c (i-1), and for V.sub.DB (i), W(i)=L.sub.eff -L.sub.c (i), and for V.sub.DB (i+1), W(i+1)=L.sub.eff -L.sub.c (i+1).

Starting with the general equation W(x)=L.sub.eff -L.sub.c (x) (Equation 3), we get: ##EQU4##

For the point V.sub.SD (i), dL.sub.c /dV.sub.gd can be estimated as: ##EQU5##

The controller 31 is then able to solve Equation 1 for N.sub.ch (i). The controller continues to take readings until the depletion region of the drain contacts the source extension so that the channel length L.sub.t approaches zero and the gate capacitance C.sub.gb drops abruptly. The controller 31 calculates N.sub.ch (x) for every measured V.sub.DB (x).

FIG. 4 is a graph plotting the gate capacitance C.sub.gb against the drain to substrate voltage V.sub.DB. A source/drain measurement curve 44 is a plot of data for a MOS transistor measurement where the applied voltage to the source is equal to the applied voltage to the drain. A drain measurement curve 45 is a plot of data for a MOS transistor measurement where the applied voltage to the source is fixed and equal to zero. The slope of a curve at a point in FIG. 4 is dC.sub.gb /dV.sub.SD =-C.sub.ox dW/dV.sub.SD. These curves are examples of the relationship between gate capacitance and voltage applied between the source/drain and the substrate, and the relationship between the depletion width and voltage applied between the source/drain and the substrate. Using these plotted values, W(x) can be calculated, which can be plugged into Equation 1, to calculate N.sub.ch (x).

FIG. 5 schematically illustrates a sample MOS transistor 70 that does not have halo implantation. Using the method described above, FIG. 5 also shows plotted curve 55, which plots x, a linear measurement along the length of the MOS transistor 70, against N.sub.ch (x) the lateral doping concentration. Curve 55 shows that the doping concentration under the gate of the MOS transistor 70 is reasonably constant.

FIG. 6 schematically illustrates another sample MOS transistor 71 that has halo implantation. Using the method described above FIG. 6 also shows plotted curve 56, which plots x, a linear measurement along the length of the MOS transistor 71, against N.sub.ch (x) the doping concentration. Curve 56 shows that the doping concentration near center of the channel is quite similar to the doping concentration of the MOS transistor 70 shown in FIG. 5. Curve 56 also shows that the MOS transistor 71 has very high peak doping peaks near the source and drain, which is due to the TED effect of the halo implantation.

FIG. 7 is a plot of the quasi-neutral channel length L.sub.c divided by the gate length L.sub.eff versus the second source drain voltage V.sub.SD with curve 46 plotting data from a non-halo doped device and curve 47 plotting data from a halo doped device. A higher L.sub.c and V.sub.SD margin is observed for the halo device, indicating improved short channel effect by using halo implantation. The voltage can either be applied between the source and the substrate or the drain and the substrate or both. For this reason in the claims, the notation first source/drain and second source/drain will be used. Under this notation, either the first source/drain can refer to the source, with the second source/drain referring to the drain, or the first source/drain can refer to the drain with the second source/drain referring to the source. In addition, in the claims the use of equation 1, also includes equations that are equivalent to equation 1, such as equations where capacitance is used instead of depletion width.

The present invention has been particularly shown and described with respect to certain preferred embodiments and features thereof. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the inventions as set forth in the appended claims. The inventions illustratively disclosed herein may be practiced without any element which is not specifically disclosed herein.