Salicide Process

1. Field of Invention

The present invention relates to a MOS process sequence. More particularly, the present invention relates to a salicide process.

2. Description of Related Art

FIGS. 1A-1C are schematic, cross-sectional views of a conventional salicide process.

As shown in Fig. 1A, several device isolation regions 102 are formed and over a substrate 100. A thin oxide layer 104 is formed between the isolation regions 102 over the substrate 100. A gate 106 and a gate sidewall spacer 108 thereof are formed over the thin oxide layer 104.

As shown in FIG. 1B, ions are implanted into the substrate 100. An annealing step is then performed to form source/drain regions 110.

As shown in FIG. 1C, the gate 106 and the source/drain regions 110 are covered by a silicide film 112. Because those silicide films 112 are formed using a self-aligned process that does not entail any additional masking steps, the silicide-covering process is referred to as a salicide process.

The salicide process in a CMOS process reduces the gate resistance. However, the gate resistance, such as gate sheet resistance, increases as the gate length reduces. On the other hand, increasing the gate area is important to improve the gate sheet resistance. Therefore, there is a need for a new salicide process that can increase the gate area to improve the gate resistance.

The invention provides a salicide process. A gate with a sidewall is provided over a substrate. A first spacer is formed on the sidewall of the gate. The gate is partially removed to create an opening on the gate, wherein the opening has a sidewall composed of the first spacer. A second spacer is formed on the sidewall of the opening. A mask layer partially filling the opening is formed. The second spacer is removed. The gate is etched to form a plurality of trenches into the two sides of the gate by using the mask layer as an etching mask. A self-aligned silicide is formed over the etched gate.

In this present invention, the two sides of the gate are etched to increase the gate area, thereby reducing the gate resistance after forming a self-aligned silicide film over the etched gate.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

FIGS. 1A-1C are schematic, cross-sectional views of a conventional salicide process; and

FIGS. 2A-2H are schematic, cross-sectional views of a salicide process according to one preferred embodiment of this invention.

FIGS. 2A-2H are schematic, cross-sectional views of a salicide process according to one preferred embodiment of this invention. Although the salicide process will be described according to the preferred embodiment, it is to be understood that the scope of the invention is not limited to the disclosed process. Therefore, persons skilled in the art can modify and arrange the disclosed process by, for example, adding or deleting a step(s) without departing from the spirit of the invention.

As shown in FIG. 2A, a MOS device comprising a gate 206 and source/drain regions 210 is formed on a substrate 200 (e.g. silicon substrate). The MOS device can be formed by steps comprising, for example, a polysilicon deposition step, a gate patterning step, an implanting step, and an annealing step. After a thin oxide layer 204 is formed between several device isolation regions 202 on the substrate 200, a polysilicon layer (not shown) is deposited over the substrate 200 in the polysilicon step and is then patterned form a gate 206 on the thin oxide layer 204 in the gate patterning step. After the gate sidewall spacer 208 is formed, ions are implanted into the substrate in the implanting step and are then annealed for the formation of source/drain regions 210 in the annealing step.

Preferably, the polysilicon layer is deposited to a thickness of about 4000 to about 5000 angstroms. The thin oxide layer 204 and the device isolation regions 202 can be made of silicon oxide by thermal oxidation. The device isolation regions 202 can be alternatively formed by a shallow trench isolation technique.

As shown in FIG. 2B, a first dielectric layer 212 is formed to surround the gate sidewall spacer 208 and to cover the substrate 200. A process for forming the first dielectric layer 212 comprises a deposition step and a polishing step. In the deposition step, a first dielectric material layer (not shown) is deposited over the substrate 200, wherein a portion of the first dielectric material layer is higher than and covers the gate 206. In the polishing step, the portion of the first dielectric material layer higher than the gate 206 is removed by means of chemical-mechanical polishing, and the remaining first dielectric material layer serves as the desired first dielectric layer 212. The first dielectric material can be nitride, or preferably be silicon nitride.

As shown in FIG. 2C, the gate 206 (shown in FIG. 2B) is partially removed. After being partially removed, the gate 206a has a top surface substantially lower than that of the first dielectric layer 212. In other words, an opening 215 with a sidewall is formed on the remaining gate 206a after the gate 206 is partially removed. The opening 215 is formed to a depth of about 1000 angstroms. That is, the remaining gate 206a has a thickness of about 3000 to about 4000 angstroms, because the gate 206 (shown in FIG. 2B) preferably has a thickness of about 4000 to about 5000 angstroms before being partially removed. The formed spacer 214 covers an edge of the exposed gate 206a.

Another spacer 214 is formed on the sidewalls of the opening 215. The spacer 214, with a width of about 500 angstroms, can be formed by performing a deposition step and an etch back step. In the deposition step, an oxide layer (not shown), preferably a silicon oxide layer, is formed to over-filling the opening 215. In the etch back step, the deposited oxide layer is etched back until the first dielectric layer 212 is exposed.

As shown in FIG. 2D, a second dielectric layer 216 is formed to partially fill the opening 215 over the gate 206a. This formation process comprises, for example, a deposition step and an over-polishing step. In the deposition step, a second dielectric material layer (not shown) is deposited to fill the opening 215 and to cover the first dielectric layer 212. In the over-polishing step, the second dielectric material layer is over-polished by means of chemical-mechanical polishing. After being over-polished, the second dielectric material layer, having a top surface lower than that of the first dielectric layer 212, serves as the second dielectric layer 216 that partially fills the opening. The second dielectric layer 216 can be made of nitride, or preferably be made of silicon oxynitride (SiON).

In addition to the over-polishing step, an etching back step can alternatively accomplish the formation of the second dielectric layer 216. In this etching back step, the second dielectric material layer is etched back to have a top surface substantially lower than that of the first dielectric layer 212, and therefore to create the second dielectric layer 216.

As shown in FIG. 2E, the spacer 214 (shown in FIG. 2D) is removed from the sidewall of the opening 215 (shown in FIG. 2D), so that the edge of the gate 206a is exposed. The spacer 214 can be removed by wet etching. Although the tips of the gate sidewall spacer 208 (shown in FIG. 2D), and a tiny portion of the first dielectric layer 212 substantially close to the tips may also be simultaneously removed in this removal step, such partial removal phenomenon does not depart from the spirit of the present invention.

As shown in FIG. 2F, the edge of the gate 206a are etched, with the second dielectric layer 216, the gate sidewall spacer 208a and the first dielectric layer 212 serving as an etching mask. After this etching step, the edge of the gate 206a are substantially lower than the center of the gate 206a. Such etched gate 206a, also a called a reversed T-shaped gate, is incorporated with the gate sidewall spacer 208a to form two trenches 218 on the edge of the etched gate 206a. Each of the trenches 218 preferably has a depth of about 2000 angstroms, and can be adjusted to optimize each process, but only if the trench 218 does not expose the thin oxide layer 204.

As shown in FIG. 2G, the first and the second dielectric layers 212 and 216 (shown in FIG. 2F) are removed with, for example, a phosphorous acid (H.sub.3 PO.sub.4) solution.

As shown in FIG. 2H, both the gate 206a and the source/drain regions 210 are covered by a silicide film 220. Because those silicide films 220 are formed using a self-aligned process that does not entail any additional masking steps, the silicide-covering process is referred to as a salicide process. If the substrate 200 and the thin oxide layer 204 are made of silicon and silicon oxide respectively, the salicide process can be performed by a metal deposition step and an annealing step. In the metal deposition step, a metal layer (not shown), such as titanium, tungsten or cobalt layer, is deposited over the substrate 200. In the annealing step, a portion of the metal layer is transformed into several silicide films 220 that self-align over the gate 206a and the source/drain regions 210, respectively. The silicide films 220 can be made of titanium silicon, tungsten silicon, or cobalt silicon, according to the need of each process.

In this present invention, the edge of the gate are etched to increase the gate area, thereby reducing the gate resistance after forming a self-aligned silicide film over the etched gate.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.