Frequency Divider With Lower Power Consumption

1. Field of the Invention

The present invention is directed to a frequency divider of the type employed in mobile telecommunication systems, and is directed particularly to a type of frequency divider known as a "dual modulus prescaler".

2. Description of the Prior Art

Frequency dividers of the type known as dual modulus prescalers are employed in frequency synthesizers of mobile telecommunication systems. Such frequency dividers have division factors switchable between 1/N and 1/(N+1), whereby N typically amounts to 64 or 128, and operate at frequencies on the order of magnitude of 1 GHz and are a component of every GSM or in DECT telephone. Since such telephones are usually batter-powered, the importance of low power consumption by all components, including the frequency divider, is significant.

Examples of the employment and the structure of such prescalers are known from the IEEE Journal of Solid-State Circuits, Vol. 29, No. 10, October, 1994, pages 1206 through 1211 as well as Vol. 27, No. 12, December, 1992, pages 1794 through 1798, wherein asynchronous divider expansion stages follow a respectively synchronous 1:4/5 divider.

An object of the present invention is to provide a frequency divider of the above-described type that exhibits an especially low power consumption.

The above object is achieved in a frequency divider constructed in accordance with the principles of the present invention having a frequency halver, to which an input signal having a frequency f is supplied, which forms an intermediate signal with only the frequency f/2 from the input signal, an intermediate divider which, dependent on a switching signal, generates a second intermediate signal having the frequency f/8 from the first intermediate signal if division by a factor 1/N is desired by reducing the frequency of the first intermediate signal by a division factor of 1/4, and which generates a second intermediate signal having the frequency f/10 from the first intermediate signal if division by a factor of 1/(N+1) is desired by reducing the frequency of the first intermediate signal by a division factor of 1/5, a divider expansion with 2.sup.N-2 divider stages including a penultimate divider stage which supplies an output signal with the frequency f/N or f/(N+1), and a logic circuit which generates the aforementioned switching signal from a control signal and output signals of the stages of the divider expansion.

In an embodiment, a jitter compensation circuit can be provided in the divider expansion. If the number of divider stages in the divider expansion is even, so that the divider stages can be grouped into a first half of stages and a second half of stages, the jitter compensation circuit can add an output signal from a last divider stage of the second half of divider stages with a clock signal for a first stage in the second half of the divider stages.

FIG. 1 is a circuit diagram of a preferred exemplary embodiment of the inventive frequency divider.

FIG. 2 shows time diagrams for explaining the functioning of the circuit of FIG. 1.

FIG. 3 is a circuit diagram of another preferred exemplary embodiment of the inventive frequency divider.

In accordance with the invention, an intermediate signal with the frequency f/2 is initially formed from the input signal IN with the frequency f by a frequency halver before this signal, as in the prior art, is supplied to a 1:4/5 divider. Further, the output signal of a penultimate stage of an expansion divider is employed as the output signal of the frequency divider instead of the output signal of a last stage. This results in only one flipflop being operated with the maximum frequency f=1 GHz, and, thus, a noticeable reduction of the overall power consumption of the frequency divider can be achieved. Since a pre-amplifier for driving the clock lines of the intermediate 1:4/5 divider can be foregone under certain circumstances, this leads to a further power reduction.

As an example, FIG. 1 shows a frequency divider for the division factors 1/64 and 1/65, having an input-side frequency halver H, an intermediate divider 4/5 and a divider expansion EXT. The input-side frequency halver H generates an intermediate signal 1 exhibiting only the frequency f/2 from an input signal IN having the frequency f. Dependent on a switchover signal U the intermediate divider 4/5 generates a second intermediate signal 2 with the frequency f/8 from the first intermediate signal in the case of a desired division factor 1/N, by reducing the frequency with the division factor 1/4 and, given a desired division factor 1/(N+1), generates the intermediate signal 2 with the frequency f/10 from the first intermediate signal by reducing the frequency with the division factor 1/5. The divider expansion EXT contains 2.sup.N-2 divider stages (FF5 . . . FF8) whose penultimate divider stage FF7 supplies an output signal OUT with the frequency f/N, or f/(N+1). The switchover signal U is formed by an AND gate A3 from a negated control signal MOD and from the negated output signals 3 . . . 6 of the respective divider stages FF5 . . . FF8. The frequency halver H is fashioned such that the input signal IN of the frequency divider serves as the clock signal for a D-flipflop FF1 therein, whose inverted output carries the signal 1 which is fed back onto the D-input. The intermediate divider 4/5 contains three flipflops FF2 . . . FF4 synchronously clocked by the signal 1, with the D-input of the flipflop FF2 being connected to an AND gate A1 that operates on the switchover signal U. The D-input of the flipflop FF3 being connected to an AND gate A2 that operates on a negated output signal of the flipflop FF2 with a negated output signal of the flipflop FF4, and the non-inverted output of the flipflop FF3 is connected to the D-input of the flipflop FF4. The flipflops FF5 . . . FF8 of the divider expansion EXT are connected here as asynchronous counters, with the respective clock inputs of the D-flipflops FF6 . . . FF8 being connected to the inverted output of the predecessor stage, and the clock input of the flipflop FF5 receiving the signal 2. All flipflops FF1 . . . FF8 are D-flipflops with a clock input triggering at positive signal edges. Due to the input-side frequency halving, a division by 128 or 130 arises at the output of the last stage of the expansion divider EXT. The desired division by 64 or 65 is achieved by taking the output signal OUT at the output of the penultimate stage of the expansion divider EXT.

FIG. 2 shows the output signal OUT of the circuit shown in FIG. 1, wherein 34 periods with high level are followed by 32 periods with low level, followed by 32 periods of high level and, finally, another 32 periods of low level. In addition to the desired fundamental, an analysis of this signal shows a further signal with half the output frequency and amplitude 2/65. This corresponds to an undesired superimposition of a noise voltage (jitter) with the frequency of the fundamental of the output signal.

For eliminating this undesired jitter, a further preferred exemplary embodiment of the invention is shown in FIG. 3 wherein a jitter at the output OUT is avoided by a modified divider expansion EXT' with a jitter compensation circuit JK. Except for the modified divider expansion EXT' instead of the divider expansion EXT, the circuit of FIG. 3 corresponds to the circuit of FIG. 1. The jitter compensation circuit JK is formed, for example, by a resistor R1 that connects the inverted output signal 4 of the flipflop FF6 to the clock input of the flipflop FF7, and an AND gate A4 which emits a signal 7 that is supplied to the clock input of the flipflop FF7 via a further resistor R2. The signal 7 is formed by the AND gate A4 operating on the inverted output signal of the flipflop FF8 and the inverted control signal MOD. This results in a signal having the amplitude -2/65 with half the frequency of the output signal being mixed with the signal 4 and the jitter is thereby eliminated.

Given an even number of divider expansion stages, so that the stages can be grouped as a first half of the stages and a second half of the stages, the jitter compensation circuit JK is in general constructed so that a signal dependent on the output signal of the last divider stage, such as FF8 is added with a clock signal for a first stage, such as FF7, of the second half of the divider stages, such as FF7, FF8 following the first half of the divider stages, such as FF5, FF6.

Although modifications and changes may be suggested by those skilled in the art, it is the intention of the inventors to embody within the patent warranted hereon all changes and modifications as reasonably and properly come within the scope of their contribution to the art.