US 6,064,077 AGrant
Integrated Circuit Transistor
Issue Date:2000-05-16
•4 Claims
•1 Drawing Sheets
Abstract
A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.
Metadata
Assignee
- STMicroelectronics, Inc.
Inventor
- Ravishankar Sandaresan
Application Information
Application Number:US 3505049
Filing Date:1994-12-06
Priority Date:1991-08-30
Art Unit:285
Classifications
IPC:
H01L 2976H01L 2994H01L 31062
Field of Search:
35725723.3;23.4;23.11327;336;387;550;344;408;328;329;335;337;338;339
Patent Drawings (1 sheets)
Description
Background of the Invention
1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to a transistor suitable for use in integrated circuit devices having small feature sizes.
2. Description of the Prior Art
As semiconductor integrated circuits continue to become smaller, it becomes increasingly difficult to fabricate transistors which operate reliably and predictably. As device feature sizes shrink to dimensions well below one micron, transistors become strongly affected by short channel effects.
Short channel effects occur as a result of the voltage field at the drain. Since the channel is very short, the electric fields from both the gate and drain affect the flow of current through the channel, changing operation of the transistor from the desired parameters. If the drain electric field is strong enough, the depletion region can extend all the way to the source, resulting in punch through.
Short channel effects can mostly be negated by increasing the dopant concentration in the channel region. However, undesirable side effects occur as a result of increasing the dopant concentration. Carrier mobility is degraded, lowering transistor gain, and threshold voltage (V.sub.t) is increased.
It would be desirable to provide a transistor structure, and method for making same, which provides improved avoidance of short channel effects without unduly adversely affecting transistor operating characteristics. It would be further desirable for such a structure and method to be compatible with widely available fabrication techniques.
Summary of the Invention
Therefore, according to the present invention, a method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.
Brief Description of the Drawings
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1-3 illustrate one preferred method for forming integrated circuit structures according to the present invention; and
FIG. 4 illustrates an alternative integrated circuit structure formed in accordance with the present invention.
Description of the Preferred Embodiment
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Referring to FIG. 1, a substrate 10 is used for the formation of integrated circuit devices. Field oxide regions 12 are formed in the substrate 10 as known in the art. An upper surface region 14 of the substrate 10 is doped with a moderate amount of impurities.
The dopant concentration for region 14 is selected to be a moderate level which allows short channel effects to be controlled. If an n-channel transistor is to be formed, the region 14 can be doped with, for example, approximately 5.times.10.sup.17 atoms/cm.sup.3 of boron. The dopant in region 14 may be implanted or diffused into the substrate 10 as known in the art.
A thin epitaxial silicon region 16 is then grown on the substrate 10. Epitaxial region 16 may be grown using molecular beam epitaxy (MBE) or a low temperature epitaxial growth process. Low temperature processes, less than approximately 850.degree. C., are preferably used to minimize outdiffusion of dopant from the region 14. Layer 16 is preferably grown to a thickness of approximately 500-1000 angstroms, and will contain the channel of the field effect transistor to be formed.
Referring to FIG. 2, a thermal oxidation step is performed to convert a portion of the epitaxial layer 16 to gate oxide 18. Gate oxide layer 18 is preferably less than approximately 150 angstroms thick. A polycrystalline silicon layer is then deposited over the entire device and patterned as known in the art to form a polycrystalline silicon gate electrode 20. If desired, the polycrystalline silicon layer can be doped before patterning, and the polycrystalline silicon electrode 20 can be formed to include a refractory metal silicide to improve conductivity. Such techniques are well known in the art.
Referring to FIG. 3, source/drain regions 22 are formed in the substrate 10 and epitaxial layer 18 by implantation and anneal as known in the art. The source/drain region 22 junction extends into the moderately doped region 14. The extension of this junction into the region 14 minimizes the short channel effect due to its higher dopant concentration. The channel of the transistor is formed in the epitaxial layer 16 beneath the gate electrode 20. Since the epitaxial layer 16 is relatively lightly doped, the resulting transistor has good operating characteristics. If desired, prior to the formation of the polycrystalline silicon layer over the gate oxide layer 18, a V.sub.t adjust implant can be made into the epitaxial layer 16 in order to set the threshold voltage of the transistor to a desired value. Dopant outdiffusion from the moderately doped region 14 during epitaxial growth and later processing steps will also tend to vary the threshold voltage somewhat, and the V.sub.t implant may not be necessary.
Referring to FIG. 4, the technique of growing the additional epitaxial layer 16 can be used to form a self-aligned, lightly doped drain (LDD) structure. As known in the art, after patterning of the gate electrode 20, an LDD implant is made to form lightly doped source/drain regions 24. Sidewall oxide regions 26 are then formed along side the gate electrode 20 using an oxide deposition and anisotropic etch as known in the art, followed by implant of the heavily doped source/drain regions 28. As before, the extension of the source/drain region junctions into the moderately doped region 14 reduces short channel effects, while the formation of the transistor channel in the lighter doped epitaxial layer 16 underneath a gate 20 produces a transistor having good operating characteristics.
As an alternative to growing the epitaxial layer 16 in FIG. 1, a selective amorphous silicon deposition may be performed followed by a solid-phase epitaxial regrowth of the amorphous silicon. Such a regrowth step may be performed at approximately 550.degree. C.-600.degree. C. as known in the art.
As will be appreciated by those skilled in the art, the technique described above results in a transistor which suffers minimal degradation from short channel effects, and has good operating characteristics due to the channel being formed in a relatively lightly doped epitaxial layer. Formation of the epitaxial layer 16 adds only minimal complexity to standard process flows, and allows high quality transistors to be fabricated using feature sizes of approximately one-half micron and less.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims
What is claimed is:
1. An integrated circuit device, comprising: a substrate having a doped region therein, said doped region having a first doping level; an epitaxial silicon region overlying the doped substrate region, said epitaxial silicon region having a second doping level that is less than said first doping level; a gate insulating layer and gate electrode overlying the epitaxial silicon region, wherein a channel region is formed under the gate electrode in said epitaxial silicon region; sidewall insulating regions disposed alongside said gate electrode; lightly doped source/drain regions in said epitaxial silicon region and said substrate underneath said sidewall insulating regions and adjacent the channel region; highly doped source/drain regions in said doped substrate region and said epitaxial silicon region adjacent the lightly doped source/drain regions, each of said highly doped source/drain regions extending from an upper surface of said epitaxial silicon region into said doped substrate region; and a threshold adjust impurity region within the channel region.
2. The device of claim 1, wherein said gate insulating layer comprises oxide.
3. The device of claim 1, wherein the doped substrate region has an impurity concentration of approximately 5.times.10.sup.17 atoms/cm.sup.3.
4. The device of claim 1, wherein said gate electrode has a width less than approximately 0.5 micron.
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Non-Patent Literature (1)
- 7th Biennial University/Government/Industry Microelectronics Symposium, Rochester, NY, Jun. 11, 1987, pp. 28-33, F. C. Jain "Improved LDD-FET structures with lightly doped n- sheaths around the n+ source/drain regions".