Method of Curvature Compensation, Offset Compensation, and Capacitance Trimming of a Switched Capacitor Band Gap Reference

The invention relates to switched capacitor band gap reference circuits, and more particularly to "curvature correction" therefor.

The closest prior art is believed to include U.S. Pat. Nos. 5,059,820, 4,375,595 (Ulmer et al.), and U.S. Pat. No. 5,563,504 (Gilbert et al.), which disclose switched capacitor band gap reference circuits having no curvature compensation.

Silicon band-gap voltage reference circuits are widely used to provide precision internal reference voltages in integrated circuits. There are many implementations of band-gap reference circuits, most of which have been of a "continuous time" nature. That is, most of the known band-gap reference circuits are analog circuits that do not include switching circuitry. However, many CMOS integrated circuit structures include nearly ideal capacitors; this has led to development of accurate band-gap reference voltage circuits using "discrete time" switched capacitor circuits. The above mentioned patents disclose several such switched capacitor band-gap voltage reference circuits, in which ratios of nearly ideal capacitors determine reference voltage scaling factors.

Prior art FIG. 1 shows switched capacitor voltage reference circuit 1, which includes a conventional switched capacitor voltage reference circuit 2 as generally disclosed in above mentioned U.S. Pat. No. 5,059,820, with a conventional sample/hold and buffer output circuit 4. Briefly, the currents NI and I of current sources 16 and 18, respectively, are time-multiplexed during non-overlapping clock signals .phi.1 and .phi.2 to produce the current I.sub.1 flowing through diode-connected transistor Q1 so as to produce in a capacitor C2A a charge proportional to a V.sub.BE voltage of transistor Q1 when it is conducting current NI; that charge, which has a negative temperature coefficient, then is transferred to feedback capacitor C2. Then, a change in charge proportional to a .DELTA.V.sub.BE voltage which transistor Q1 undergoes when the current through it changes from NI to I is stored on capacitor C1; that charge, which is proportional to absolute temperature, then is transferred to feedback capacitor C2. The net charge transferred to feedback capacitor C2 is converted by operational amplifier 25 to the voltage V.sub.OUT on conductor 27. A conventional sample and hold circuit and buffer circuit 4 simply converts the voltage V.sub.OUT to a "continuous time" reference voltage V.sub.REF.

The circuit of prior art FIG. 1 and all of the known band-gap reference circuits perform, in essence, the summation of a base-emitter voltage V.sub.BE of a transistor which has a negative temperature coefficient with a PTAT (proportional to absolute temperature) voltage which has a positive temperature coefficient in order to achieve cancellation of the positive and negative temperature coefficients. However, all band-gap reference circuits also exhibit an inherent undesirable "curvature" in their reference voltage versus temperature characteristic, due to the non-linearity of the temperature coefficient of the V.sub.BE voltage of any bipolar transistor. So-called "curvature compensation" circuitry has been used in conjunction with the known "continuous time" band-gap voltage reference circuits in order to achieve reduction in such curvature, as shown in U.S. Pat. No. 5,519,308 (Gilbert et al.). However, the known prior curvature compensation circuits are compatible only with the known "continuous time" or analog band-gap voltage reference circuits, but have not been used with switched capacitor band-gap voltage reference circuits.

Accordingly, it is an object of the invention to provide a curvature correction circuit for a switched capacitor band gap reference voltage circuit.

It is another object of the invention to avoid the effects of thermal drift in a switched capacitor band gap reference voltage circuit.

It is another object of the invention to provide a band gap reference circuit which is more accurate than has been achievable using either prior continuous time band gap reference circuits or prior switched capacitor band gap reference circuits.

It is another object of the invention to provide a switched capacitor band gap reference circuit in which the switched capacitor circuits conveniently eliminate the effect of input offset of an amplifier therein.

It is another object of the invention to provide a circuit and method for trimming integrated circuit capacitances with a degree of accuracy that is substantially higher than the accuracy of the capacitance of a minimum sized capacitor that can be manufactured using a particular manufacturing process.

Briefly described, and in accordance with one embodiment thereof, the invention provides a curvature compensated switched capacitor band gap reference circuit, a switched capacitor band gap reference circuit including a first .DELTA.V.sub.BE -generating circuit. The first .DELTA.V.sub.BE -generating circuit includes at least a first transistor (Q1), a first current switching circuit (44,45,52) adapted to produce first (IPT1) and second (IPT7+IPT1) currents through the first .DELTA.V.sub.BE -generating circuit causing it to produce a first .DELTA.V.sub.BE voltage and transfer a corresponding first charge into a summing conductor (24) and a feedback capacitor C2) of an operational amplifier (25). The first .DELTA.V.sub.BE -generating circuit also includes a second capacitor (C2A) coupled to store a V.sub.BE voltage and transfer a corresponding second charge into the summing conductor (24) and the feedback capacitor (C2). A curvature correction circuit includes a second .DELTA.V.sub.BE -generating circuit. The second .DELTA.V.sub.BE -generating circuit includes at least a second transistor (Q3) and a second current switching circuit (41,42,14) adapted to produce only a third current (IPTO) and then only a fourth current (I.sub.OTC) through the second .DELTA.V.sub.BE -generating circuit causing it to produce a second .DELTA.V.sub.BE voltage, and a curvature correction capacitor (C4) coupled to receive the second .DELTA.V.sub.BE voltage and couple a corresponding curvature correction charge into the summing conductor (24) and the feedback capacitor (C2), to thereby produce a curvature compensated voltage on an output of the operational amplifier, the first, second and third currents being PTAT/R currents. In one embodiment a first current source (43) is connected to produce a PTAT/R current (IPT2) through a third transistor (Q2), causing it to produce the V.sub.BE voltage. In one embodiment the fourth current is a V.sub.BE /R current, and the second current switching circuit is adapted to cause the third current and then both the third current and the fourth current to flow through the second transistor (Q3). In the described embodiments the various PTAT/R currents are produced by applying a PTAT voltage across a resistor having a non-zero temperature coefficient. The capacitances of the third capacitor (C2A) and the feedback capacitor (C2) can be trimmed to maintain a constant sum of the capacitances of the feedback capacitor (C2) and the third capacitor (C2A) by providing a capacitance trimming array (62) including a group of trim capacitors (127) each having a first conductor coupled to the summing conductor (24), a first terminal (57), a second terminal coupled to the summing conductor (24), and a third terminal (56), the feedback capacitor (C2) being coupled between the first (57) and second (24) terminals, and the third capacitor (C2A) being coupled between the second terminal (24) and the third terminal (56). A trim capacitor (C127-i) of the group (127) can be switched into parallel connection with the feedback capacitor (C2) and while also switching that trim capacitor (C127-i) out of parallel connection with the third capacitor (C2A) in response to a first logic level (B-i) of a corresponding bit of a digital trim word, or vice versa. Very small trim adjustments to the capacitances of the feedback capacitor (C2) can be made by providing a capacitance trimming array (62) including a first group of trim capacitors (127), a second group of trim capacitors (132), a first terminal (57), and a second terminal (24), the feedback capacitor (C2) being coupled between the first (57) and second (24) terminals. A trim capacitor (C127-i) of the first group (127) can be switched into parallel connection with the feedback capacitor (C2) and simultaneously switching a corresponding trim capacitor (132-i) of the second group (132) out of parallel connection with the feedback capacitor (C2) in response to a first logic level (B-i) of a corresponding bit of a digital trim word, or vice versa, to cause a change in the capacitance between the first and second terminals by an amount equal to the difference between the capacitances of the corresponding capacitors of the first and second groups.

FIG. 1 is a schematic diagram of a prior art switched capacitor band gap reference circuit generally as disclosed in U.S. Pat. No. 5,059,820.

FIG. 2 is a diagram illustrating use of the curvature correction circuit of the present invention in conjunction with the prior art switched capacitor band gap reference circuit of FIG. 1.

FIGS. 3A-3D each constitute the schematic diagram of the same preferred embodiment of the invention, but with different switch configurations to facilitate description of the operation during different phases.

FIG. 4 is a detailed circuit schematic of a particular implementation of the embodiment disclosed in FIGS. 3A-D.

FIG. 5 is a schematic drawing of the switched current source circuitry contained in block 40 of FIG. 4.

FIG. 6 is a detailed circuit schematic diagram of the amplifier 25 in FIG. 4.

FIG. 7 is a timing diagram for the timing signals .phi.1, .phi.2, .phi.3 and .phi.4 and the voltage on summing node 24 of FIG. 3A.

FIG. 8 is a graph illustrating "curvature" of an uncorrected switched capacitor band gap reference circuit output voltage, a correction signal produced by the curvature correction circuit 3 of FIG. 4, and the corrected band gap reference voltage produced by the curvature-corrected switched capacitor band gap reference circuit of FIG. 4.

FIG. 9 is a schematic diagram of an alternative embodiment of the invention.

FIG. 10 is a diagram of a capacitor trimming circuit that allows trimming of capacitor C1 in FIG. 3A with a resolution of 0.5 femtofarads.

Referring to FIG. 2, curvature-corrected switched capacitor reference band gap circuit 1 includes both the prior art switched capacitor band gap circuit 2 described above and a curvature compensation circuit 3. (Or, one of the switched capacitor band-gap reference voltage circuits shown in U.S. Pat. Nos. 5,563,504 and 4,375,595 could be used instead of the one shown in FIG. 2.) Curvature compensation circuit 3 includes a PTAT/R current source circuit 10 and a 0TC/R current source 13. A current produced by a PTAT (proportional to absolute temperature) voltage across a resistor is referred to as a PTAT/R current. Similarly, a current produced by an 0TC (zero temperature coefficient) voltage across a resister is referred to as a 0TC/R current.

PTAT/R current source 10 is connected between +V.sub.S and a first terminal of a switch 11 actuated by .phi.1. .phi.1 and .phi.2 are non-overlapping clock signals. The second terminal of switch 11 is connected by conductor 12 to a first terminal of a .phi.2-actuated switch 14, the second terminal of which is connected to 0TC/R current source 13. 0TC/R current source 13 is connected between +V.sub.S and second terminal of .phi.2-actuated switch 14. Conductor 12 is connected to the emitter of a diode-connected PNP transistor Q3, the base and collector of which are connected to ground. A capacitor C4 is connected between conductor 12 of curvature correction circuit 3 and the summing conductor 24 of prior art switched capacitor band gap circuit 2, as shown.

During "charging phase" .phi.1, switch 11 is closed and switch 14 is open, so the current flowing through transistor Q3 is equal to I.sub.PTAT/R. This produces an emitter-base voltage V.sub.BE31 on conductor 12 during .phi.1.

During "reference phase" .phi.2, switch 14 is closed and switch 11 is open, so the current through transistor Q3 is equal to I.sub.OTC/R. At all temperatures (except one) I.sub.PTAT is different than I.sub.OTC/R. So, when the current through diode Q3 is equal to I.sub.OTC/R during .phi.2, the voltage on conductor 12 is equal to V.sub.BE32 which differs from V.sub.BE31. In accordance with the present invention, this difference in voltage on conductor 12 is a .DELTA.V.sub.BE3 curvature compensation voltage change that causes a curvature correction charge equal to C.sub.4 (V.sub.B31 -V.sub.B32) of the correct polarity to be transferred from capacitor C4 via summing node 24 into feedback capacitor C2. The .DELTA.V.sub.BE curvature correction voltage change produced on conductor 12 and the corresponding curvature correction charge transferred into feedback capacitor C2 has a shape indicated by curve B in FIG. 8 that precisely matches the shape indicated by curve A in FIG. 8 of the residual band-gap curvature error of switched capacitor band-gap voltage reference circuit 2. Note that the capacitances of the various capacitors herein are indicated by the same alphanumeric characters used to designate the capacitors themselves. For example, C2 is the capacitance of capacitor C2, etc. The ratio of C2 to C4 provides a constant scale factor needed to provide almost exact curvature compensation of the voltage V.sub.OUT produced on conductor 27, as indicated by curve C in FIG. 8.

The operation of prior art switched capacitor band gap reference circuit 2 in FIG. 2 is that during charging phase .phi.1 the PTAT/R current NI develops a voltage V.sub.BE11 across transistor Q1, so capacitors C1 and C2A are charged to V.sub.BE11. Then, during reference phase .phi.2 the PTAT/R current I through transistor Q1 charges conductor 20 to V.sub.BE12, causing capacitor C1 to transfer charge proportional to the change in the V.sub.BE voltage, i.e., .DELTA.V.sub.BE1, of transistor Q1 to feedback capacitor C2. The difference .DELTA.V.sub.BE1 between V.sub.BE11 and V.sub.BE12 is proportional to absolute temperature, since I and NI both are PTAT/R currents. The voltage V.sub.BE11 stored on capacitor C2A during .phi.1 also is transferred to feedback capacitor C2 when switch 23 is closed during .phi.2. The above mentioned voltage change .DELTA.V.sub.BE3 equal to V.sub.BE31 -V.sub.BE32 on conductor 12 of curvature correction circuit 3 then superimposes the above mentioned curvature correction charge into the summing node 24 of operational amplifier 25 and hence into feedback capacitor C2 to correct the basic band-gap voltage developed on summing node 27 by the conventional switched capacitor band-gap voltage reference circuit 2.

As subsequently shown, the voltage V.sub.OUT on conductor 27 is given by the expression: ##EQU1## where the known switched capacitor voltage reference circuit 2 produces the first two terms on the right hand side of the above equation, and the curvature correction circuit 3 of the present invention provides the third term on the right hand side of the equation.

FIG. 3A shows a simplified schematic diagram of the preferred embodiment of the invention including a different switched capacitor band gap reference circuit 2A that does not utilize the same transistor Q1 to develop both the required V.sub.BE and .DELTA.V.sub.BE signals, in contrast to the prior art circuit 2 of FIG. 2. Instead, the switched capacitor reference circuit 2A in FIG. 3A develops the .DELTA.V.sub.BE signal across transistor Q1 and develops the V.sub.BE signal across transistor Q2. Curvature correction circuit 3 is similar to the one in FIG. 2, except that current source 41 in FIG. 3A is a V.sub.BE /R current source, rather than a 0TC/R current source such as current source 13 in FIG. 2. As subsequently explained, this is because in FIG. 3A current sources 41 and 42 can simultaneously flow through transistor Q3, whereas in FIG. 2 current sources 10 and 14 do not flow simultaneously through transistor Q3.

A diode-connected PNP transistor Q4 has its base and collector connected to ground and its emitter connected to conductor 34, to receive "dump" currents from current sources 41 and 45 when they are not switched into transistors Q3 and Q1, respectively. This keeps the current source terminals at about the same voltages for the various switch states, which may prevent undesirable variations in the output impedances thereof during the switching.

In FIG. 3A, switched capacitor band gap reference circuit 2A includes current source 43 conducting PTAT/R current I.sub.PT2 of magnitude I continuously flowing through conductor 37 and diode-connected PNP transistor Q2 to ground. If switch 49 is closed and switch 52 is open, current source 45 conducts PTAT/R current I.sub.PT7 of value 7I through conductor 39 and switch 49 to conductor 34 and through a transistor Q4 to ground. Current source 45 also supplies I.sub.PT7 to transistor Q1 through conductor 39 and switch 52 to conductor 20 when switch 49 is open and switch 52 is closed. Current source 44 continuously supplies PTAT/R current I.sub.PT1 of value I through conductor 20 and through diode-connected transistor Q1 to ground if switch 52 is open. Thus, if switch 52 is closed and switch 49 is open, then I.sub.PT1 +I.sub.PT7 flows through transistor Q1 to ground.

Current source 46 supplies PTAT/R current I.sub.PT3 through conductor 29 and diode-connected PNP transistor Q5 to ground to continuously bias the (+) input of operational amplifier 25 to the emitter-base voltage V.sub.BE5 of transistor Q5, to equalize the voltages on switches 55 and 26 so as to balance charge injection effects. (Alternatively, conductor 29 could be biased to any other convenient fixed reference voltage. For example, conductor 29 could be connected to conductor 37, in which case transistor Q5 could be eliminated.)

Conductor 12 of curvature correction circuit 3 is connected to the left terminal of capacitor C4, the right terminal of which is connected by summing conductor 24 to the (-) input of operational amplifier 25, to the left terminal of switch 60, and to one terminal of each of capacitors C1, C2, and C2A.

The left terminal of capacitor C1 is connected to conductor 20. The left terminal of capacitor C2A is connected to the left terminal of switch 61, the right terminal of switch 55, and to one terminal of switch 66. The other terminal of switch 66 is connected to ground. The left terminal of switch 55 is connected to conductor 37. The right terminal of capacitor C2 is connected to the left terminal of switch 26 and the right terminal of switch 54.

The output of operational amplifier 25 produces V.sub.OUT on conductor 27, which is connected to the left terminal of switch 4B, the right terminal of switch 60, and the right terminals of switches 26 and 61. The right terminal of switch 4B is connected by conductor 28A to one terminal of capacitor C5, the other terminal of which is connected to ground. The reference voltage V.sub.REF is produced on conductor 28A by the sample/hold circuit including sampling switch 4B and capacitor C5.

Note that the .DELTA.V.sub.BE voltage referred to above is produced across the emitter-base junction of transistor Q1, but the V.sub.BE voltage referred to above is produced across the emitter-base junction of transistor Q2 rather than transistor Q1 as in FIG. 2. The voltage V.sub.BE2 across transistor Q2 can be the same as or different than either of the voltages V.sub.BE11 (FIG. 3A) or V.sub.BE12 (FIG. 3C) produced across transistor Q1.

I.sub.PT0, I.sub.PT1, I.sub.PT2, I.sub.PT3, I.sub.PT4, and I.sub.PT5 all are scaled to have a value I of approximately 5 microamperes. I.sub.PT7 is scaled to have a value 7I of approximately 35 microamperes. I.sub.VBE/R is scaled to provide a V.sub.BE/R current of 5 microamperes to be added to I.sub.PT0

In FIG. 3A, switches 54 and 55 are actuated by "charging phase" signal .phi.1. Switch 60 is actuated (i.e., turned on) by a "settling phase" signal .phi.2. Switches 14, 50, 49, 52, 26 and one of 61 and 66 are actuated or turned on by a "reference phase" signal .phi.3. Switch 4B is turned on by an "update phase" signal .phi.4.

The V.sub.BE /R current source 41 and PTAT/R current sources 42-46 included within dotted line 40 in FIG. 3A are shown in more detail in the diagram of FIG. 5, subsequently described. The details of operational amplifier 25 are shown in more detail in FIG. 6.

The operation of the circuit of FIG. 3A is described with reference to FIGS. 3A-3D, which show the switch configurations for the .phi.1, .phi.2, .phi.3 and .phi.4 phases, respectively.

FIG. 3A shows the configuration of the various switches for charging phase .phi.1, as shown in FIG. 8. During charging phase .phi.1, switch 49 is open and switches 52 and 60 are closed, so the PTAT/R current I.sub.PT1 +I.sub.PT7 is equal to 8I, which flows through conductor 20 and transistor Q1 to ground to produce the voltage V.sub.BE11 across the emitter-base junction of transistor Q1. The PTAT/R current I.sub.PT2 of value I flows through conductor 37 and transistor Q2. (I can be 5 microamperes.) PTAT/R current I.sub.PT0 of value I flows from current source 42 through transistor Q3 to ground, producing a voltage V.sub.BE31 across its emitter-base junction.

With switch 14 open and switch 50 closed, a V.sub.BE/R current I.sub.VBE/R flows from current source 41 through transistor Q4 to ground. I.sub.VBE/R is a V.sub.BE/R current, rather than a 0TC/R current such as current source 13 of FIG. 2. (A V.sub.BE/R current is one established by applying a transistor V.sub.BE voltage across a resistor of resistance R, and hence has the same temperature coefficient as the V.sub.BE voltage.) Note that in FIG. 2, either switch 11 is on, directing I.sub.PTAT/R through transistor Q4, or switch 14 is on, directing I.sub.PTAT/R through transistor Q4, but they are never simultaneously on. In contrast, in FIG. 3A either the PTAT/R current of current source 42 (which corresponds to current source 10 in FIG. 3) flows through transistor Q3 or the currents of both PTAT/R current source 42 and V.sub.BE /R current source 41 flow through transistor Q3. Therefore, to get a zero temperature coefficient of the current flowing through transistor Q4 during .phi.3 in FIG. 3A, it is necessary to use a V.sub.BE /R rather than a 0TC/R current for current source 41.

The PTAT/R current I.sub.PT3 of value I from current source 46 flows through level shifting transistor Q5, to level-shift the inputs of operational amplifier 25 to the V.sub.BE5 voltage of transistor Q2, through which PTAT/R current I.sub.PT2 of value I flows. This results in matching of the charge injection of switches 54 and 55 with the charge injection of switch 60, and also avoids the requirement that the output V.sub.OUT on conductor 27 of amplifier 25 swing to zero volts when it is connected as a follower for offset correction and pre-charging, as subsequently described. At the end of charging phase .phi.1, capacitor C1 is charged to V.sub.BE11 -V.sub.BE5, capacitors C2 and C2A are charged to V.sub.BE2 -V.sub.BE5, and capacitor C4 is charged to V.sub.BE31 -V.sub.BE5.

Referring to FIG. 3B, during "settling phase" .phi.2, switches 54 and 55 are opened to sample V.sub.BE2, and switch 60 remains closed. The transient which occurs on conductor 24 at the trailing edges of .phi.1 (because of the switching that occurs there) is allowed to settle during .phi.2, as shown in FIG. 8, so that the transient does not disturb the generation of a .DELTA.V.sub.BE voltage on transistor Q1. This is important to obtaining accurate reproduction of the .DELTA.V.sub.BE voltage across transistor Q1, because when switches 54 and 55 are opened they couple charge through capacitances C2A and C2 into summing node 24. That causes a change in the voltage on summing node 24. This is shown by the "node 24" waveform in FIG. 7, and it perturbs the charges in capacitors C1 and C4. Since the .DELTA.V.sub.BE curvature correction voltage that is to be coupled by capacitor C4 into summing node 24 and feedback capacitor C2 is a critical part of the curvature corrected band gap voltage, it is desirable to let that variation on node 24 settle. (Alternatively, settling phase .phi.2 could be omitted in some cases, for example as in the embodiment of FIG. 2, wherein the reference phase .phi.2 is the same as the reference phase .phi.3 for FIGS. 3A-3C. Note that one of switches 66 and 61 (FIG. 3A) is closed, depending on which of the subsequently described operating or trim modes of operation is being performed.

Referring to FIG. 3C, switch 60 is opened and switch 26 is closed during reference phase .phi.3 as shown. Switch 52 is opened and switch 49 is closed, so the current I.sub.PT1 provides a PTAT/R current I through transistor Q1, resulting in the voltage V.sub.BE12 across its emitter-base junction. Switch 50 is opened and switch 14 is closed, so the current I.sub.PT0 +I.sub.VBE/R provides a 0TC/R current through transistor Q3, producing the voltage V.sub.BE32 across its emitter-base junction. If switch 66 is closed, capacitor C2A is charged to -V.sub.BE5 volts. The PTAT/R current I.sub.PT1 of value I flows through transistor Q1, producing thereon an emitter-base voltage V.sub.BE12. During reference phase .phi.3, capacitor C2 is connected as a feedback capacitor for amplifier 25, and therefore receives transfer charges from capacitors C1, C4 and C2A as a result of operational amplifier 25 varying V.sub.OUT to maintain the (-) and (+) inputs thereof at the same virtual ground voltage V.sub.BE5.

During normal operation, switch 61 is open, and switch 66 is closed during .phi.3 by clock signal .phi.3B to transfer the charge in capacitor C2A into feedback capacitor C2 to increase V.sub.OUT to a value equal to a scale factor determined by C2A multiplied by the band gap voltage. (The actual scale factor is equal to 1+C2A/C2.) However, during one of the trim operations subsequently described, switch 66 is opened and switch 61 is closed to connect capacitor C2A in parallel with feedback capacitor C2, while capacitor C1 is trimmed to adjust the voltage V.sub.OUT on conductor 27 to a value precisely equal to the band gap voltage of silicon, so the temperature coefficient of V.sub.OUT will be zero.

By the end of reference phase .phi.3, capacitor C1 is charged to V.sub.BE12 -V.sub.BE5, and capacitor C4 is charged to V.sub.BE32 -V.sub.BE5. Feedback capacitor C2 initially holds the charge corresponding to V.sub.BE32 -V.sub.BE5 from the .phi.2 settling phase, and now receives additional transfer charges from capacitors C1, C2A and C4 based on the differences in charges transferred to capacitor C2 between the end of settling phase .phi.2 and the end of reference phase .phi.3. Specifically, capacitor C2 receives transfer charges C1.multidot.(V.sub.BE11 -V.sub.BE2), C2A.multidot.(V.sub.BE2), and C4 (V.sub.BE31 -V.sub.BE32). Accordingly, the voltage across feedback capacitor C2 is given by the equation: ##EQU2##

This results in a voltage V.sub.OUT on conductor 27 at the output of amplifier 25 of: ##EQU3##

Note that neither V.sub.BE5 nor the amplifier offset voltage V.sub.OS appears in the expression for the output voltage V.sub.OUT. That is because the offset voltage of operational amplifier 25 is automatically cancelled by the above described switching technique. The cancellation occurs because feedback capacitor C2 is connected between conductor 37 and summing conductor 24 during charging phase .phi.1. This causes capacitor C2 to be charged to V.sub.BE2 minus the "virtual" voltage on summing conductor 24. The virtual voltage on summing conductor 24 is equal to V.sub.BE5 +V.sub.OS. Then, during reference phase .phi.3 feedback capacitor C2 is connected between summing conductor 24 and operational amplifier output conductor 27, which cancels both the offset voltage V.sub.OS and V.sub.BE5.

It is noteworthy that Eq. 2 has the appropriate form for a band-gap voltage reference circuit having curvature correction, wherein the sum of the capacitances of feedback capacitor C2 and capacitor C2A constitutes a scaling factor of the V.sub.BE voltage produced across the emitter-base junction of transistor Q2. The capacitance of capacitor C1 is a scale factor for the .DELTA.V.sub.BE voltage produced across transistor Q1. C4 constitutes a scale factor for the curvature correction term .DELTA.V.sub.BE developed across the emitter-base junction of transistor Q3 during the switching between .phi.2 and the end of .phi.3. The capacitance of capacitor C2 is a scale factor for the magnitude of V.sub.OUT.

During "update phase" .phi.4, switch 4B is closed to allow the output voltage V.sub.OUT of operational amplifier 25 to be updated onto a hold capacitor C5. The foregoing sequence of .phi.1, .phi.2, .phi.3 and .phi.4 may be repeated indefinitely.

FIG. 4 shows a more detailed implementation of the circuit shown in FIGS. 3A-D. The current sources shown in block 40 are the same as in FIGS. 3A-D. The various switches shown in FIGS. 3A-D are implemented by various MOSFETs designated by the same or similar reference numerals. In FIG. 4, additional trim capacitors C1', C1", C2' and C2A' are illustrated. A suitable buffer circuit 4D has its input connected to conductor 28A, and its output produces the curvature-corrected output reference voltage V.sub.REF on conductor 28. Buffer circuit 4D preferably is capable of driving a resistive load and/or a large load capacitance of 1-10 microfarads.

Capacitor C1 is adjusted by adjusting trimmable capacitors C1' and C1" in FIG. 4 so as to cause switched capacitor band gap reference circuit 1A to have zero drift value. This can be accomplished by selection of trim capacitor values from an array of capacitors represented in FIG. 4 by trimmable capacitors C1' and C1" that are selectively added to or removed from the effective capacitance of capacitor C1. Capacitor C1 may be trimmed electronically through a digital interface to the digital register or, for example, by cutting polycrystaline silicon resistor links with a laser beam. This can be accomplished by using digital data to control the trim by selecting capacitors from a trim array. Similarly, the output voltage V.sub.OUT is adjusted by adjusting the effective values of capacitors C2 and C2A by trimming the values of adjustable capacitors C2' and C2A'.

Referring again to FIG. 3A, during the manufacturing process capacitor C1 is trimmed first. The clock signal .phi..sub.3A is set to a "1" during .phi..sub.3 so that switch 61 in FIG. 3A (switches 61A and 61B in FIG. 4) is turned on (i.e., closed). The clock signal .phi..sub.3B is set to a "0" during .phi..sub.3 so that switch 66 is turned off (i.e., opened). Switch 26 is turned on. This connects capacitors C2 and C2A in parallel as a feedback network for amplifier 25. Capacitor C1 then is trimmed by providing an 8-bit digital word as an input to a capacitance trimming array 64 shown in FIG. 3A. The structure and operation of the capacitance trimming array 64 is subsequently described with reference to FIG. 10. Capacitor C1 is trimmed so as to set the voltage V.sub.OUT on conductor 27 to a value commonly referred to by those skilled in the art as the "magic number" approximately equal to the band gap voltage of silicon.

After the band gap voltage has been precisely established by trimming of C1 as described above, then .phi..sub.3B is set to a "1" and .phi..sub.3A is set to a "0" during phase .phi..sub.3, so that switch 61 is opened and switch 66 is closed. Then only feedback capacitor C2 is connected as a feedback network of amplifier 25. The closing of switch 66 causes capacitor C2A to function as a gain scaling capacitor so that the value of V.sub.OUT is equal to the product of a scaling factor (1+C2A/C2) determined by the capacitance of C2A multiplied by the established "magic number" band gap voltage achieved by the prior trimming of capacitor C1. This is true only if the sum of C2 and C2A is maintained constant. Capacitor C2A is trimmed by providing an 8-bit digital word as an input to trim array 62, which is shown in FIG. 10.

Capacitor C2 is simultaneously trimmed with capacitor C2A using trim array 62 such that the sum of the trimmed capacitors C2A and C2 is constant. The capacitance trim circuit array 62 of FIG. 10 accomplishes trimming of capacitors C2 and C2A such that the sum of their capacitances is constant by shifting the capacitance "trimmed" from one of C2 and C2A to the other.

Referring to FIG. 10, capacitance trim array 62 includes three terminals which are connected to conductors 24, 56, and 57, respectively, in FIG. 3A. The connections of capacitors C2 and C2A to conductors 24, 56, and 57 in FIG. 3A are indicated by dotted lines in FIG. 10. Eight N-channel MOSFETs 125-0,1 . . . 7 have their source electrodes connected to conductor 57. Their gates are connected to the B0,1 . . . 7 outputs, respectively, of a data register which is loaded with a digital word indicating the amount of capacitance trimming required. The desired trim code B0,1 . . . 7 can be permanently "burned in" using various well known techniques. The assignee of the present application accomplishes this by laser cutting of polycrystaline silicon conductors to establish the values of B0,1 . . . 7. The drain electrodes of MOSFETs 125-0,1 . . . 7 are connected to the first plates of capacitors 127-0,1 . . . 7, respectively, and also to the drain electrodes of P-channel MOSFETs 131-0,1 . . . 7, respectively, and also to the drain electrodes of N-channel MOSFETs 129-0,1 . . . 7, respectively.

Note that each of the capacitors 127-0,1 . . . 7 and 132-0,1 . . . 3 has a "first plate" with an adjacent numeral "1" and a "second plate" with an adjacent numeral "2". The second plates of capacitors 127-0,1 . . . 7 are connected to conductor 24. The source electrodes of MOSFETs 131-0,1 . . . 7 are connected to conductor 57. The source electrodes of MOSFETs 129-0,1 . . . 7 are connected to conductor 56. The digital signals B0, B1 . . . B7 are connected to the gate electrodes of MOSFETs 131-0,1 . . . 7 respectively, and also to the gate electrodes of MOSFETs 129-0,1 . . . 7, respectively. The corresponding pairs of N-channel MOSFETs 125-0,1 . . . 7 and P-channel MOSFETs 131-0,1 . . . 7 form eight CMOS transmission gate switches between conductor 57 and the first plates of capacitors 127-0,1 . . . 7, respectively. Capacitors 127-0,1 . . . 7 have capacitances of 6.5, 7, 8, 10, 7.5, 15, 30, and 60 femtofarads (FF), respectively.

Conductor 24 is connected to the second plates of capacitors 132-0,1 . . . 3, each of which has a capacitance of 6 FF. The first plates of capacitors 132-0,1 . . . 3 are connected to the drain electrodes of P-channel MOSFETs 134-0,1 . . . 3, respectively, to the drain electrodes of N-channel MOSFETs 135-0,1,2 . . . 3, respectively, and to the drain electrodes of N-channel MOSFETs 133-0,1 . . . 3, respectively. The source electrodes of MOSFETs 135-0,1 . . . 3 and the source electrodes of MOSFETs 134-0,1 . . . 3 are connected to conductor 24. The gate electrodes of MOSFETs 135-0,1 . . . 3 are connected to the digital signals B0, B1, B2, and B3, respectively. The source electrodes of MOSFETs 133-0,1 . . . 3 are connected to conductor 56. The digital signals B0, B1 . . . B3 are connected to the gate electrodes of MOSFETs 134-0,1 . . . 3, respectively, and to the gate electrodes of MOSFETs 133-0,1 . . . 3, respectively. The corresponding pairs of N-channel MOSFETs 134-0,1 . . . 3 and P-channel MOSFETs 134-0,1 . . . 3 form four CMOS transmission gate switches between conductors 57 and the first plates of capacitors 132-0,1 . . . 3, respectively.

If any of the signals B0,1 . . . 7 is switched to a "1", that turns a corresponding one of N-channel MOSFETs 125-0,1 . . . 7 on, and a complementary "0" level turns on the P-channel MOSFET of the corresponding CMOS transmission gate; the same "0" level turns off the corresponding one of N-channel MOSFETs 129-1, . . . 7. This connects the corresponding one of capacitors 127-0,1 . . . 7 in parallel with capacitor C2, and removes it from being connected in parallel with capacitor C2A. Similarly, if any of B0,1 . . . 7 is switched to a "0", that turns a corresponding one of N-channel MOSFETs 129-0,1 . . . 7 on, and the corresponding one of MOSFETs 125-0,1 . . . 7 will be turned off. That connects the corresponding one of capacitors 127-0,1 . . . 7 in parallel with capacitor C2A and removes it from being connected in parallel with capacitor C2.

Thus, the total trim capacitance of capacitors 127-0,1 . . . 7 is always distributed among capacitors C2 and C2A, so that the sum of the capacitances of capacitors C2 and C2A is constant and is unchanged by the trimming because the trimming switches various ones of trim capacitors 127-0,1 . . . 7 from being connected in parallel with one of capacitors C2 and C2A to being connected in parallel with the other.

Similarly, the total trim capacitance of capacitors 132-0,1 . . . 3 is always distributed among capacitors C2 and C2A, so the total capacitance of capacitors C2 and C2A is unaffected by switching any of trim capacitors 132-0,1 . . . 3 from being in parallel with one of capacitors C2 and C2A to being connected in parallel with the other.

The four least significant bits B0,1,2,3, in effect, allow a net differential amount of capacitance equal to the difference between two capacitors to be switched in parallel with either of capacitors C2 and C2A. If any of B0, B1, B2, or B3 is switched to a "1", then 6.5, 7, 8, or 10 FFs of capacitance of a corresponding one of capacitors 127-0,1,2,3 is switched from being connected in parallel with capacitor C2A to being connected in parallel with capacitor C2. At the same time, the 6 FF capacitance of the corresponding one of capacitors 132-0,1,2,3 is switched from being connected in parallel with capacitor C2 to being connected in parallel with capacitor C2A. Thus, the relatively small differential amount of capacitance between the one of capacitors 127-0,1,2,3 switched to being connected in parallel with capacitor C2 and the corresponding one of capacitors 132-0,1,2,3 switched to being not connected in parallel with capacitor C2 is in effect added to the capacitance of capacitor C2.

Similarly, if any of B0, B1, B2, or B3 is switched to a "0", then 6.5, 7, 8, or 10 FFs of capacitance of a corresponding one of capacitors 127-0,1,2,3 is switched from being connected in parallel with capacitor C2 to being connected in parallel with capacitor C2A. At the same time, the 6 FF capacitance of the corresponding one of capacitors 132-0,1,2,3 is switched from being connected in parallel with capacitor C2A to being connected in parallel with capacitor C2. Thus, the relatively small differential amount of capacitance between the one of capacitors 127-0,1,2,3 switched away from being connected in parallel with capacitor C2 and the corresponding one of capacitors 132-0,1,2,3 switched to being connected in parallel with capacitor C2 is in effect subtracted from the capacitance of capacitor C2. It should be noted that individual polycrystaline silicon capacitors of capacitance less than approximately 3 to 5 FF can not be manufactured with the manufacturing process used for making the curvature corrected switch capacitor band gap circuit described herein. Therefore, the above differential capacitive switching circuit and technique provides the advantage of effective trimming of the capacitance of polycrystaline silicon capacitors with a resolution of approximately 0.5 FFs by "differential" switching of amounts of capacitance as low as 0.5 FF to or away from a circuit node.

By maintaining the sum of the capacitances of capacitors C2 and C2A constant, the temperature drift of V.sub.OUT is independent of the output voltage. The can be accomplished by simultaneously trimming capacitors C2 and C2A.

Referring to FIG. 5, the current source circuit 40 of FIG. 4 is shown in more detail. Current source circuit 40 provides the various PTAT/R and V.sub.BE /R currents required by curvature-corrected switched capacitor reference circuit 1A. Current source generator 40 includes P-channel MOSFETs 69, 70, 79, 41, 42, 43, 44, 45 and 46 all having their source electrodes connected to a reference voltage V+. MOSFETs 41-46 correspond to current sources 41-46 in FIGS. 3A-D. The gate electrodes of MOSFETs 69, 70, and 42-46 are connected by conductor 71 to the output of an operational amplifier 82. The gate electrodes of MOSFETs 79 and 41 are connected by conductor 78 to the output of a second operational amplifier 77. The drain electrodes of MOSFETs 41-46 are connected to conductors 35, 36, 37, 38, 39, and 29, respectively. The drain electrode of MOSFET 69 is connected by conductor 72 to the (+) input of operational amplifier 71 and to one terminal of resistor 73. The other terminal of resistor 73 is connected to the emitter of a PNP diode-connected PNP transistor 74, the collector and base of which are connected to ground. The drain of MOSFET 70 is connected by conductor 75 to the (-) input of operational amplifier 82, the (-) input of operational amplifier 77, and to the emitter of a diode-connected PNP transistor 76, the base and collector of which are connected to ground. The drain of MOSFET 79 is connected by conductor 80 to the (+) input of operational amplifier 77 and to one terminal of resistor 81, the other terminal of which is connected to ground. Current source circuit 40 of FIG. 5 also provides the PTAT/R bias currents (not shown) needed by operational amplifier 25.

In circuit 40 of FIG. 5 MOSFETs 69 and 70 maintain equal currents through transistors 74 and 76. The emitter area of transistor 74 is 8 times that of transistor 76, and operational amplifier 82 provides feedback to the gate of MOSFETs 69 and 70 to keep conductors 72 and 75 at identical voltages. Therefore, a PTAT .DELTA.V.sub.BE voltage difference is developed across resistor 73 and a PTAT/R current flows through MOSFET 69, and hence through current mirror output MOSFETs 42-46 (because they are all driven by the same gate-to-source voltage). Operational amplifier 77 servos the voltage across resistor 81 to be equal to V.sub.BE current which generates a V.sub.VBE/R current which is mirrored from MOSFET 79 to MOSFET 41 through which I.sub.VBE/R flows.

Referring to FIG. 6, operational amplifier 25 is a simple single-stage folded cascode amplifier using P-channel MOSFET input devices. The circuitry designated by numeral 25A constitutes the ordinary folded cascode operational amplifier, and the circuitry 25B constitutes bias circuity for generating the bias voltages required. The gates of MOSFETs 90, 96, 103 and 106 are connected to power down control signals (not shown) to shut the circuit down during a power down mode.

The illustrated architecture was chosen for its ability to provide very high gain in a single stage, and also for its single dominant pole compensation characteristics. The individual bias voltages are generated from a suitable bias voltage generator circuit. Since the operation amplifier has a dominant pole compensated by an output capacitance, a large hold capacitor (e.g., 1-10 microfarads) can be used to significantly reduce the bandwidth of operational amplifier 25 during the update phase .phi.4, and therefore lower the noise of band gap reference circuit 1A.

While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make the various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. It is intended that all elements or steps which are insubstantially different or perform substantially the same function in substantially the same way to achieve the same result as what is claimed are within the scope of the invention.

For example, the .DELTA.V.sub.BE voltages referred to herein can be the difference in V.sub.BE voltages produced by forcing first and second scaled or equal currents through different transistors, rather than the same transistor (e.g., Q1 or Q3) as disclosed above. The curvature compensation technique of the present invention is applicable to either kind of switched capacitor band gap reference circuit.

Furthermore, the .DELTA.V.sub.BE3 curvature correction voltage developed across transistor Q3 of curvature correction circuit 3 does not necessarily need to be coupled to the same summing node 24 to which the .DELTA.V.sub.BE1 band gap voltage developed across transistor Q1 is coupled. FIG. 9 shows an alternative embodiment in which the curvature correction voltage A.sub.BE3 is produced across diode-connected transistor Q3 by causing I.sub.PTAT/R from current source 42 first to flow through transistor Q3 and then causing I.sub.VBE/R to also flow through transistor Q3 by turning on switch 14. This .DELTA.V.sub.BE3 curvature correction voltage change charges up capacitor C4, while switch 26A is closed. In this embodiment, band gap reference voltage circuit 2B includes amplifier 25 connected in a non-inverting configuration relative to the .DELTA.V.sub.BE generating circuitry including current sources 44 and 45, switch 52, and diode-connected transistor Q1. The emitter of transistor Q1 is connected to the non-inverting input of amplifier 25. Feedback capacitor C2 is connected between output conductor 27A and summing node 24A, which is connected to the (-) input of amplifier 25. Capacitor C3 is connected between summing node 24A and ground, and, with feedback capacitor C2, determines the gain of the band gap reference circuit. The curvature correction charge is acquired in capacitor C4 by causing I.sub.VBE/R and then I.sub.VBE/R +I.sub.PTAT/R to flow through transistor Q3. During the reference phase the curvature correction charge is transferred to feedback capacitor C2 and corrects the curvature of the band gap voltage being produced on conductor 27A in response to I and then I+NI flowing through transistor Q1.

The basic technique of acquiring charge on capacitor C4 and then transferring it to feedback capacitor C2 herein is the same as for other known switched capacitor band gap circuits. Therefore, the band gap circuit shown in FIG. 9 is considered to be a switched capacitor band gap reference circuit because switch 23 is operated to discharge capacitor C2 and because acquired charge is transferred from C4 to C2, even though the terminals of feedback capacitor C2 are not actually switched from one conductor to another.

It should be understood that the curvature correction voltage is not determined by either the magnitudes of the currents or the emitter area(s) of the transistor or transistors used to generate the two V.sub.BE voltages, the difference between which constitutes the .DELTA.V.sub.BE curvature correction voltage. What does cause the desired curvature correction voltage is that the two currents have different temperature coefficients. In the example of FIG. 2, one current is a PTAT/R current and the other is a 0TC/R current, whereas in the example of FIG. 3A one current is a V.sub.BE /R current and the other is a PTAT/R current. Other pairs of currents with different temperature coefficients also could be used instead.

The curvature compensation circuit 3 described herein also could be used to compensate for temperature-dependent variation in a transfer characteristic of an amplifier circuit that is not used in a band gap generator circuit. For example, in FIG. 2, the circuitry including current sources 16 and 18, switches 17, 19, 21, 23, capacitor C2A, and transistor Q1 could be deleted to provide such a compensated circuit.