Non-Volatile Memory Cell Having Dual Gate Electrodes

1. Field of the Invention

The present invention relates to a non-volatile semiconductor memory device, more particularly it relates to a non-volatile semiconductor memory having dual gate electrodes.

2. Description of the Related Art

A non-volatile semiconductor memory device is made to handle the write and read signals by shifting the threshold voltage by the charge existing in a charge storing mechanism formed in the insulating film.

For example, where the electrons are stored in the charge holding mechanism of a non-volatile semiconductor memory device of the N-type Metal-Oxide-Silicon (MOS) type, the threshold voltage is shifted to a positive direction. At the time of a read operation, a voltage is applied to the memory cell in question, but since the threshold voltage is larger than this applied voltage due to the electrons stored in this charge holding mechanism, the current flowing through the bit line is reduced. Conversely, where no electrons are stores in the charge holding mechanism or positive holes are stored, the threshold voltage is shifted to a negative direction, therefore the amount of the current flowing at the time of a read operation becomes large.

In this way, the basic operating principle of the nonvolatile semiconductor memory device lies in the use of the difference occurring in the current flowing through the transistor and making the magnitude of the current flowing at the time of a read operation correspond to the binary information.

Usually, the memory transistors are formed by a bulk process, impurities are introduced into channel parts and other portions, punch through or leakage between elements is prevented from occurring, and, at the same time, the threshold value is controlled.

However, disadvantages are caused due to the formation of the insulating film and the ion "implantation. To fix these, a high temperature heating step is necessary. Therefore, it is difficult to optimize the distribution of the impurities in the elements.

Further, in the sub-0.1 .mu.m generation of gate lengths, the statistical fluctuation in the concentration of the impurities to be introduced becomes relatively large - so much so as to exert an influence upon the actual device. Therefore, the control of the threshold voltage becomes further difficult.

Especially, the statistical fluctuation of the concentration of the impurity of the channel part is directly related to the fluctuation of the threshold voltage of the element, therefore a uniform circuit operation no longer can be carried out. Thus it has been said that the 0.1 .mu.m generation may become the limit of miniaturization of the bulk type of MOS transistors.

In order to avoid this, a MOS transistor having a configuration in which two gates sandwich a channel having a low impurity concentration using a silicon on insulator (SOI) structure (structure in which a silicon monocrystalline layer is isolated via an insulating layer) or the like (a so-called XMOS transistor) has been proposed.

Since the gate electrode used for writing/erasing and the gate electrode accessed at the time of a read operation are the same, the voltage is applied both to the gate electrodes of the transistor accessed at the time of reading data and the non-selected transistors connected to the same word line WI, W2, or the like. For this reason, the non-selected memory cells also enter into a weak writing state whereby the data is destroyed. This disadvantage, called the "reading disturbance", has been difficult to eliminate.

Further, the closer one gets to this generation of miniaturization, the more it is required that the program voltage of the non-volatile semiconductor memory device be reduced as much as possible and the more it is required to reduce the thickness of the insulating layer and the ferroelectric film constituting part of the charge holding mechanism. However, this conversely aggravates the effect of the reading disturbance.

Further, since the memory unit, the peripheral circuits, and the other circuits (logic etc.) have different structures of gate insulating layers, it is necessary to form the gate electrodes divided in two or three steps.

Further, the semiconductor layer is in an electrically floating state since it is completely surrounded by an insulator. For this reason, charges which are not absorbed by the source (for example, positive holes in the case of an NMOS) among the charges generated during the operation of the element, for example, the charges electrolytically dissociated due to collision at the drain end, are stored in the semiconductor layer, which changes the potential.

Such a change of the potential changes the threshold voltage and consequently becomes a cause preventing a uniform circuit operation.

An object of the present invention is to provide a non-volatile semiconductor memory device capable of miniaturization exceeding the limit of the above mentioned MOS transistors, in more detail, capable of suppressing fluctuation of a gate threshold voltage due to the fluctuation of a channel impurity concentration and reducing the soft write phenomenon (read disturb) due to reading and further having a good match with the manufacturing process of a logic circuit.

According to the present invention, there is provided a non-volatile semiconductor memory device comprising a semiconductor layer which has a first surface and a second surface opposing each other; a first insulating layer and a second insulating layer which are respectively formed on the first surface and second surface of the semiconductor layer; and a first gate electrode and a second gate electrode formed on the the first insulating layer and second insulating layer, respectively; a channel region defined in the semiconductor layer between the first and second gate electrodes; a charge storing means in the first insulating layer; wherein a

thickness of the semiconductor layer at the channel region is of an extent that the electric field of one surface of the semiconductor layer exerts an influence upon the other surface such that both a first gate threshold voltage measured with respect to the first gate electrode and a second gate threshold measured with respect to the second gate electrode are determined by a charge stored in the charge storing means.

Preferably, the first gate electrode is a write electrode; and the second gate electrode is a read electrode.

Preferably, the first insulating layer is constituted by a multi-layer Insulating film and has a charge storing function.

Preferably, a floating gate is buried in the first insulating layer and the charges are stored on or in the floating gate.

Preferably, at least the first insulating layer contains a ferroelectric layer.

Preferably, a source and drain region of the semiconductor layer is formed on a third insulating layer on a supporting substrate.

The semiconductor layer may be formed by epitaxial growth.

Preferably, the semiconductor layer is formed on the semiconductor substrate via a third insulating layer and, at the same time, connected to the semiconductor substrate via a connecting opening provided in one part of the insulating layer.

A plurality of channel regions may be connected in series in the semiconductor layer.

An electrode may be provided for draining the charges in the channel formed in the semiconductor layer.

Preferably, an electrode is provided for draining the charges in the channel formed in the semiconductor layer.

The lengths of the first gate electrode and second gate electrode in the channel direction may be different.

As stated above, a non-volatile semiconductor memory device according to the present invention comprises a non-volatile semiconductor memory device comprising a semiconductor layer which has a first surface and a second surface opposing each other; a first insulating layer and a second insulating layer which are respectively formed on the first surface and second surface of the semiconductor layer; and a first gate electrode and a second gate electrode formed on the first insulating layer and second insulating layer, respectively; a channel region defined in the semiconductor layer between said first and second gate electrodes; a charge storing means in the first insulating layer; wherein a thickness of the semiconductor layer at the channel region is of an extent that the electric field of one surface of the semiconductor layer exerts an influence upon the other surface such that both a first gate threshold voltage measured with respect to the first gate electrode and a second gate threshold measured with respect to the second gate electrode are determined by a charge stored in the charge storing means.

The thickness d such that the field of one surface of the semiconductor layer influences the other surface can be defined by for example the following approximation:

Note, where the impurity concentration N.sub.B of the channel region of the semiconductor layer approaches the intrinsic carrier concentration, the following equation is used:

In the equations,

e is the dielectric constant of the semiconductor layer;

D, is Fermi Level; q is the amount of the charge of an electron;

N.sub.B is the impurity concentration of the channel region of the semiconductor layer,

k is the Boltzmann constant,

T is an absolute temperature, and

n.sub.i is the intrinsic carrier concentration.

The above equations (1) and (1') show the spread of the depletion layer when the inversion layer starts to be formed in one of the surfaces of channel region of the semiconductor layer. This can be considered to be the thickness where the field of one surface of the semiconductor layer influences the other surface. For example, when it is assumed that the semiconductor layer is a monocrystalline silicon layer and the impurity concentration of the channel region is 1.4.times.10.sup.17 /cm.sup.3 or more, the thickness d found from equation (1) is about 100 nm or less.

Preferably the first gate electrode is used as the write electrode for storing the charges in the charge storing means in the first insulating layer, and the second electrode is used as the read electrode for the data.

The charge storing means can be constituted by a multi-layer insulating layer. As the multi-layer insulating layer having a charge storing function, an ONO film (laminate of a silicon oxide film, a silicon nitride film, and another silicon oxide film), an ON film (a laminate of a silicon oxide film and a silicon nitride film), etc. can be used. Alternatively, the charge storing means can be constituted by a floating gate buried in the first insulating layer or the second insulating layer. The floating gate can be constituted by a metal silicide, for example, polycrystallite silicon or tungsten silicide, a "polycidell film (laminate of a polycrystalline silicon film and a silicide film), or the like. Alternatively, it is also possible to include the ferroelectric layer in one or more of the first insulating layer and second insulating layer. As the ferroelectric layer, for example, a PZT (Pb--Zr--Ti--O), PLZT (Pb--La--Zr--Ti--O), Y,(SrBi.sub.2 Ta.sub.2 O.sub.3)1 PT (PbTi0.sub.3), etc. can be used.

Preferably the semiconductor layer is constituted by an SOI type semiconductor layer formed on an SOI type insulating layer.

It is also possible to form the semiconductor layer by epitaxial growth.

In the non-volatile semiconductor memory device according to the present invention, a so-called XMOS structure is adopted in which the first gate electrode and second gate electrode are laid on the two sides of the channel region of the semiconductor layer via the first insulating layer and the second insulating layer, respectively. For this reason, it becomes unnecessary to control the threshold voltage by the impurity concentration of the channel region as in the MOS transistor of the related art.

The threshold voltage is controlled by the impurity concentration of the channel region in a related art, and therefore a fluctuation of the threshold voltage of the gate electrode is caused due to the statistical fluctuation of the impurity concentration of the channel along with the miniaturization of the channel length. For this reason, in the structure of the related art, it has been said that about 0.1 IJm is the limit of a MOS transistor.

Contrary to this, since the present invention adopts a so-called XMOS structure, it is not affected by the statistical fluctuation of the impurity concentration of the channel. The threshold voltage can be controlled by the relationship of the work function of the first gate electrode, the second gate electrode, and the channel region. Therefore, miniaturization is possible even after the 0.1 .mu.m generation--which has been said to be the limit of miniaturization of the related art of bulk MOS transistors.

Further, in the present invention, since the two facing gate electrodes are made to share the functions of the write operation (and erasing) and the read operation, the soft write (erroneous writing) state of the non-selected cells during the read operation is reduced and the read disturb can be prevented. This is because, in the present invention, the disturbing field becomes for example a half or less in comparison with the case of the related art. In general, the amount of change of the charge is represented by an exponential function of the field in most cases, therefore, in the present invention, it is expected that the amount of disturbance can be further reduced to less than a half.

In the present invention, the first gate electrode on the first insulation where the charge storing means is formed becomes the write electrode. The charges are stored in the charge storing means by the write electrode. Due to the influence of the charges of the charge storing means , the threshold voltage of the read electrode on the opposite side the semiconductor layer changes. Due to the change of the threshold voltage, the read operation of the data is carried out. According to experiments by the pre-sent inventors, it was confirmed that: where the value obtained by converting the charges stored in the charge storing means to the voltage of the first gate electrode is defined as V.sub.g1, and the threshold voltage of the read electrode is defined as V.sub.thu, the change of that threshold voltage is represented by the following theoretical equation:

In the equation,

C.sub.in1 indicates the capacitance of the insulating layer between the first gate electrode and the semiconductor layer,

C.sub.inu indicates the capacitance between the semiconductor layer and the read electrode, and C.sub.si indicates the capacitance of the semiconductor. layer in which the channel region is formed.

According to experiments in which the semiconductor layer was formed on the surface of a P-type substrate via an insulating layer by using lateral Soil phase epitaxial technology and the electrodes were formed on the semiconductor layer via the insulating layer, the change of V.sub.thu with respect to the change of V.sub.g1, is about -0.18 (V.sub.thu changes by about 0.8V to about 0.45V during the period where V.sub.g1 changes from -1 to +1V). It was confirmed that this substantially coincided with the value by the above theoretical equation. Namely, it was confirmed that the threshold voltage of the read electrode on the opposite side of the semiconductor layer with respect to the write electrode sufficiently changed due to the influence of the charges of the charge storing means.

Further, in the present invention, the second insulating layer and the read gate electrode of either can be prepared in the same way as the process of preparing the other circuits such as the peripheral circuits. For this reason, there is a high process compatibility with the other circuits besides those of the memory cell portion. Further, in the present invention, since an electrode for draining the charges existing in the semiconductor layer is connected to at least one part of the semiconductor layer, the potential in the semiconductor layer can be kept at a predetermined value. Due to this, reproducible circuit operation is guaranteed.

These and other objects and features of the present invention will become more apparent from the following description of the preferred embodiments made with reference to the appended drawings, in which:

FIG. 1 is an equivalent circuit diagram of a nonvolatile memory array of a first embodiment;

FIG. 2A to FIG. 2F are process diagrams showing a manufacturing process of the non-volatile semiconductor memory shown in FIG. 1;

FIG. 3 is an equivalent circuit diagram of a nonvolatile memory array of a second embodiment;

FIG. 4 is a sectional view of principal parts of the non-volatile memory cell of a third embodiment;

FIG. 5 is an equivalent circuit diagram of the nonvolatile memory array of the third embodiment;

FIG. 6A to FIG. 6H are process diagrams showing the manufacturing process of the non-volatile semiconductor memory shown in FIG. 4;

FIG. 7 is a sectional view of the principal parts of the non-volatile memory call of a fourth embodime

FIG. 8 is a sectional view of the principal parts of the non-volatile memory call of a fifth embodiment;

FIG. 9A-to FIG. 9F are process diagrams showing the manufacturing process of the non-volatile semiconductor memory shown in FIG. 7;

FIG. 10 in a sectional view of the principal parts of the non-volatile memory cell of a sixth embodiment;

FIG. 11 is a sectional viewof the principal parts of the non-volatile memory cell of a seventh embodiment;

FIG. 12 is a sectional view of the principal parts of the non-volatile memory cell of an eighth embodiment;

FIG. 13 is a sectional viewof the principal parts of the nonvolatile memory cell of a ninth embodiment;

FIG. 16 is a sectional viewof the principal parts of the non-volatile memory call of a 10th embodiment'

FIG. 15 in a sectional viewof the principal parts of the non-volatile memory cell of an 11th embodiment

FIG. 16 is a sectional viewof the principal parts of the non-volatile memory cell of a 12th embodiment;

FIG. 17 is a sectional view of the principal parts of the non-volatile memory cell of a 13th embodiment;

FIG. 18 is an equivalent circuit diagram of the nonvolatile semiconductor memory shown in FIG. 17;

FIG. 19 is a sectional view of the principal Parts of the non-volatile memory cell of a 14th embodiment;

FIG. 20 is a sectional view of the principal parts of the non-volatile memory cell of a 15th embodiment;

FIG. 21 is a sectional view of theprincipal parts of the non-volatile memory cell of a 16th embodiment;

FIG. 22 is a sectional view of theprincipal parts of the non-volatile memory cell of a 17th embodiment;

FIG. 23 is a sectional view of the principal parts of the non-volatile memory cell of an 18th embodiment;

FIG. 24 is a sectional view of the principal parts of the non-volatile memory cell of a 19th embodiment;

FIG. 25 is a sectional view of the principal parts of the non-volatile memory cell of a 20th embodiment;

FIG. 26A is a view schematically showing the nonvolatile memory cell of a 21st embodiment by perspective view;

FIG. 26B is a view of the non-volatile memory cell of FIG. 26A seen from the front;

FIG. 26C is a view of the non-volatile memory cell of FIG. 26A seen from the side;

FIGS. 27A to 27J are views showing the manufacturing process of the non-volatile memory cell o the 21st embodiment by front views;

FIGS. 28A to 28i are views showing the manufacturing process of the non-volatile memory cell of the 21st embodiment by front views;

FIG. 29A is a view schematically showing the nonvolatile memory cell of a 22nd embodiment by a perspective view;

FIG. 29B is a view of the non-volatile memory cell of FIG. 29A seen from the front;

FIG. 29C is a view of the non-volatile memory cell of FIG. 29A seen from the side; and

FIG. 30 is a sectional view of the principal parts of the non-volatile memory cell of the 23rd embodiment.

A typical equivalent circuit diagram of a memory array of a non-volatile semiconductor memory device is shown in FIG. 1. The memory shown in FIG. 1 is a NOR type, in which word lines WI, W2 . . . and pairs of bit lines B1a, B1b; B2a, B2b; . . . are individually connected to respective memory cellsM1 . . . M4 . . . in the form of a matrix.

Below, the process of manufacturing a first embodiment of such a non-volatile semiconductor memory device will be shown (in this example a multi-layer insulating film, particularly an ONO film, is used in the charge storing mechanism).

As shown in FIG. 2A, first, a field insulating film (silicon oxide film) 4 is formed on the surface of a semiconductor substrate 2 constituted by a monocrystalline silicon substrate or the like by a LOCOS process.

Next, as shown in FIG. 2B, the impurity is introduced into the memory region by using an ion implantation method or the like.

Next, as shown in FIG. 2C, a lower layer film 6 (bottom oxide film) of the gate insulating layer, constituted by the ONO film, is formed.

Next, as shown in FIG. 2D, a silicon nitride film 8 in the gate insulating layer, constituted by an ONO film, or the like is deposited by using a chemical vapor deposition (CVD) process or the like.

Next, as shown in FIG. 2E, an upper layer silicon oxide film 10 of an ONO film is formed by thermally oxidizing the silicon nitride film.

Next, as shown in FIG. 2F, a gate electrode material layer is formed by a CVD process or the like. This is patterned to form a control gate 12.

Next, as shown in FIG. 2G, in order to form the peripheral circuits and the other parts, the ONO film at the position other than the memory cell portion is removed.

Next, as shown in FIG. 2H, the introduction of the impurity, formation of the gate oxide film 14, and the formation of the gate electrode 16 are carried out for the peripheral circuits and the other parts.

Next, as shown in FIG. 2I, a source-drain region 20 is formed on the surface of the semiconductor substrate 2 in a self-aligning manner with respect to the gate electrodes 12 and 16, an inter-layer insulating layer 17 is formed, and a take-out electrode 18 is attached to complete the device.

In a non-volatile semiconductor memory device configured in this way, where for example the data of the memory cell ml shown in FIG. 1 is read, the word line W1 is accessed. Usually, NMOS transistors are used for the transistors of a non-volatile semiconductor memory device, therefore a positive voltage is applied to the word line W1. At almost the same time, a current flowing between the bit line B1a and the bit line B1b is detected, and it is decided whether the data is "1" or "0".

Note that, in the usual bulk process (process of forming the elements on a bulk semiconductor substrate), the film structure of the gate insulating layer differs between the memory cell part and the peripheral circuit, but the gates are formed on the same surface.

Next, a non-volatile semiconductor memory device of a second embodiment will be shown in FIG. 3. Usually, the arrangement is the method of arrangement referred to as the "NAND type", in which word lines W1, W2, . . . and a pair of bit 3 lines B1y, B2y for the number of connected mentioned before are individually connected to the respective memory cells M.sub.11, M.sub.12, . . . M.sub.xy.

For the preparation of such a non-volatile memory device, a process similar to that for the above NOR type is used.

The operation of the non-volatile semiconductor memory device configured in this way is usually as follows.

In the read operation, the word line of the cell to be read is fixed to 0V and a sufficient voltage (hereinafter referred to as Vcc) is applied which makes all cell transistors become electrically conductive to the word lines other than this.When a positive voltage is applied to the bit line B1y, all cell transistors other than the cell to be read are in the electrically conductive state, therefore whether the current "flows" or "does not flow" through the bit line B2y is determined according to whether the selected cell transistor has reached the normally on or normally off state.

The states where the current "flows" and "does not flow" respectively correspond to "I" and "O". Further, Usually the erasing of the NAND type data is carried out in block units or all cells in the semiconductor chip.

This erasing is carried out by applying a sufficient voltage (hereinafter referred to as Vpp) to selective gate, well and substrate. Further bit line B11 and B21 is open.

As a result, electrons are introduced from the storing phenomenon (mechanism) to the semiconductor layer in which a channel is formed, therefore the cell transistor becomes a depletion type (normally on). Therefore, a writing of data is carried out to the desired cell transistor.

Where all cell transistors are normally on, so data ""0" is the written. In the data is writing, the word line for performing the writing is applied to Vpp and a bit line is fixed to 0V and a voltage which makes all cell transistors become electrically conductive to the selection gate SG2 and the word lines other than this.

Therefore, an electron is introduced to the charge storing mechanism, and this time, the cell transistor becomes an enhancement type (normally off type). Further, where the data is writing, Vpp is applied to the non-selected cell's word line, and introduced an electron to its charge-stored cell's charge stored mechanism. Therefore, non selective cell transistors function as depletion (normally on) type transistors.

In a third embodiment of the present invention, the non-volatile semiconductor memory device is configured by using an ONO film as the charge storing layer and by utilizing a so-called XMOS structure.

A sectional view of the principal parts of a memory cell in the non-volatile semiconductor memory device according to the present embodiment will be shown in FIG. 4.

As shown in FIG. 4, a non-volatile semiconductor memory device 22 according to the present embodiment has an SOI structure, in which an SOI type insulating layer 26 is formed on a supporting substrate 24, and an SOI type semiconductor layer 28 is formed on this SOI type insulating layer 26 in the form of an island. A first gate insulating layer 32 and a second gate insulating layer 34 are laid on the two sides of a channel region 30 of each semiconductor layer 28. Further, the first gate electrode 36 is laid on the first gate insulating layer 32 side and the second gate electrode 38 is laid on the second gate insulating layer 34 side. These are therefore located on the two sides of the channel region 30.

On the two sides of the channel region 30 of the semiconductor layer 28 along the plane direction, the source-drain regions 40 and 42 are formed in a self-aligning manner with respect to the second gate electrode 38. Further, interconnection layers 44 and 46 acting as bit lines are electrically connected to these source-drain regions 40 and 42 are formed on the insulating layer 26.

In the present embodiment, the first gate insulating layer 32 is constituted by an ONO film (three-layer film of silicon oxide film, silicon nitride film, and another silicon oxide film) and constitutes the charge storing layer. The first gate electrode 36 becomes the electrode for writing the data (also for the erasing of data; the same is true for the following), and the second gate electrode 38 becomes the electrode for reading the data.

In the present embodiment, the thickness of the semiconductor layer 28 is such that the electric field of one surface of the semiconductor layer 28 influences the electric field of the other surface. The thickness of the semiconductor layer 28 is concretely determined by the above equation (1) or (1'). Where for example the semiconductor layer is a silicon single crystal and the 10.sup.17 /CM.sup.3 impurity concentration of the channel region is or more, it is for example about 100 nm or less.

An equivalent circuit diagram of a memory cell of the non-volatile semiconductor memory device according to the present embodiment will be shown in FIG. 5. As shown in FIG. 5, the non-volatile semiconductor memory device 24 according to the present embodiment is of the NOR type, in which write word lines W1a, W2a . . . read word lines W1b, W2b . . . and pairs of bit lines B1a, B1b; B2a, B2b; . . . are individually connected to respective memory cells M1 . . . M4 . . . in the form of a matrix.

Next, an explanation will be made of an example of the manufacturing process of the non-volatile semiconductor memory device according to the present embodiment. First of all, as shown in FIG. 6A, a step difference 48 is formed on the surface of a semiconductor substrate 47 constituted by a silicon single crystal wafer, or the like, by using reactive ion etching (RIE), or the like, and a semiconductor layer projection 28a is formed in the form of an island.

Next, as shown in FIG. 6B, a silicon oxide film 50 is formed by a thermal oxidation method or the like, and a silicon nitride film 52 is formed on that silicon oxide film 50. The silicon nitride film 52 is formed by, for example, a CVD process. The thickness of the silicon oxide film 50 is not particularly limited, but for example may be about 1.0 to 3.0 nm The thickness of the silicon nitride film 52 is about 2.0 to 20.0 nm.

Thereafter, as shown in FIG. 6C, the surface of the silicon nitride film 52 is thermally oxidized, and a silicon oxide film 54 having a thickness of for example about 2.0 to 6.0 nm is formed. A first gate insulating layer 32 comprising an ONO film is formed by a silicon oxide film 54, a silicon nitride film 52, and a silicon oxide film 50.

Next, as shown in FIG. 6D, as the gate material which becomes the first gate electrode 36 is formed from, for example, a polycrystalline silicon film or "polycide" film by a CVD process or the like. This is etched to pattern the first gate electrode 36. Subsequently, the portion beneath the first gate electrode 36 other than the first gate insulating layer 32 is removed by etching. Of course, it is also possible to leave the silicon oxide film 54, the silicon nitride film 52, and the silicon oxide film 50.

Next, as shown in FIG. 6E, an SOI type insulating layer 26 is formed on the semiconductor substrate 47 on which the first gate electrode 36 is formed. This insulating layer 26 is constituted by silicon oxide formed by for example a CVD process.

Next, as shown in FIG. 6F, a supporting substrate 24 is bonded to the surface of the SOI type insulating layer 26. In actuality, a leveling polycrystalline silicon layer is deposited on the surface of the insulating layer 26 by a CVD process or the like and leveled by polishing the surface thereof by chemical mechanical polishing (CMP) or the like, and a supporting substrate 24 constituted by a silicon wafer or the like is bonded to that leveled surface. Thus, the method of forming the SOI structure according to the present embodiment is a so-called bonding SOI method.

Next, as shown in FIG. 6G, the assembly is turned upside-down from the state shown in FIG. 6F and the surface of the semiconductor substrate 47 is polished by a CMP process or the like until the surface of the insulating layer 26 is exposed. The SOI type semiconductor layer 28 constituted by the silicon single crystal is left in the part corresponding to the step difference 48 (semiconductor layer projection 28a). The thickness of the SOI type semiconductor layer 28 left on the SOI type insulating layer 26 is a thickness of an extent that the electric field of one surface of the semiconductor layer 28 influences electric field of the other surface and for example is about 100 nm or less.

Next, as shown in FIG. 6H, the second gate insulating layer 34 is formed on the surface of the semiconductor layer 28. This second gate insulating layer 34 is constituted by, for example, a silicon oxide film and is formed by a thermal oxidation or CVD process. The thickness of this second gate insulating layer 34 is not particularly limited, but for example is about 2.0 to 10.0 nm. Note that, it is also possible to introduce an impurity for adjustment of the threshold value into the semiconductor layer 28 before or after the formation of the second gate insulating layer 34, but in the present embodiment, the introduction of the impurity can be omitted by setting the difference of the work functions between the gate material and the semiconductor layer to an appropriate value.

Next, as shown in FIG. 4, as the gate material layer which becomes the second gate electrode 38, for example a polycrystalline silicon film or a "polycide" film is deposited on the second gate insulating layer 34 by a CVD process or the like, the gate material layer is patterned by RIE or the like, and therefore the second gate electrode 38 is formed. Next, ion implantation of the impurity is carried out in a self-aligning manner with respect to this second gate electrode 38 to form the source-drain regions 40 and 42 on the semiconductor layer 28. The conditions for the ion implantation are not particularly limited, but as is used as the impurity and the ion implantation is carried out under conditions of 40 to 80 KeV, 3.times.10.sup.15 to 5.times.10.sup.15 /cm.sup.2. The channel region 30 is formed in the semiconductor layer 28 just beneath of the second gate electrode 38 to which the impurity is not introduced.

Thereafter, the interconnection layers 44 and 46 connected to the source-drain regions 40 and 42 are formed by a polycrystalline silicon interconnection layer, an aluminum interconnection layer, an aluminum alloy interconnection layer, or the like.

By the process as described above, the memory cells of the non-volatile semiconductor memory device 22 shown in FIG. 4 are produced.

In the non-volatile semiconductor memory device according to the present embodiment, as shown in FIG. 5, where the writing/erasing o the data is carried out, the write voltage is applied to the first gate electrode 36 for writing through the write word lines W1a, W2a . . . This write voltage is not particularly limited, but is for example 5 to 9V. By the application of this write voltage, the charges are stored in the ONO film of the first gate insulating layer 32 constituting the charge storing layer. The electric field caused by these stored charges influences the electric field of the surface of the second gate insulating layer 34 of the semiconductor layer 28.

For this reason, by applying the read voltage to the first gate electrode 38 for reading shown in FIG. 4 through the read word lines W1b, W2b . . . shown in FIG. 5 at the time of reading data, the stored data can be read out. The read voltage is not particularly limited, but is for example about 0.7V.

In the structure of the non-volatile semiconductor memory device of the related art, the read electrode and the write electrode were the same, therefore there was a large possibility that erroneous writing (read disturb) would occur at the non-selected cells at a read operation of the data. in the present embodiment, the write electrode and the read electrode are different, therefore the inconvenience of reading disturbances etc. can be effectively prevented.

Further, the thickness of the second gate insulating layer 34 under the second gate electrode 38 which becomes the read electrode can be set relatively thick, i.e., about 6 to 8 nm, without considering the write voltage so as to be process compatible with the peripheral transistors. Conversely the thickness of the silicon oxide film in the first gate insulating layer 32 can be made thick to about 4 nm or less in order to reduce the write voltage.

Further, in the present embodiment, a so-called XMOS structure is adopted in which the first gate electrode 36 and the second gate electrode 38 are respectively laid on the two sides of the channel region 30 of the semiconductor layer 28 via the first gate insulating layer 32 and the second gate insulating layer 34 . For this reason, the threshold voltage can be controlled, without the influence of the statistical fluctuation of the channel impurity concentration, by the relationship of the work function with the first gate electrode 36, the second gate electrode 38, and the channel region 30.Miniaturization is possible even after the 0.1 nm generation--which has been said to be the limit of miniaturization of the related art of bulk MOS transistors.

Furthermore, in the present embodiment, it is possible to fabricate the second gate insulating layer 34 and the second gate electrode 38 in the same way as the manufacturing process of the other circuits such as the peripheral circuit. For this reason, there is a high process compatibility with the circuits other than the memory cell portion.

In the fourth embodiment of the present invention, as shown in FIG. 7, a non-volatile semiconductor memory device 22a is produced in the same way as that for the first embodiment except that the first gate insulating layer 32a is constituted by a single layer not having a charge storing function such as a silicon oxide film and the second gate insulating layer 34a is constituted by a charge storing layer such as an ONO film.

In the present embodiment, the first gate electrode 36 becomes the read gate electrode, and the second gate electrode 38 becomes the write gate electrode.

In the present embodiment, the same action and effect as those by the third embodiment can be expected.

In the fifth embodiment of the present invention, as shown in FIG. 8, the non-volatile semiconductor memory device is configured using a floating gate 56 as the charge storing layer and using an XMOS structure as a prerequisite.

As shown in FIG. 8, the non-volatile semiconductor memory device 22b according to the present embodiment has an SOI structure, in which the SOI type insulating layer 26 is formed on the supporting substrate 24, and the SOI type semiconductor layers 28 and 76 are formed on this SOI type insulating layer 26 in the form of islands. The semiconductor layer 28 is the SOI type semiconductor layer for the memory cell portion, and the semiconductor layer 76 is the SOI type semiconductor layer for the peripheral circuit portion. A first gate insulating layer 59 and a second gate insulating layer 62 are laid at the two sides of each semiconductor layer 28 in the memory cell portion. Further, the first gate electrode 36a is laid on the first gate insulating layer 59 side, and the second gate electrode 38a is laid on the second gate insulating layer 62 side. These are therefore located on the two sides of the channel region 30.

The first gate insulating layer 59 comprises an intermediate insulating layer 58 and a tunnel insulating layer 60. A floating gate 56 is interposed between these films 58 and 60. In the present embodiment, the floating gate 56 becomes the charge storing layer.

In the memory cell portion, on the two sides of the channel region 30 of the semiconductor layer 28 along the plane direction, the source-drain regions 40 and 42 are formed in a self-aligning matching manner with respect to the second gate electrode 38. Further, interconnection layers 66 and 68, which become the bit lines electrically connected to these source-drain regions 40 and 42, are formed on the inter-layer insulating layer 64.

In the peripheral circuit portion, a gate insulating layer 63 is formed on only one surface of the semiconductor layer 76, and the gate electrode 74 for the peripheral circuit is laid thereon. Source-drain regions 80 and 82 are formed on the semiconductor layer 76 so as to be located on the two sides of the gate electrode 74, and the portion just beneath of the gate electrode becomes the channel region 78. Interconnection layers 70 and 72 formed on the inter-layer insulating layer 64 are connected to the source-drain regions 80 and 82. The transistor of the peripheral circuit portion is constituted by the usual MOS transistor. Of course, in the transistor of the peripheral circuit portion, it is also possible, if the gate insulating film and the gate electrode are formed beneath of the channel region 78, to form a so-called XMOS structure. Where the impurity is not introduced into the channel region, it is rather preferred that the transistor of the peripheral circuit portion be given the XMOS structure.

In the present embodiment, in the memory cell portion, the first gate electrode 36a becomes the electrode for writing the data, and the second gate electrode 38a becomes the electrode for reading the data.

In the present embodiment, the thickness of the semiconductor layer 28 is a thickness such that the elective field of one surface of the semiconductor layer 28 influences the electric field at the other surface. The thickness of the semiconductor layer 28 is concretely determined by the above equation (1) or (1'). where for example the semiconductor layer is made--of a silicon single crystal, it is for example about 100 nm or less.

In the present embodiment, the semiconductor layer 76 of the peripheral circuit portion is formed simultaneously with the semiconductor layer 28 of the memory cell portion, and the thicknesses thereof are substantially the same. Further, the gate insulating layer 63 and the gate electrode 74 of the peripheral circuit portion can be formed by the same process as that for the second gate insulating layer 62 and second gate electrode 38a of the memory cell portion.

The equivalent circuit diagram of the memory cell of the non-volatile semiconductor memory device according to the present embodiment has a structure shown in FIG. 5 similar to the third embodiment.

As shown in FIG. 5, the non-volatile semiconductor memory device according to the present embodiment is of the NOR type, in which write word lines W1a, W2a . . . read word lines W1b, W2b . . . , and pairs of bit lines B1a, B1b; B2a, B2b; . . . are individually connected to respective memory cells M1 . . . M4 . . . in the form of a matrix.

Next, an explanation will be made of an example of the manufacturing process of the non-volatile semiconductor memory device according to the fifth embodiment.

First of all, as shown in FIG. 9A, a step difference 48 is formed on the surface of a semiconductor substrate 47 constituted by a silicon single crystal wafer or the like by using RIB or the like, and semiconductor layer projections 28a and 76a are formed in the form of islands.

Next, as shown in FIG. 9B, a tunnel insulating layer 60 constituted by a silicon oxide film or the like is formed by using the thermal oxidation method or the like. Next, as shown in FIG. 9C, a gate material layer which becomes the floating gate 56 is formed on the tunnel insulating layer 60, an intermediate insulating layer 58 is formed thereon, and the gate material layer acting as the first gate electrode 36a which serves as the control gate is formed on this intermediate insulating layer 58. Thereafter, patterning is carried out to obtain the floating gate 56 and the first gate electrode 36a. This process is the same as the process of a usual floating gate type memory cell.

The intermediate insulating layer 58 can be, for example, an ONO film. The floating gate 56 is constituted by polycrystalline silicon formed by, for example, a CVD process. The first gate electrode 36a can be constituted by for example a polycrystalline silicon film or a "polycide" film.

Next, as shown in FIG. 9D, the SOI type insulating layer 26 is formed on the semiconductor substrate 47 on which the first gate electrode 36a is formed. This insulating layer 26 is constituted by silicon oxide formed by, for example, a CVD process.

Next, the supporting substrate 24 is bonded to the surface of the SOI type insulating layer 26. In actuality, a leveling polycrystalline silicon layer is deposited on the surface of the insulating layer 26 by CVD or the like and leveled by polishing the surface thereof by CMP or the like.The supporting substrate 24 constituted by a silicon wafer or the like is bonded to that leveled surface. Thus, the method of forming the SOI structure according to the present embodiment is a so-called bonding SOI method.

Next, as shown in FIG. 9E, the assembly is turned upside-down from the state shown in FIG. 9D and the surface of the semiconductor substrate 47 is polished by the CMP process or the like until the surface of the insulating layer 26 is exposed. The SOI type semiconductor layers 28 and 76 constituted by the silicon single crystal are left in the part corresponding to the step difference 48 (semiconductor layer projections 28a and 76a). The thickness of the SOI type semiconductor layer 28 left on the SOI type insulating layer 26 is a thickness such that the electric field of one surface of the semiconductor layer 28 influences the electric field at the other surface and is for example about 100 nm or less. Where it is intended to change the thickness of the semiconductor layer 28 and the thickness of the semiconductor layer 76, it is sufficient to change the height of the projection 28a and the projection 76a in the step shown in FIG. 9A.

Next, as shown in FIG. 9F, the usual transistor process is used to form a second gate insulating layer 62 and a gate insulating layer 63 for the peripheral circuit portion on the surfaces of the semiconductor layers 28 and 76. A second gate electrode 38a and a gate electrode 74 for the peripheral circuit portion are formed on them, respectively. The second gate insulating layer 62 and the gate insulating layer 63 for the peripheral circuit portion are constituted by silicon oxide formed by, for example, thermal oxidation and can be simultaneously formed by the same manufacturing process. Further, the second gate electrode 38a and the gate electrode 74 for the peripheral circuit portion are constituted by a polycrystalline silicon film or a "polycide" film etc. formed by, for example, the CVD process and can be simultaneously formed by the same manufacturing process. Where there also exists a logic circuit portion other than the peripheral circuit portion, the gate insulating layer and the gate electrode of the transistor thereof can be simultaneously produced by the same process.

Next, the ion implantation of the impurity is carried out in a self-aligning manner with respect to the second gate electrode 39a and the gate electrode 74 for the peripheral circuit portion to form the source-drain regions 40 and 42 in the semiconductor layer 28 and the source-drain regions 80 and 82 in the semiconductor layer 76. It is also possible to change the conditions of the ion implantation between the memory cell portion and the peripheral circuit portion. The semiconductor layer 28 just beneath the second gate electrode 38a to which the impurity is not introduced becomes the channel region 30. Further, the channel region 78 is formed in the semiconductor layer 76 just beneath the gate electrode 74 for the peripheral circuit portion.

Next, as shown in FIG. 8, an inter-layer insulating layer 64 is formed on the SOI structure on which the gate electrodes 38a and 74 are formed.A contact hole is formed in this inter-layer insulating layer 64, and interconnection layers 66, 68, 70, and 72 connected to the source-drain regions 40, 42, 80, and 82 are formed. These interconnection layers are constituted by a polycrystalline silicon interconnection layer, an aluminum interconnection layer, an aluminum alloy interconnection layer, or the like.

By the process as described above, the respective memory cells and peripheral circuits of the non-volatile semiconductor memory device 22b shown in FIG. 8 are produced.

The present embodiment has the same action and effect as those of the third embodiment except the charges are stored in the floating gate 56.

In the sixth embodiment of the present invention, as shown in FIG. 10, the non-volatile semiconductor memory device is produced in the same way as the fifth embodiment except that, in the memory cell portion, a gate insulating layer 84 constituted by a single layer of a silicon oxide film or the like is laid between the first gate electrode 36b and the semiconductor layer 28, and an intermediate insulating layer 58b, a floating gate 56b, and a tunnel insulating layer 60b are formed between the second gate electrode 38b and the semiconductor layer 28.

In the present embodiment, the first gate electrode 36b becomes the read gate electrode, and the second gate electrode 38b becomes the write gate electrode.

In the present embodiment, the same action and effect those by the fifth embodiment can be expected.

In the seventh embodiment of the present invention, as shown in FIG. 11, the non-volatile semiconductor memory device is constituted using a ferroelectric layer 92 and a floating gate 56 and with a so-called XMOS structure as the prerequisite. The non-volatile semiconductor memory device according to the present embodiment is a modification of the non-volatile semiconductor memory device having a floating gate type XMOS structure shown in FIG. 8, where the ferroelectric layer 92 is laid on the intermediate insulating film between the floating gate 56c and the first gate electrode 36c. This will be explained in detail below. Note, explanations of portions common to the above embodiments will be partially omitted.

As shown in FIG. 11, the present embodiment has an SOI structure, in which the SOI type insulating layer 26 is formed on the supporting substrate 24, and the SOI type semiconductor layer 28 is formed on this SOI type insulating layer 26 in the form of an island. On the two sides of the channel region 30 of the semiconductor layer 28, a first gate insulating layer 93 and a second gate insulating layer 96 are laid. Further, a first gate electrode 36c is laid on the first gate insulating layer 93 side and a second gate electrode 38c is laid on the second gate insulating layer 96 side. These are therefore located on the two sides of the channel region 30.

On the two sides of the channel region 30 of the semiconductor layer 28 along the plane direction, the source-drain regions 40 and 42 are formed in a self-aligning manner with respect to the second gate electrode 38c. Further, the interconnection layers 44 and 46 acting as the bit lines electrically connected to these source-drain regions 40 and 42 are formed on the insulating layer 26.

In the present embodiment, an insulating layer 90, a floating gate 56c, a buffer layer 94, and a ferroelectric layer 92 are laid on the first gate insulating layer 93 from the channel region 30 side. This laminate structure located beneath of the channel region 30 is metal-ferroelectric metal-insulator semiconductor (MFMIS) structure. This is a non-volatile memory structure utilizing high speed polarization inversion and residual polarization of the ferroelectric layer 92. The direction of polarization of the ferroelectric layer 92 changes in accordance with the voltage of +V or -V from the first gate electrode 36c, which is the write gate electrode.The charge is generated in the floating gate 56c, and the storage of the data becomes possible.

In the present embodiment, the thickness of the semiconductor layer 28 is a thickness such that the electric field of one surface of the semiconductor layer 28 influences the electric field of the other surface. The thickness of the semiconductor layer 28 is concretely determined by the above equation (1) or (1'). Where for example the semiconductor layer is made of a silicon single crystal, it is for example about 100 nm or less.

In the present embodiment, the ferroelectric layer 92 is not particularly limited, but may be constituted by for example PZT (Pb--Zr--Ti--O), PLZT (Pb--La--Zr--Ti--O), Y.sub.1 (SrBi.sub.2 Ta.sub.2 O.sub.9)1 or PT (PbTi0.sub.3) . The buffer layer 94 is for holding the crystallinity of the ferroelectric layer 92 and does not always have to be provided. The buffer layer 94 can be made of a selenium oxide (SeO.sub.2) film for PT, a platinum (Pt) film, a ruthenium oxide (Ru0.sub.2) film, and a two-layer structural film of iridium/iridium oxide (Ir/IrO.sub.2) for PZT, PLZT, and Y.sub.1, and so on. As the floating gate 56c, for example, a polycrystalline silicon film can be used. As the insulating layer 90, for example, silicon oxide can be used. As the first gate electrode 36c, a polycrystalline silicon film, tungsten film, "polycide" film, etc. can be used. As the second gate electrode 38c, a polycrystalline silicon film, "polycide" film, etc. can be used. As the second gate insulating layer 96, silicon oxide etc. can be used.

Note that where the buffer layer is a conductive film such as platinum or Ir/IrO.sub.2 the buffer layer can be used as the floating gate. In this case, a contamination preventing/bonding layer constituted by TiN or the like is provided between the floating gate 56c and the insulating layer 90. Further, where the floating gate is made of polycrystalline silicon, an alloy-formation preventing layer such as TiN is provided with the buffer layer such as Pt, IrO.sub.2, or RuO.sub.2.

The present embodiment has the same action and effect as those by the fifth embodiment except that the writing and erasing of the data are carried out from the first gate electrode 36c by utilizing the polarization inversion of the ferroelectric layer 92 and the residual polarization thereof. Particularly, in the present embodiment, since the ferroelectric layer is utilized, the write voltage required for the polarization inversion can be set lower than that comprising the floating gate alone. This also contributes to the lowering of the voltage.

As shown in FIG. 12, the eighth embodiment of the present invention is a modification of the embodiment shown in FIG. 11, where the first gate electrode 36d provided beneath the channel region 30 becomes the read electrode, and the second gate electrode 38d provided on the channel region 30 becomes the write and erasing electrode. A first gate insulating layer 93d comprised by a single layer is provided between the first gate electrode 36d and the channel region 30, and a ferroelectric layer 92d, a buffer layer 94d, a floating gate 56d, and an insulating layer 96d are provided between the second gate electrode 38d and the channel region 30.

In the present embodiment, the same action and effect as those by the fifth embodiment can be expected. in the ninth embodiment of the present invention, as shown in FIG. 13, the non-volatile semiconductor memory device is configured using an ON film, that is, a laminate of a Silicon nitride film and a silicon oxide film, as the charge storing layer, and with a so-called XMOS structure as a prerequisite.

The non-volatile semiconductor memory device according to the present embodiment is a modification of the non-volatile semiconductor memory device having a MONOS type XMOS structure shown in FIG. 4, in which the first gate insulating layer 32e made of the ONO film is used in place of the ONO film shown in FIG. 4. The ONO film has a charge storing function similar to the ONO film. Below, this will be explained in detail. Note, explanations of portions common to the above embodiments will be partially omitted.

As shown in FIG. 13, the present embodiment has an SOI structure, in which the SOI type insulating layer 26 is formed on the supporting substrate 24, and the SOI type semiconductor layer 28 is formed on this SOI type insulating layer 26 in the form of an island. On the two sides of the channel region 30 of the semiconductor layer 28, a first gate insulating layer 32e and a second gate insulating layer 34e are laid. Further, a first gate electrode 36e is laid on the first gate insulating layer 32e side and a second gate electrode 38e is laid on the second gate insulating layer 34e side. These are therefore located on the two sides of the channel region 30.

On the two sides of the channel region 30 of the semiconductor layer 28 along the plane direction, the source-drain regions 40 and 42 are formed in a self-aligning manner with respect to the second gate electrode 38c. Further, the interconnection layers 44 and 46 acting as the bit lines electrically connected to these source-drain regions 40 and 42 are formed on the insulating layer 26.

In the present embodiment, the first gate insulating layer 32e located beneath the channel region 30 is constituted by an ON film having a charge storing flnction. The rest of the structure is similar to that of the embodiment shown in FIG. 4.

The present embodiment has the same action and effect as those by the first embodiment shown in FIG. 4.

As shown in FIG. 14, the 10th embodiment of the present invention is a modification of the embodiment shown in FIG. 13, in which the first gate electrode 36f provided beneath of the channel region 30 becomes the read electrode, and the second gate electrode 38f provided on the channel region 30 becomes the write and erasing electrode. A first gate insulating layer 32f comprised of a single layer is provided between the first gate electrode 36f and the channel region 30, and a second gate insulating film 34f made of an ON film is provided between the second gate electrode 38f and the channel region 30.

In the present embodiment, the same action and effect as those by the fourth embodiment can be expected.

The 11th embodiment of the present invention is a modification of the third to 10th embodiments. it is an embodiment wherein the SOI structure is formed by a method other than the bonding method.

As shown in FIG. 15, in the present embodiment, the ion implantation is carried out in a predetermined pattern so that the peak of the n-type or p-type impurity concentration comes at the position of a predetermined depth from the surface of a semiconductor substrate 100 constituted by a silicon single crystal wafer or the like so as to form a first gate electrode 102. Thereafter, the ion implantation of 02 is carried out for the entire surface so that the peak of concentration is obtained at a depth located on the gate electrode 102, thereby forming an SOI type insulating layer 104.

For this reason, a semiconductor layer 106 constituted by a silicon single crystal is formed on the insulating layer 104. By utilizing this semiconductor layer, a non-volatile semiconductor memory device utilizing an XMOS structure according to the third to tenth embodiments may be formed.

In the present embodiment as well, a memory cell structure of the non-volatile semiconductor memory device disclosed in any one of the third to tenth embodiments can be realized. In addition, the manufacturing process thereof is easier than the bonding SOI method.

The 12th embodiment of the present invention is a modification of the third to 10th embodiments. It is an embodiment for obtaining a SOI structure by a method other than the bonding method as shown in FIG. 16.

An insulating layer 108 in which a first gate electrode 110 is buried in a predetermined pattern is formed on a semiconductor substrate 100 constituted by a silicon single crystal wafer or the like. A contact hole 112 exposed at the surface of the semiconductor substrate 100 is formed in the insulating layer 108. Thereafter, an amorphous silicon film is grown by a CVD process, and a semiconductor layer 114 is crystallized from the bottom portion of the contact hole 112 by using the lateral SOI phase epitaxial technique.

Next, on the semiconductor layer 114, a gate insulating layer 116 constituting the second gate insulating layer, a floating gate 118, an intermediate insulating layer 120, and a second gate electrode 122 are formed. The materials of the gate electrode, the floating gate, and the insulating layer are the same as those of the above embodiments.

In the present embodiment, the memory cell structure of the non-volatile semiconductor memory device disclosed in any of the third to tenth embodiments can be realized. In addition, the manufacturing process thereof is easier than the bonding SOI method.

Note that, in the above embodiments, the memory cell structure of the non-volatile semiconductor memory device was made of the NOR type, but the present invention can be applied also to a NAND type.

Below, an explanation will be made of some embodiments of a non-volatile semiconductor memory device of a NAND type to which the present invention is applied.

In the 13th embodiment of the present invention, similar to the third embodiment, the NAND type non volatile semiconductor memory device is constituted by using the ONO film as the charge storing layer and utilizing the so-called XMOS structure.

A sectional view of the principal parts of one memory cell in the non-volatile semiconductor memory device according to the present embodiment will be shown in FIG. 17.

As shown in FIG. 17, a non-volatile semiconductor memory device 202 according to the present embodiment has an SOI structure, in which an SOI type insulating layer 206 is formed on a supporting substrate 204, and a plurality (eight in the present embodiment) of SOI type semiconductor layers 208 are formed on this SOI type insulating layer 206 in a connected state. On the two sides of the channel region 210 of each semiconductor layer 208, a first gate insulating layer 212 and a second gate insulating layer 214 are laid. Further, a first gate electrode 216 is laid on the first gate insulating layer 212 Bide and a second gate electrode 218 is laid on the second gate insulating layer 214 side. These are therefore located on the two sides of the channel region 210.

On the two sides of the channel region 210 of the semiconductor layer 208 along the plane direction, the source-drain regions 220 and 222 are formed in a self-aligning manner with respect to the second gate electrode 218. Further, the interconnection layers 224 and 226 acting as the bit lines electrically connected to these source-drain regions 220 and 222 are formed on the insulating layer 206. Note that, the structure is one wherein the source-drain regions 220 and 222 between adjoining memory cells are commonly used (connected in series), and respective channel regions 210 are connected.

In the present embodiment, the first gate insulating layer 212 is constituted by an ONO film (three-layer film of a silicon oxide film, a silicon nitride film, and another silicon oxide film) and constitutes the charge storing layer. The first gate electrode 216 becomes the electrode for writing the data (also for erasing the data; the same is true also for the following), and the second gate electrode 218 becomes the electrode for reading the data.

In the present embodiment, the thickness of the semiconductor layer 208 is a thickness such that the electric field of one surface of the semiconductor layer 208 influences the electric field of the other surface. The thickness of the semiconductor layer 208 is concretely determined by the above equation (1) or (1'). Where, for example, the semiconductor layer is a silicon single crystal and the impurity concentration of the channel region is 10.sup.7 /cm.sup.3 or more, the thickness of the semiconductor layer is, for example, about 100 nm or less.

An equivalent circuit diagram of the memory cell of the non-volatile semiconductor memory device according to the present embodiment will be shown in FIG. 18. As shown in FIG. 18, in the non-volatile semiconductor memory device according to the present embodiment, write word lines WN1a, WN2a MN8a, and read word lines WN1b, WN2b . . . MN8b are individually connected to respective memory cells MN1 . . . M8 . . . , and a bit line BN1a is connected to the memory cell MN8 and a bit line BN1b is connected to the memory cell MN1.

The manufacturing process of the non-volatile semiconductor memory device according to the present embodiment is substantially the same as that of the third embodiment, except that each memory cell of the nonvolatile semiconductor memory device 22 shown in FIG. 17 is produced only by changing the mask for forming the step difference on the surface of the semiconductor substrate constituted by the silicon single crystal wafer or the like, interconnections, and mask for the contacts.

In the non-volatile semiconductor memory device according to the present embodiment, as shown in FIG. 18, where writing/erasing data, the write voltage is applied to the first gate electrode 216 for writing through the write word lines WN1a, WN2a, WN8a. This write voltage is not particularly limited, but is for example 5 to 9V. By the application of this write voltage, the charges are stored in the ONO film of the first gate insulating layer 212 constituting the charge storing layer. The electric field by these stored charges influences the electric field of the surface of the second gate insulating layer 214 of the semiconductor layer 208.

For this reason, at the time of reading the data, by applying the read voltage to the third gate electrode 218 for reading shown in FIG. 17 through the read word lines WN1b, WN2b, . . . , WN8b shown in FIG. 18, the stored data can be read out. The read voltage is not particularly limited, but is for example 0.7v.

As mentioned before, in the structure of the nonvolatile semiconductor memory device of the related art, the read electrode and the write electrode were the same.Therefore, there was a large possibility of erroneous writing (read disturb) in the non-selected cells at the time of reading of the data. In the present embodiment, the electrode for writing and the electrode for reading are different, so the inconvenience of read disturb etc. can be effectively prevented.

Further, the thickness of the second gate insulating layer 214 beneath the second gate electrode 218 which becomes the read electrode is made process compatible with the peripheral transistors, therefore it can be constituted relatively thick to about 6 to 8 nm without considering the write voltage. Conversely the thickness of the silicon oxide film in the first gate insulating layer 212 can be made thin to about 4 nm so as to reduce the write voltage.

Further, in the present embodiment, a so-called XMOS structure is adopted where the first gate electrode 216 and the second gate electrode 218 are laid at the two sides of the channel region 210 of the semiconductor layer 208 via the first gate insulating layer 212 and the second gate insulating layer 214, respectively. For this reason, the threshold voltage can be controlled by the relationship of the work functions with the first gate electrode 216, the second gate electrode 218, and the channel region 210 without being influenced by the statistical fluctuation of the channel impurity concentration. Therefore, miniaturization is possible even after the 0.1 .mu.m generation--which has been said to be the limit of miniaturization of the related art of bulk MOS transistors.

Furthermore, in the present embodiment, it is possible to fabricate the second gate insulating layer 214 and the second gate electrode 218 in the same manner as the Process for fabricating the other circuits such as the peripheral circuits. For this reason, there is a high process compatibility also with the circuits other than the memory cell portion.

In the 14.sup.th embodiment of the present invention, as shown in FIG. 19, a non-volatile semiconductor memory device 202a is produced in the same way as that for the 13.sup.th embodiment except that a first gate insulating layer 212a is constituted by a film comprised of a single layer not having a charge storing function such as a silicon oxide film, and a second gate insulating layer 214a is constituted by a charge storing layer such as an ONO film.

In the present embodiment, the first gate electrode 216 becomes the read gate electrode and the second gate electrode 218 becomes the write gate electrode.

In the present embodiment, the same action and effect as those by the 13.sup.th embodiment can be expected.

In the 15.sup.th embodiment of the present invention, as shown in FIG. 20, a NAND type non-volatile semiconductor memory device is configured by using a floating gate 236 as the charge storing layer and using an XMOS structure as a prerequisite.

As shown in FIG. 20, the non-volatile semiconductor memory device 202b according to the present embodiment has an SOI structure, in which an SOI type insulating layer 206 is formed on the supporting substrate 204, and an 901 type semiconductor layer 208 is formed on this SOI type insulating layer 206 in a connected state. On the two sides of the channel region 210 of each semiconductor layer 208, a first gate insulating layer 239 and a second gate insulating layer 242 are laid. Further, a first gate electrode 216a is laid on the first gate insulating layer 239 side, and a second gate electrode 218a is laid on the second gate insulating layer 242 side. These are therefore located on the two sides of the channel region 210.

The first gate insulating layer 239 comprises an inter-layer insulating layer 238 and a tunnel insulating layer 240. A floating gate 236 is interposed between these films 238 and 240. in the present embodiment, the floating gate 236 becomes the charge storing layer.

On the two sides of the channel region 210 of the semiconductor layer 208 along the plane direction, the source-drain regions 220 and 222 are formed in a self-aligning manner with respect to the second gate electrode 218. Further, the interconnection layers 246 and 248 act as the bit lines electrically connected to these source-drain regions 220 and 222 and are formed on the inter-layer insulating layer 244. Note that, the structure is one wherein the source-drain regions 220 and 222 between adjoining memory cells are commonly used (connected in series), and respective channel regions 210 are connected.

In the present embodiment, in the memory cell portion, the first gate electrode 216a becomes the electrode for writing the data, and the second gate electrode 218a becomes the electrode for reading the data.

In the present embodiment, the thickness of the semiconductor layer 208 is a thickness such that the elective field of one surface of the semiconductor layer 208 influences the electric field of the other surface. The thickness of the semiconductor layer 208 is concretely determined by the above equation (1) or (1') and is, for example, about 100 nm or less where the semiconductor layer is made of a silicon single crystal.

An equivalent circuit diagram of the memory cell of the non-volatile semiconductor memory device according to the present embodiment exhibits the structure shown in FIG. 18 similar to the 13.sup.th embodiment.

The manufacturing process of the non-volatile semiconductor memory device according to the present invention is substantially the same as that of the third embodiment except the step of manufacturing the peripheral circuit portion. Each memory cell of the nonvolatile semiconductor memory device 202b shown in FIG. 20 is produced only by changing the mask for forming the step difference on the surface of the semiconductor substrate constituted by the silicon single crystal wafer or the like, interconnections, and the mask for the contacts.

The present embodiment has the same action and effect as those of the 13th embodiment except the charges are stored in the floating gate 236.

In the 16th embodiment of the present invention, as shown in FIG. 21, the non-volatile semiconductor memory device is produced in the same way as the 15th embodiment except that a gate insulating layer 270 constituted by a silicon oxide film comprised by a single layer or the like is laid between the first gate electrode 216b and the semiconductor layer 208, and an inter-layer insulating layer 238b, a floating gate 236b, and a tunnel insulating layer 240b are formed between the second gate electrode 218b and the semiconductor layer 208.

In the present embodiment, the first gate electrode 216b becomes the read gate electrode, and the second gate electrode 218b becomes the write gate electrode.

In the present embodiment, the same action and effect as those of the 15th embodiment can be expected.

In the 17th embodiment of the present invention, as shown in FIG. 22, the non-volatile semiconductor memory device is configured by using a ferroelectric layer 282 and a floating gate 236 and with a so-called XMOS structure as a prerequisite. The non-volatile semiconductor memory device according to the present embodiment is a modification of the non-volatile semiconductor memory device having a floating gate type XMOS structure shown in FIG. 19, wherein the ferroelectric layer 282 is laid on the inter-layer insulating film between the floating gate 236c and the first gate electrode 216c. This will be explained in detail below. Note, explanations of portions common to the above embodiments will be partially omitted.

As shown in FIG. 22, the present embodiment has an SOI structure, in which an SOI type insulating layer 206 is formed on the supporting substrate 204, and an SOI type semiconductor layer 208 is formed on this SOI type insulating layer 206 in a connected state. On the two sides of the channel region 210 of the semiconductor layer 208, a first gate insulating layer 283 and a second gate insulating layer 286 are laid. Further, a first gate electrode 216c is laid on the first gate insulating layer 283 side and a second gate electrode 218c is laid on the second gate insulating layer 286 side. These are therefore located on the two sides of the channel region 210.

On the two sides of the channel region 210 of the semiconductor layer 208 along the plane direction, the source-drain regions 220 and 222 are formed in a self-aligning manner with respect to the second gate electrode 218c. Further, the interconnection layers 246 and 248 acting as the bit lines electrically connected to these source-drain regions 220 and 222 are formed on the interlayer insulating layer 244. Note that, the structure is one wherein the source-drain regions 220 and 222 between adjoining memory cells are commonly used (connected in series), and respective channel regions 210 are connected.

In the present embodiment, an insulating layer 280, a floating gate 236c, a buffer layer 284, and a ferroelectric layer 282 are laid on the first gate insulating layer 283 from the channel region 210 side. This laminate structure located beneath the channel region 210 is the MFMIS structure mentioned before. It is a non-volatile memory structure utilizing the high speed polarization inversion and residual polarization of the ferroelectric layer 282. In the floating gate 236c, the direction of polarization of the ferroelectric layer 282 changes in accordance with the voltage of +V or -V from the first gate electrode 216c which serves as the gate electrode for writing.The charge is generated in the floating gate 236c, and the storage of the data becomes possible.

In the present embodiment, the thickness of the semiconductor layer 208 is a thickness such that the electric field of one surface of the semiconductor layer 208 influences the electric field of the other surface. The thickness of the semiconductor layer 208 is concretely determined by the above equation (1) or (1'). Where,for example, the semiconductor layer is made of a silicon single crystal, the thickness is about 100 nm or less.

In the present embodiment, the ferroelectric layer 282 is not particularly limited, but similar to the seventh embodiment, it is constituted by, for example, PZT (Pb--Zr--Ti--O), PLZT (Pb--La--Zr--Ti--O), Y.sub.1 (SrBi.sub.2 Ta.sub.2 0.sub.9), or PT (PbTi0.sub.3). The buffer layer 284 is for holding the crystallinity of the ferroelectric layer 282 and does not always have to be provided. The buffer layer 284 can be made of a selenium oxide (Seo.sub.2) film for PT, a platinum (Pt) film, a ruthenium oxide (Ru0.sub.2) film, and a two-layer structural film of iridium/iridium oxide (Ir/lr0.sub.2) for the PZT, PLZT, and Y.sub.1, and so on. As the floating gate 236c, for example, a polycrystalline silicon film can be used. As the insulating layer 280, for example, silicon oxide can be used. As the first gate electrode 216c, a polycrystalline silicon film, tungsten film, "polycide" film, Pt film, etc. can be used. As the second gate electrode 218c, a polycrystalline silicon film, "polycide" film, etc. can be used. As the second gate insulating layer 216, silicon oxide etc. can be used.

Note that, in the case where the buffer layer is a conductive film such as platinum or Ir/Ir0.sub.2, the buffer layer can be used as the floating gate. In this case, a contamination preventing/bonding layer constituted by TiN or the like is provided between the floating gate 236c and the insulating layer 280. Further, where the floating gate is made of polycrystalline silicon, an alloy-formation preventing layer such as TiN is provided with the buffer layer such as Pt, Ir0.sub.2, or Ru0.sub.2.

The present embodiment has the same action and effect as the 11th embodiment except the writing and erasing of the data are carried out from the first gate electrode 216c by utilizing the polarization inversion of the ferroelectric layer 282 and the residual polarization thereof. Particularly, since the present embodiment utilizes the ferroelectric layer, the write voltage required for the polarization inversion can be set lower than that comprising the floating gate alone. This also contributes to the lowering of voltage.

As shown in FIG. 23, the 18th embodiment of the present invention is a modification of the embodiment shown in FIG. 22, in which the first gate electrode 216d provided beneath of the channel region 210 becomes the read electrode, and the second gate electrode 218d provided on the channel region 210 becomes the write and erasing electrode. A first gate insulating layer 283d comprised of a single layer is provided between the first gate electrode 216d and the channel region 210, and a ferroelectric layer 282d, a buffer layer 284d, a floating gate 236d, and an insulating layer 286d are provided between the second gate electrode 218d and the channel region 210.

In the present embodiment, the same action and effect as those of the 17th embodiment can be expected.

In the 19th embodiment of the present invention, as shown in FIG. 24, the non-volatile semiconductor memory device is configured using an ON film, that is, a laminate film of a silicon nitride film and a silicon oxide film, as the charge storing layer, and with a so-called XMOS structure as a prerequisite. The non-volatile semiconductor memory device according to the present embodiment is a modification of the non-volatile semiconductor memory device having a MONOS type XMOS structure shown in FIG. 17 in which the first gate insulating layer 212e made of the ON film is used in place of the ONO film shown in FIG. 17. The ON film has the charge storing finction similar to the ONO film. Below, this will be explained in detail. Note, explanations of portions common to the above embodiments will be partially omitted.

As shown in FIG. 24, the present embodiment has an SOI structure, in which an SOI type insulating layer 206 is formed on the supporting substrate 204, and an SOI type semiconductor layer 208 is formed on this SOI type insulating layer 206 in a connected state. On the two sides of the channel region 210 of the semiconductor layer 208, a first gate insulating layer 212e and a second gate insulating layer 214e are laid. Further, a first gate electrode 216e is laid on the first gate insulating layer 212e side and a second gate electrode 218e is laid on the second gate insulating layer 214e side. These are therefore located on the two sides of the channel region 210.

On the two sides of the channel region 210 of the semiconductor layer 208 along the plane direction, the source-drain regions 220 and 222 are formed in a self-aligning manner with respect to the second gate electrode 218c. Further, the interconnection layers 224 and 226 act as the bit lines electrically connected to these source-drain regions 220 and 222, and are formed on the insulating layer 206. Note that, the structure is one wherein the source-drain regions 220 and 222 between adjoining memory cells are commonly used (connected in series), and respective channel regions 210 are connected.

In the present embodiment, the first gate insulating layer 212e located beneath the channel region 210 is constituted by an ON film having the charge storing function. The rest of the configuration is similar to that of the embodiment shown in FIG. 17.

The present embodiment has the same action and effect as the 13th embodiment shown in FIG. 17.

As shown in FIG. 25, the 20th embodiment of the present invention is a modification of the embodiment shown in FIG. 24 in which the first gate electrode 216f provided beneath of the channel region 210 becomes the read electrode, and the second gate electrode 218f provided on the channel region 210 becomes the write and erasing electrode. A first gate insulating layer 212f comprised of a single layer is provided between the first gate electrode 216f and the channel region 210, and a second gate insulating film 214f made of an ON film is provided between the second gate electrode 218f and the channel region 210.

In the present embodiment, the same action and effect as the 14th embodiment can be expected.

The 21st embodiment of the present invention is a modification of the third to 20th embodiments. It is an embodiment where the electrode for draining the charges out of the semiconductor layer 28 (hereinafter referred to as the draining electrode) is provided. Here, an explanation will be made of the configuration and manufacturing process thereof in comparison with the third embodiment.

FIG. 26A schematically shows by a perspective view the structure of one memory cell where the draining electrode is formed with respect to a NOR type non-volatile semiconductor memory device having an XMONOS structure having an ONO film as the charge storing layer. FIG. 26B is a view of the cell of FIG. 26A seen from the front, and FIG. 26C is a view of the cell of FIG. 26A seen from the side.

As shown in FIGS. 26A to 26C, the non-volatile semiconductor memory device 22c according to the present embodiment has an SOI structure, in which an SOI type insulating layer 26 is formed on the supporting substrate (24), and SOI type semiconductor layers 28 are formed on this SOI type insulating layer 26 in the form of islands at predetermined intervals. A draining electrode 300 for draining charges existing in the semiconductor layer 28 partially connected to the negative side of the semiconductor layer 28 is formed in the SOI insulating layer 26.

On the two sides of the channel region 30 of the semiconductor layer 28, a first gate insulating layer 32 and a second gate insulating layer 34 are laid. Further, a first gate electrode 36 is laid on the first gate insulating layer 32 side and a second gate electrode 38 is laid on the second gate insulating layer 34 side. These are therefore located on the two sides of the channel region 30.

On the two sides of the channel region 30 of the semiconductor layer 28 along the plane direction, the source-drain regions 40 and 42 are formed in a self-aligning manner with respect to the second gate electrode 38. Further, the interconnection layers 44 and 46 act as the bit lines electrically connected to these source-drain regions 40 and 42 and are formed on the insulating layer 26.

In the present embodiment, since the draining electrode 300 for draining the charges existing in the semiconductor layer 28 is provided, the potential of the semiconductor layer 28 can be kept constant, whereby uniform circuit operation is guaranteed.

Note that, in the present embodiment, the first gate insulating layer 32 is constituted by an ONO film (three-layer film of a silicon oxide film, a silicon nitride film, and another silicon oxide film) and constitutes the charge storing layer. The first gate electrode 36 becomes the electrode for writing the data (also for erasing the data, the same is also true for the following), and the second gate electrode 38 becomes the electrode for reading the data.

Also, in the present embodiment, the thickness of the semiconductor layer 28 is a thickness such that the electric field of one surface of the semiconductor layer 28 influences the electric field of the other surface. The thickness of the semiconductor layer 28 is concretely determined by the above equation (1) or (1'). Where for example the semiconductor layer is a silicon single crystal and the impurity concentration of the channel region is 10.sup.17 /cm.sup.3 or more, the thickness is, for example, about 100 nm or less.

Next, an explanation will be made of one example of the method of producing the non-volatile semiconductor memory device according to the present embodiment.

First of all, as shown in FIG. 27A and FIG. 28A, the step difference 28 is formed on the surface of the semiconductor substrate 47 constituted by the silicon single crystal wafer or the like by using RIE or the like, and the semiconductor layer projection 28a is formed in the form of an island.

Next, as shown in FIG. 27B and FIG. 28B, the silicon oxide film 302 is formed by using the thermal oxidation method or the like, and a contact hole 302a reaching one part of one surface of the step difference 48 is formed in this silicon oxide film 302.

Thereafter, as shown in FIG. 27C and FIG. 28C, the electrode material is deposited in the contact hole 302a and on the silicon oxide film 302 and patterning is carried out by etching by using a mask to form the draining electrode 300.

Next, as shown in FIG. 27D and FIG. 28D, the silicon oxide film 302 of the portion other than the portion just beneath the drawing electrode 300 is removed by using the same mask.

Next, as shown in FIG. 27E and FIG. 28E, a silicon oxide film is formed by using the thermal oxidation method or the like, and a silicon nitride film is formed on that silicon oxide film. The silicon nitride film is formed by, for example, a CVD process. The thickness of the silicon oxide film is not particularly limited, but is, for example, about 1.0 to 3.0 nm. The thickness of the silicon nitride film is about 2.0 to 20.0 nm.

Thereafter, the surface of the silicon nitride film is thermally oxidized to form a silicon oxide film having a thickness of, for example, about 2.0 to 6.0 rm. The first gate insulating layer 32 comprising the ONO film is constituted by the silicon oxide film, the silicon nitride film, and the other silicon oxide film.

Next, as shown in FIG. 27F and FIG. 28F, the gate material which becomes the first gate electrode 36 may be, for example, a polycrystalline silicon film or "polycide" film which is formed by CVD or the like and is etched for the patterning of the first gate electrode 36. Subsequently, the portion beneath of the first gate electrode 36 other than the first gate insulating layer 32 is removed by etching. Of course, it is also possible to leave the ONO film.

Next, as shown in FIG. 27G and FIG. 28G, an SOI type insulating layer 26 is formed on the semiconductor substrate 47 on which the first gate electrode 36 is formed. This insulating layer 26 is constituted by silicon oxide formed by for example a CVD process.

Next, as shown in FIG. 27H and FIG. 28H, the supporting substrate 24 is bonded to the surface of the SOI type insulating layer 26. In actuality, a leveling polycrystalline silicon layer is deposited on the surface of the insulating layer 26 by CVD or the like and leveled by polishing the surface thereof by CMP or the like.The supporting substrate 24 is constituted by a silicon wafer or the like and is bonded to that leveled surface. Thus, the method of forming the SOI structure according to the present embodiment is a so-called bonding SOI method.

Next, as shown in FIG. 271 and FIG. 28I, the assembly is turned upside-down and the surface of the semiconductor substrate 47 is polished by the CMP process or the like until the surface of the insulating layer 26 is exposed. The SOI type semiconductor layer 28 constituted by the silicon single crystal is left at the part corresponding to the step difference 48 (semiconductor layer projection 28a). The thickness of the SOI type semiconductor layer 28 left on the SOI type insulating layer 26 is a thickness such that the electric field of one surface of the semiconductor layer 28 influences the electric field of the other surface and, for example, is about 100 nm or less.

Next, as shown in FIG. 27J and FIG. 28J, the second gate insulating layer 34 is formed on the surface of the semiconductor layer 28. This second gate insulating layer 34 is constituted by, for example, a silicon oxide film and formed by a CVD process or the like. The thickness of this second gate insulating layer 34 is not particularly limited, but for example is about 2.0 to 10.0 nm. Note that, it is also possible to introduce an impurity for adjustment of the threshold value into the semiconductor layer 28 before or after the formation of the second gate insulating layer 34, but in the present embodiment, the introduction of the impurity can be omitted by setting the difference of the work functions between the gate material and the semiconductor layer to an appropriate value.

Next, as the gate material layer which becomes the second gate electrode 38, for example, a polycrystalline silicon film or the "polycide" film is deposited on the second gate insulating layer 34 by a CVD process or the like. The gate material layer is patterned by RIE or the like to form the second gate electrode 38. Next, the ion implantation of the impurity is carried out in a self-aligning manner with respect to this second gate electrode 38 to form the source-drain regions 40 and 42 on the semiconductor layer 28. The conditions for the ion implantation are not particularly limited, but As is used as the impurity, and the ion implantation is carried out under conditions of 40 to 80 KeV, 3.times.10.sup.15 to 5.times.10.sup.15 /CM.sup.2. The channel region 30 is formed in the semiconductor layer 28 just beneath the second gate electrode 38 to which the impurity is not introduced.

Thereafter, the interconnection layers 44 and 46 connected to the source-drain regions 40 and 42 are formed by a polycrystalline silicon interconnection layer, aluminum interconnection layer, aluminum alloy interconnection layer, or the like.

By the process as described above, the memory cells of the non-volatile semiconductor memory device 22c shown in FIG. 26A and FIG. 26C are produced.

In the non-volatile semiconductor memory device according to the present embodiment, in addition to the effect of the third embodiment, since the draining electrode 300 for draining the charges existing in the semiconductor layer 28 is provided, the potential of the semiconductor layer 28 can be freely set, whereby there is an advantage that uniform circuit operation can be guaranteed.

In the 22nd embodiment of the present invention, as shown in FIGS. 29A to 29C, a non-volatile semiconductor memory device 22nd embodiment is produced similar to the 21st embodiment except that the first gate electrode 36a is formed so as to bypass the draining electrode 300a, the formation of the draining electrode 300a and the formation of the ONO film and the back surface gate are reversed in order, and the back surface gate mask is slightly changed.

In the present embodiment, the same action and effect as those of the 21st embodiment can be expected.

The 23rd embodiment of the present invention is a modification of the third to 12th embodiments. Here, the structure thereof is shown in FIG. 30 in comparison with the third embodiment.

In the present embodiment, the first gate electrode 36g formed in the SOI type insulating layer 26 is not positively processed to the same size as that of the second gate electrode 38, which exerts an influence-upon the design rule, but is formed larger than the second gate electrode 38.

Specifically, in the plane direction of the channel region 30, it is formed so that the region overlapping the source-drain diffusion layers 40 and 42 of the first gate electrode 36g becomes larger than the second gate electrode 38.

The rest of the structure is the same as that of FIG. 4. In the present embodiment, the same action and effect as those of the fourth embodiment can be expected.